JP3661334B2 - Minority carrier lifetime measurement method and semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for measuring the lifetime of minority carriers in a semiconductor device, and more particularly to a method for measuring the lifetime of minority carriers in a semiconductor device having an SOI structure in which a single crystal silicon layer is stacked on an insulating film.
[0002]
A MOSFET with a silicon on insulator structure (hereinafter abbreviated as SOI structure) is characterized by low parasitic capacitance, and therefore consumes less power. When applied to a DRAM, the pit line capacitance is reduced and the MOSFET operates at high speed. Is possible.
[0003]
However, the SOI structure has a problem that the lifetime of minority carriers at the buried oxide film and the silicon interface is short. If the lifetime is short, the reverse leakage current of the pn junction becomes large, causing problems such as an increase in power consumption and deterioration in charge retention characteristics of the DRAM.
[0004]
For this reason, in the SOI structure, it is necessary to quantitatively monitor the lifetime of minority carriers.
Under the circumstances as described above, there is a demand for a method for measuring the lifetime of minority carriers capable of accurately measuring the lifetime of minority carriers in the SOI layer.
[0005]
[Prior art]
The time until the minority carriers generated in the conventional SOI layer recombine and disappear, that is, the minority carrier lifetime, is generally measured by irradiating the SOI layer with an electromagnetic wave having a wavelength of 800 nm to 1,000 nm. The time-dependent change of the minority carrier concentration is performed by exciting the carriers and measuring the reflection intensity of the microwave irradiated to the SOI layer.
[0006]
For the measurement of minority carrier concentration using such microwaves, see, for example, “Microwave Techniques in Measurement of Lifetime in Germanium”, Journal of Applied Physics, Vol. 30, N0.7, pp. 1054-1060 (1959). Has been described.
[0007]
[Problems to be solved by the invention]
In the conventional minority carrier lifetime measurement method described above, it is known that visible light reaches a depth of about several tens of μm when visible light is irradiated onto the SOI layer.
[0008]
When the SOI layer is irradiated with visible light, the visible light reaches the support substrate of the SOI layer, and minority carriers are excited also in this support substrate portion. Therefore, the lifetime of the minority carriers excited only in the SOI layer is reduced. There was a problem that it could not be measured accurately.
[0009]
The present invention aims to provide a method for measuring the lifetime of minority carriers that makes it possible to easily and easily measure the lifetime of minority carriers excited only in the SOI layer from the above situation. It is.
[0010]
[Means for Solving the Problems]
Measurement of the minority carrier lifetime of the present invention, p-type a p ⁺ layer and the n ⁺ layer was formed on the SOI layer, the p ⁺ layer and the n ⁺ layer and the respective p ⁺ layer pad electrode and the n ⁺ pad In a method for measuring the minority carrier lifetime in a semiconductor device having a metal wiring layer connected to a layer electrode, a charge measuring device is provided between the n ⁺ layer pad electrode and the ground, and the p ⁺ layer pad electrode is connected to the ground. When the ions are implanted into the SOI layer between the p ⁺ layer and the n ⁺ layer, the amount of charge collected in the n ⁺ layer pad electrode is measured by the charge measuring device, and the ion implantation position is measured. The lifetime of minority carriers in the SOI layer is calculated based on the relationship between the collected charge amount and the SOI layer.
[0011]
That is, in the present invention, as shown in FIG. 1, an insulating film 2 is formed on the surface of the support substrate 1, an SOI layer 3 composed of a p layer is formed on the surface of the insulating film 2, and the surface of the SOI layer 3 is formed. A p ⁺ layer 4 and an n ⁺ layer 5 are formed, a charge measuring device 8 is provided between the n ⁺ layer 5 and the ground, and ions 7 are formed in the SOI layer 3 between the p ⁺ layer 4 and the n ⁺ layer 5. Is injected into the SOI layer 3 and the support substrate 1, but since the insulating film 2 is formed between the SOI layer 3 and the support substrate 1, the minority carriers are excited by the support substrate 1. Minority carriers do not affect the measurement of the charge measuring device 8, and the lifetime of minority carriers excited only in the SOI layer 3 can be measured.
[0012]
In this case, the relationship between the distance between the ion irradiation position and the diffusion layer, that is, the n ⁺ layer, and the collected charge amount collected by the charge measuring device is as shown in FIG. Since the charge amount decreases, the collected charge amount corresponding to the incident position is measured, and the lifetime is found at the intersection of the incident position line and the collected charge amount line in FIG. Lifetime can be measured.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the first to fourth embodiments of the present invention will be described in detail with reference to FIGS.
3 is a sectional view of the first embodiment of the present invention, FIG. 4 is a plan view of the first embodiment of the present invention, FIG. 5 is a sectional view of the second embodiment of the present invention, and FIG. 6 is the present invention. FIG. 7 is a sectional view of a third embodiment according to the present invention, FIG. 8 is a plan view of the third embodiment according to the present invention, and FIG. 9 is a fourth embodiment according to the present invention. It is sectional drawing of an example.
[0014]
In the first embodiment according to the present invention, to form a p ⁺ layer 4 and n ⁺ layer 5 at intervals of 50μm to p-type silicon layer 13 as shown in FIG. 3, p ⁺ layer 4 as shown in FIG. 4 And p ⁺ layer pad electrode 4a are connected by metal wiring 6a made of aluminum or the like, and n ⁺ layer 5 and n ⁺ layer pad electrode 5a are connected by metal wiring 6b made of aluminum or the like.
[0015]
Then, a charge measuring device 8 capable of measuring charges with an accuracy of 0.1 fC is connected to the n ⁺ layer 5 through an n ⁺ layer pad electrode as shown in FIG.
Thereafter, as shown in FIG. 3, ions 7 accelerated to about several MeV are irradiated between the n ⁺ layer 5 and the p ⁺ layer 4, and the collected charge amount is measured by the charge measuring device 8.
[0016]
The ion irradiation position needs to be controlled with a precision of several μm using a parallel plate capacitor.
Then, by using FIG. 2, the lifetime of minority carriers in the SOI layer 3 can be measured by finding the lifetime at the intersection of the ion incident position line and the collected charge amount line.
[0017]
In the second embodiment according to the present invention, to form a p ⁺ layer 4 and n ⁺ layer 5 at intervals of 50μm to p-type silicon layer 13 as shown in FIG. 5, p ⁺ layer 4 as shown in FIG. 6 And p ⁺ layer pad electrode 4a are connected by metal wiring 6a made of aluminum or the like, and n ⁺ layer 5 and n ⁺ layer pad electrode 5a are connected by metal wiring 6b made of aluminum or the like.
[0018]
Then, a charge measuring device 8 capable of measuring charges with an accuracy of 0.1 fC is connected to the n ⁺ layer 5 through an n ⁺ layer pad electrode as shown in FIG.
In the second embodiment, after forming the metal wirings 6a and 6b, a polyimide film 9 having a film thickness of 30 μm capable of shielding α rays is deposited as shown in FIG. As shown in FIG. 6, a 2 μm square polyimide hole 9a is formed.
[0019]
When the α-ray source 7a that emits the α-ray 7b is placed on the silicon substrate, the energy of the α-ray 7b emitted from the α-ray source 7a is about 5 MeV. Attenuates and does not reach the p-type silicon layer 13. For this reason, α rays 7b are incident only on the polyimide hole 9a.
[0020]
From the relationship between the position of the polyimide hole 9a and the collected charge amount, it is possible to measure the minority carrier lifetime as in the first embodiment.
In the second embodiment, since the polyimide hole 9a for determining the incident position of the α-ray 7b is formed using the lithography technique, it is possible to control the incident position of the α-ray 7b inexpensively and easily. .
[0021]
In the third embodiment according to the present invention, before the p ⁺ layer 4 and the n ⁺ layer 5 are formed on the p type silicon layer 13 at an interval of 50 μm as shown in FIG. forming a gate electrode 10 through the gate oxide film 10b, and a p ⁺ layer 4 and the p ⁺ layer pad electrode 4a as shown in FIG. 8 are connected by metal wiring 6a made of aluminum, n ⁺ layer 5 and the n ^{The +} layer pad electrode 5a is connected by a metal wiring 6b made of aluminum or the like.
[0022]
Then, a charge measuring device 8 capable of measuring charges with an accuracy of 0.1 fC is connected to the n ⁺ layer 5 through an n ⁺ layer pad electrode as shown in FIG.
In the third embodiment, when a charge amount is collected by the charge measuring device 8, a positive voltage is applied to the gate electrode 10. Therefore, electrons generated in the p-type silicon layer 13 Since it flows through the interface immediately below, the lifetimes of the upper interface and the lower interface of the p-type silicon layer 13 could not be measured separately in the first and second embodiments. In the third embodiment, the lifetime of the upper interface of the p-type silicon layer 13 can be measured.
[0023]
In the fourth embodiment according to the present invention, as shown in FIG. 9, after forming the gate electrode 10 during the step of forming the oxide film 12, the p-type silicon layer 13 is formed via the gate oxide film 10b, and 50 .mu.m. the n of the p ⁺ layer 4 and n ⁺ layer 5 were formed at intervals, 0.1 fC of the charge measuring instrument 8 capable of measuring charges in precision as shown in FIG. 1 via the n ⁺ layer pad electrode ⁺ Connect to layer 5.
[0024]
Thereafter, as shown in FIG. 9, ions 7 accelerated to about several MeV are irradiated between the n ⁺ layer 5 and the p ⁺ layer 4, and the collected charge amount is measured by the charge measuring device 8.
[0025]
The ion irradiation position needs to be controlled with a precision of several μm using a parallel plate capacitor.
In the fourth embodiment, as in the third embodiment, when a charge amount is collected by the charge measuring device 8, a positive voltage is applied to the gate electrode 10, so that it is generated in the p-type silicon layer 13. In this case, the electrons that have flown flow through the interface immediately above the gate electrode 10, so that the life of the upper interface and the lower interface of the p-type silicon layer 13 is reduced in the first and second embodiments. Although the time could not be measured separately, in the fourth embodiment, the lifetime of the lower interface of the p-type silicon layer 13 can be measured.
[0026]
In this embodiment, a charge measuring device is provided between the n ⁺ layer pad electrode and the ground, the p ⁺ layer pad electrode is connected to the ground, and ions are implanted into the SOI layer between the p ⁺ layer and the n ⁺ layer. The charge amount collected by the n ⁺ layer pad electrode is measured by this charge measuring instrument and the lifetime of minority carriers in this SOI layer is calculated based on the relationship between the ion implantation position and the collected charge amount. However, contrary to the present embodiment, a charge measuring device is provided between the p ⁺ layer pad electrode and the ground, the n ⁺ layer pad electrode is connected to the ground, and the n ⁺ layer and the p ⁺ layer are connected to each other. When the ions are implanted into the SOI layer, the charge amount collected by the p ⁺ layer pad electrode is measured by the charge measuring device. Based on the relationship between the ion implantation position and the collected charge amount, the holes of the SOI layer are measured. It is possible to calculate the lifetime of minority carriers.
[0027]
【The invention's effect】
As is apparent from the above description, according to the present invention, the lifetime of minority carriers formed on the SOI layer on the surface of the support substrate can be measured in the middle of the semiconductor device manufacturing process by a very simple method. Thus, there is an advantage that a semiconductor substrate having a short minority carrier lifetime can be removed in the middle of the process, and a method for measuring the lifetime of minority carriers and a semiconductor device that can be expected to significantly improve the reliability and reliability. A manufacturing method can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a diagram showing the relationship between the distance between an n ⁺ layer and an ion incident position and the amount of collected charges collected by a charge measuring instrument. Sectional view of an example [FIG. 4] Plan view of a first embodiment according to the present invention [FIG. 5] Sectional view of a second embodiment according to the present invention [FIG. 6] Plan view of a second embodiment according to the present invention [FIG. 7 is a sectional view of a third embodiment according to the present invention. FIG. 8 is a plan view of a third embodiment according to the present invention. FIG. 9 is a sectional view of a fourth embodiment according to the present invention.
1 Support substrate 2 Insulating film 3 SOI layer 4 p ⁺ layer
4a p ⁺ layer pad electrode 5 n ⁺ layer
5a n ⁺ layer pad electrode
6a Metal wiring
6b Metal wiring 7 ion
7a alpha source
7b α ray 8 Charge measuring instrument 9 Polyimide film
9a Polyimide hole
10 Gate electrode
10a Pad electrode of gate electrode
10b Gate oxide film
11 Silicon substrate
12 Oxide film
13 p-type silicon layer

Claims (5)

A semiconductor device comprising a metal wiring layer in which ap ⁺ layer and an n ⁺ layer are formed in a p-type SOI layer, and the p ⁺ layer and the n ⁺ layer are connected to the p + layer pad electrode and the n ⁺ layer pad electrode, respectively. In the method of measuring the lifetime of minority carriers in
When a charge measuring device is provided between the n ⁺ layer pad electrode and the ground, the p ⁺ layer pad electrode is connected to the ground, and ions are implanted into the SOI layer between the p ⁺ layer and the n ⁺ layer The charge amount collected by the n ⁺ layer pad electrode is measured by the charge measuring device, and the lifetime of minority carriers in the SOI layer is calculated based on the relationship between the ion implantation position and the collected charge amount. Minority carrier lifetime measurement method.   Forming a coating that blocks α-rays on the surface of the metal wiring layer, providing an opening in the coating, providing the α-ray radiation source on the semiconductor device, and the relationship between the position of the opening and the amount of collected charge The minority carrier lifetime measurement method according to claim 1, wherein the minority carrier lifetime of the SOI layer is calculated based on the lifetime. After forming a gate electrode on the SOI layer, a p ⁺ layer and an n ⁺ layer are formed on the SOI layer, and a positive voltage is applied to the gate electrode between the p ⁺ layer and the n ⁺ layer. When the ions are implanted into the SOI layer, the charge amount collected by the n ⁺ layer pad electrode is measured by the charge meter, and the upper side of the SOI layer is measured based on the relationship between the ion implantation position and the collected charge amount. The minority carrier lifetime measurement method according to claim 1, wherein the lifetime of the minority carrier at the interface is calculated. After forming a gate electrode in contact with the lower surface of the SOI layer via a gate insulating film in the oxide film between the SOI layer and the support substrate, a p ⁺ layer and an n ⁺ layer are formed on the SOI layer, and the gate electrode is formed on the gate electrode. Measuring the amount of charge collected on the n ⁺ layer pad electrode by the charge meter when ions are implanted into the SOI layer between the p ⁺ layer and the n ⁺ layer in a state where a positive voltage is applied; 2. The minority carrier lifetime measurement method according to claim 1, wherein the minority carrier lifetime of the lower interface of the SOI layer is calculated based on the relationship between the ion implantation position and the collected charge amount.   The manufacturing process of a semiconductor device includes the step of measuring the lifetime of minority carriers by the method according to claim 1, 2, 3, or 4, and the step of removing a semiconductor substrate whose lifetime is shorter than a set value. A method of manufacturing a semiconductor device.

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