JP3661822B2 - Chip support substrate for semiconductor packaging - Google Patents
Chip support substrate for semiconductor packaging Download PDFInfo
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- JP3661822B2 JP3661822B2 JP01898297A JP1898297A JP3661822B2 JP 3661822 B2 JP3661822 B2 JP 3661822B2 JP 01898297 A JP01898297 A JP 01898297A JP 1898297 A JP1898297 A JP 1898297A JP 3661822 B2 JP3661822 B2 JP 3661822B2
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- Prior art keywords
- semiconductor chip
- support substrate
- wiring
- adhesive
- semiconductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
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- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は、半導体パッケ−ジ用チップ支持基板に関する。
【０００２】
【従来の技術】
半導体の集積度が向上するに従い、入出力端子数が増加している。従って、多くの入出力端子数を有する半導体パッケージが必要になった。一般に、入出力端子はパッケージの周辺に一列配置するタイプと、周辺だけでなく内部まで多列に配置するタイプがある。前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）が代表的である。これを多端子化する場合は、端子ピッチを縮小することが必要であるが、０．５ｍｍピッチ以下の領域では、配線板との接続に高度な技術が必要になる。後者のアレイタイプは比較的大きなピッチで端子配列が可能なため、多ピン化に適している。従来、アレイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は挿入型となり、表面実装には適していない。このため、表面実装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と称するパッケージが開発されている。
【０００３】
一方、電子機器の小型化に伴って、パッケージサイズの更なる小型化の要求が強くなってきた。この小型化に対応するものとして、半導体チップとほぼ同等サイズの、いわゆるチップサイズパッケージ（ＣＳＰ； Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案されている。これは、半導体チップの周辺部でなく、実装領域内に外部配線基板との接続部を有するパッケージである。具体例としては、バンプ付きポリイミドフィルムを半導体チップの表面に接着し、チップと金リード線により電気的接続を図った後、エポキシ樹脂などをポッティングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩＡＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．１４０，ｐ１８−１９）や、仮基板上に半導体チップ及び外部配線基板との接続部に相当する位置に金属バンプを形成し、半導体チップをフェースダウンボンディング後、仮基板上でトランスファーモールドしたもの（Ｓｍａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃｋａｇｅ ＣＳＰ； ＴｈｅＳｅｃｏｎｄ ＶＬＳＩ Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐａｎ，ｐ４６−５０，１９９４）などがある。
【０００４】
【発明が解決しようとする課題】
しかしながら、従来提案されている半導体パッケージの多くは、小型で高集積度化に対応できかつパッケージクラックを防止し信頼性に優れしかも生産性に優れるものではない。
本発明は、パッケージクラックを防止し信頼性に優れる小型の半導体パッケ−ジの製造を可能とする半導体パッケ−ジ用チップ支持基板を提供するものである。
【０００５】
【課題を解決するための手段】
本発明の半導体パッケ−ジ用チップ支持基板は
Ａ．絶縁性支持基板の一表面には複数組の配線が形成されており、前記配線は少なくとも半導体チップ電極と接続するインナ−接続部及び半導体チップ搭載領域部を有すものであり、
Ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前記配線が形成されている箇所であって前記インナ−接続部と導通するアウタ−接続部が設けらる箇所に、開口が設けられており、
Ｃ．前記絶縁性支持基板の前記半導体チップ搭載領域内であって前記配線のない箇所に、少なくとも１個の貫通穴が設けられており、
Ｄ．前記配線の半導体チップ搭載領域部を含めて前記半導体チップが搭載される箇所に、絶縁性のフィルム状接着材が形成されており、
Ｅ．半導体チップ搭載後、前記配線のない前記半導体チップ搭載領域内において、前記半導体チップと前記フィルム状接着材間に空隙が形成されるよう構成されたことを特徴とするものである。
【０００６】
【発明の実施の形態】
絶縁性支持基板としては、ポリイミド、エポキシ樹脂、ポリイミド等のプラスチックフィルム、ポリイミド、エポキシ樹脂、ポリイミド等のプラスチックをガラス不織布等基材に含浸・硬化したもの等が使用できる。
絶縁性支持基板の一表面に複数組の配線を形成すには、銅箔をエッチングする方法、所定の箇所に銅めっきをする方法、それらを併用する方法等が使用できる。
絶縁性支持基板に外部接続部、貫通穴などの開口を設けるには、ドリル加工やパンチングなどの機械加工、エキシマレーザや炭酸ガスレーザなどのレーザ加工等により行うことができる。また、接着性のある絶縁基材等に開口部をあらかじめ設け、それを銅箔等の配線形成用金属箔と張り合わせる方法、銅箔付きまたはあらかじめ配線が形成された絶縁基材に開口部を設ける方法、それらを併用する等が可能である。インナ−接続部と導通するアウタ−接続部は、絶縁性支持基板開口部にハンダボール、めっき等によりバンプ等を形成することにより作成することができる。これは、外部の基板等に接続される。
フィルム状接着材搭載領域は、できるだけ均一に配線パターンが配置されていることが好ましい。
【０００７】
絶縁性のフィルム状接着材は、半導体チップ搭載のためのダイボンド材であり、半導体チップおよび配線との接着力が強く、かつリフロー時（半導体パッケージを外部基板等にＩＲリフロー（温度２３０℃）を用いて実装する時等）に発生する内部圧力で、変形または破れやすいことが望ましい。
具体的には、化１
【化１】
で表されるテトラカルボン酸二無水物（１）の含量が全テトラカルボン酸二無水物の７０モル％以上であるテトラカルボン酸二無水物と、ジアミンを反応させて得られるポリイミド樹脂、更にエポキシ樹脂等の熱硬化性樹脂からなるフィルム状接着材がある。更にこれにシリカ、アルミナ、等の無機物質フィラーを含有させることもできる。
貫通穴は、フィルム状接着材搭載領域内に少なくとも１個以上形成される。穴径は特に問わないが、例えば、０．０５ｍｍ以上かつ１．０００ｍｍ以下が好ましい。配置も特に問わないが、なるべく均等に複数個配置されていることが好ましく、これらの穴径および配置は、配線パターンに応じて選択される。
【０００８】
本発明の半導体パッケ−ジ用チップ支持基板を使用して半導体パッケ−ジを製造するには、本発明の半導体パッケ−ジ用チップ支持基板のフィルム状接着材の面に半導体チップを接着し、半導体チップ電極を支持基板のインナ−接続部とワイヤーボンディング等により接続する。さらに半導体チップの少なくとも半導体チップ電極面を樹脂封止し、アウター接続部にはんだボールを搭載することにより半導体パッケ−ジを製造することが出来る。
【０００９】
【実施例】
図１により、本発明の一実施例について説明する。
ポリイミド接着剤をポリイミドフィルムの両面に塗布した、厚さ０．０７ｍｍのポリイミドボンディングシート１に、開口３及び貫通穴９をドリル加工で形成する。次に厚さ０．０１８ｍｍの銅箔（日本電解製、商品名：ＳＬＰー１８）を接着後、インナー接続部及び展開配線２を通常のエッチング法で形成する。さらに、露出している配線に無電解ニッケルめっき（膜厚：５μｍ）、無電解金めっき（膜厚：０．８μｍ）を順次施す（不図示）。ここでは、無電解めっきを使用したが、電解めっきを用いてもよい。次に打ち抜き金型を用いてフレーム状に打ち抜き、複数組のインナー接続部、展開配線、アウター接続部となる開口を形成した支持基板を準備する（図１ａ）。支持基板の作製方法として市販の２層（銅／ポリイミド）フレキシブル基板のポリイミドを、レーザ加工によりアウター接続部穴等を形成する方法でもよい。
次に支持基板の半導体チップ搭載領域に、ダイボンドフィルム４（日立化成工業株式会社製、商品名：ＤＦ−３３５、厚み０．０１５ｍｍ）を仮接着する（図１ｂ）。仮接着の条件は、例えば温度１６０℃、時間５秒、圧力３ｋｇｆ／ｃｍ2である。次に、仮接着したダイボンドフィルムを用いて、半導体チップ６を支持基板の所定の位置に接着する。接着条件は、例えば温度２２０℃、時間５秒、圧力３００ｇｆ／ｃｍ2である。このとき配線のない部分で、半導体チップ６とダイボンドフィルム４間に空隙が形成される。さらに、半導体チップ電極とインナー接続部を、金ワイヤ５をボンディングして電気的に接続する（図１ｃ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂７（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて各々封止する（図１ｄ）。その後、アウター接続部にはんだボール８を配置し溶融させ（図１ｅ）、パンチにより個々のパッケージに分離し半導体パッケージが得られる（図１ｆ）。最後に半導体パッケージを、外部基板１０にＩＲリフロー
（温度２３０℃）を用いて実装する（図１ｇ）。このときダイボンドフィルムは、貫通穴側に変形または破れ、空隙部に発生する内部圧力を緩和する。
【０００７】
【発明の効果】
ａ．絶縁性支持基板の一表面に複数組の配線（少なくとも半導体チップ電極と接続するインナ−接続部及び半導体チップ搭載領域部を有す）を形成し、
ｂ．絶縁性支持基板の、絶縁性支持基板の配線が形成されている箇所であってインナ−接続部と導通するアウタ−接続部が設けらる箇所に開口を設け、
ｃ．配線の半導体チップ搭載領域部を含めて半導体チップが搭載される箇所に接着材を形成し、
ｄ．半導体チップを、支持基板のインナ−接続部が設けられている面に接着材を用いて接着し、
ｅ．半導体チップ電極を基板のインナ−接続部とワイヤーボンディングにより接続し、
ｆ．半導体チップの少なくとも半導体チップ電極面を樹脂封止して
製造する半導体パッケージでは、支持基板の半導体チップ搭載領域に露出した配線があるので、通常のペースト状接着材（銀ペースト、無銀ペースト）を使用すると、半導体チップと配線がショートしてしまう恐れがある。このため半導体チップ搭載領域にレジスト等の絶縁材料を塗布した構造や、絶縁フィルムを貼った構造となるが、この構造では多くの材料界面ができ、また接着材のペーストが半導体チップ接着時にボイドを混入しやすく、ＩＲリフロー等で外部基板に実装する際に、剥離やパッケージクラックが発生しやすく、信頼性を落とす原因になる。また絶縁性のフィルム状接着材を使用した場合でも、半導体チップとフィルム状接着材間のボイドを完全になくすことは非常に困難であり、同様に信頼性を落とす原因になる。
本発明では、半導体チップとフィルム状接着材間に大きな空隙部を形成し、リフロー時に発生する内部圧力を、フィルム状接着材が貫通穴側に変形または破れることで緩和できる。したがって、パッケージクラックを防止し信頼性の高い小型半導体パッケ−ジの製造が可能となる。
【図面の簡単な説明】
【図１】本発明の一実施例を説明するための、半導体パッケージ製造工程を示す断面図である。
【符号の説明】
１ ポリイミドボンディングシート
２ インナー接続部及び展開配線
３ 開口
４ ダイボンドフィルム
５ 金ワイヤ
６ 半導体チップ
７ 半導体封止用エポキシ樹脂
８ はんだボール
９ 貫通穴
１０ 外部基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip support substrate for a semiconductor package.
[0002]
[Prior art]
As the degree of integration of semiconductors has improved, the number of input / output terminals has increased. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, there are a type in which input / output terminals are arranged in a row around the package and a type in which the input / output terminals are arranged in multiple rows not only in the periphery but also in the interior. The former is typically QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in a region having a pitch of 0.5 mm or less, advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged with a relatively large pitch. Conventionally, an array type is generally a PGA (Pin Grid Array) having connection pins, but connection with a wiring board is an insertion type and is not suitable for surface mounting. Therefore, a package called BGA (Ball Grid Array) that can be mounted on the surface has been developed.
[0003]
On the other hand, with the downsizing of electronic devices, the demand for further downsizing of the package size has increased. In order to cope with this miniaturization, a so-called chip size package (CSP) having a size substantially equal to that of a semiconductor chip has been proposed. This is a package having a connection portion with an external wiring board in the mounting region, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is bonded to the surface of a semiconductor chip, and after electrical connection is made between the chip and a gold lead wire, epoxy resin or the like is potted and sealed (NIKKEI MATERIALS & TECHNOLOGY 94. 4, No. 140, p18-19) or metal bumps are formed on the temporary substrate at positions corresponding to the connection portions between the semiconductor chip and the external wiring substrate, and the semiconductor chip is transferred on the temporary substrate after face-down bonding. Molded (Smallest Flip-Chip-Like Package CSP; TheSecond VLSI Packaging Workshop of Japan, p46-50, 1994).
[0004]
[Problems to be solved by the invention]
However, many of the conventionally proposed semiconductor packages are small in size, can cope with high integration, prevent package cracks, have excellent reliability, and are not excellent in productivity.
The present invention provides a chip support substrate for a semiconductor package that enables the manufacture of a small semiconductor package that prevents package cracks and has excellent reliability.
[0005]
[Means for Solving the Problems]
The chip support substrate for a semiconductor package of the present invention is an A.D. A plurality of sets of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part and a semiconductor chip mounting area part connected to the semiconductor chip electrode,
B. The insulating support substrate is provided with an opening at a location where the wiring of the insulating support substrate is formed and where an outer connection portion is provided which is electrically connected to the inner connection portion. ,
C. At least one through hole is provided in the semiconductor chip mounting region of the insulating support substrate at a location without the wiring,
D. An insulating film-like adhesive is formed at a location where the semiconductor chip is mounted including the semiconductor chip mounting region of the wiring,
E. After the semiconductor chip is mounted, a gap is formed between the semiconductor chip and the film adhesive in the semiconductor chip mounting region without the wiring.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
As the insulating support substrate, it is possible to use a plastic film such as polyimide, epoxy resin or polyimide, or a material such as polyimide, epoxy resin or polyimide impregnated and cured on a substrate such as a glass nonwoven fabric.
In order to form a plurality of sets of wirings on one surface of the insulating support substrate, a method of etching a copper foil, a method of copper plating at a predetermined location, a method of using them together, and the like can be used.
Openings such as external connection portions and through holes can be provided on the insulating support substrate by machining such as drilling or punching or laser processing such as excimer laser or carbon dioxide laser. In addition, an opening is provided in an insulating base material having adhesive in advance, and the opening portion is attached to a metal foil for wiring formation such as copper foil. It is possible to use a combination of these methods. The outer connection portion that is electrically connected to the inner connection portion can be formed by forming bumps or the like in the insulating support substrate opening by solder balls, plating, or the like. This is connected to an external substrate or the like.
In the film adhesive mounting region, it is preferable that the wiring pattern is arranged as uniformly as possible.
[0007]
The insulating film adhesive is a die-bonding material for mounting a semiconductor chip, has a strong adhesive force between the semiconductor chip and the wiring, and reflows (IR reflow (temperature 230 ° C.) to the external substrate etc.) It is desirable that the internal pressure generated during mounting and the like be easily deformed or broken.
Specifically, Chemical 1
[Chemical 1]
A tetracarboxylic dianhydride having a tetracarboxylic dianhydride (1) content of not less than 70 mol% of the total tetracarboxylic dianhydride and a polyimide resin obtained by reacting with a diamine, and further an epoxy There is a film adhesive made of a thermosetting resin such as a resin. Furthermore, an inorganic substance filler such as silica, alumina or the like can be contained therein.
At least one through hole is formed in the film adhesive mounting region. The hole diameter is not particularly limited, but is preferably 0.05 mm or more and 1.000 mm or less, for example. The arrangement is not particularly limited, but a plurality of them are preferably arranged as uniformly as possible, and the hole diameter and arrangement are selected according to the wiring pattern.
[0008]
To manufacture a semiconductor package using the semiconductor package chip support substrate of the present invention, the semiconductor chip is bonded to the surface of the film-like adhesive of the semiconductor package chip support substrate of the present invention, The semiconductor chip electrode is connected to the inner connection portion of the support substrate by wire bonding or the like. Furthermore, a semiconductor package can be manufactured by resin-sealing at least the semiconductor chip electrode surface of the semiconductor chip and mounting solder balls on the outer connection portion.
[0009]
【Example】
An embodiment of the present invention will be described with reference to FIG.
An opening 3 and a through hole 9 are formed by drilling in a polyimide bonding sheet 1 having a thickness of 0.07 mm, in which a polyimide adhesive is applied to both sides of a polyimide film. Next, after bonding a copper foil having a thickness of 0.018 mm (trade name: SLP-18, manufactured by Nippon Electrolytic Co., Ltd.), the inner connection portion and the developed wiring 2 are formed by a normal etching method. Further, electroless nickel plating (film thickness: 5 μm) and electroless gold plating (film thickness: 0.8 μm) are sequentially applied to the exposed wiring (not shown). Although electroless plating is used here, electrolytic plating may be used. Next, a punching die is used to punch out into a frame shape to prepare a support substrate on which a plurality of sets of inner connection portions, developed wirings, and openings serving as outer connection portions are formed (FIG. 1a). As a method for producing the support substrate, a commercially available two-layer (copper / polyimide) flexible substrate polyimide may be formed by forming the outer connection hole or the like by laser processing.
Next, a die bond film 4 (manufactured by Hitachi Chemical Co., Ltd., trade name: DF-335, thickness 0.015 mm) is temporarily bonded to the semiconductor chip mounting region of the support substrate (FIG. 1b). The temporary bonding conditions are, for example, a temperature of 160 ° C., a time of 5 seconds, and a pressure of 3 kgf / cm 2 . Next, the semiconductor chip 6 is bonded to a predetermined position of the support substrate using the temporarily bonded die bond film. The bonding conditions are, for example, a temperature of 220 ° C., a time of 5 seconds, and a pressure of 300 gf / cm 2 . At this time, a gap is formed between the semiconductor chip 6 and the die bond film 4 at a portion where there is no wiring. Further, the semiconductor chip electrode and the inner connection portion are electrically connected by bonding the gold wire 5 (FIG. 1c). What was formed in this way was loaded into a transfer mold die, and each was sealed using epoxy resin 7 for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 1d). . Thereafter, the solder balls 8 are disposed and melted in the outer connection portion (FIG. 1e), and separated into individual packages by punching to obtain a semiconductor package (FIG. 1f). Finally, the semiconductor package is mounted on the
[0007]
【The invention's effect】
a. Forming a plurality of sets of wirings (having at least an inner connection part and a semiconductor chip mounting area part connected to the semiconductor chip electrode) on one surface of the insulating support substrate;
b. An opening is provided at a location where the wiring of the insulating support substrate is formed on the insulating support substrate, and where the outer connection portion that is electrically connected to the inner connection portion is provided,
c. An adhesive is formed on the part where the semiconductor chip is mounted including the semiconductor chip mounting area of the wiring,
d. The semiconductor chip is bonded to the surface of the support substrate where the inner connection portion is provided using an adhesive,
e. The semiconductor chip electrode is connected to the inner connection part of the substrate by wire bonding,
f. In semiconductor packages manufactured by resin-sealing at least the semiconductor chip electrode surface of a semiconductor chip, since there are exposed wires in the semiconductor chip mounting area of the support substrate, ordinary paste-like adhesive (silver paste, silver-free paste) is used. If used, the semiconductor chip and the wiring may be short-circuited. For this reason, a structure in which an insulating material such as a resist is applied to the semiconductor chip mounting area or a structure in which an insulating film is applied is formed. In this structure, many material interfaces are formed, and the paste of the adhesive material causes voids when the semiconductor chip is bonded. It is easy to mix, and when mounted on an external substrate by IR reflow or the like, peeling or package cracking is likely to occur, causing a drop in reliability. Even when an insulating film-like adhesive is used, it is very difficult to completely eliminate voids between the semiconductor chip and the film-like adhesive, which similarly causes a decrease in reliability.
In the present invention, a large gap is formed between the semiconductor chip and the film-like adhesive, and the internal pressure generated during reflow can be alleviated by the film-like adhesive being deformed or broken to the through hole side. Therefore, it is possible to manufacture a small-sized semiconductor package that prevents package cracks and has high reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor package manufacturing process for explaining an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Polyimide bonding sheet 2 Inner connection part and expansion | deployment wiring 3 Opening 4 Die bond film 5 Gold wire 6 Semiconductor chip 7 Epoxy resin 8 for semiconductor sealing Solder ball 9 Through
Claims (2)
Ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前記配線が形成されている箇所であって前記インナ−接続部と導通するアウタ−接続部が設けらる箇所に、開口が設けられており、
Ｃ．前記絶縁性支持基板の前記半導体チップ搭載領域内であって前記配線のない箇所に、少なくとも１個の貫通穴が設けられており、
Ｄ．前記配線の半導体チップ搭載領域部を含めて前記半導体チップが搭載される箇所に、絶縁性のフィルム状接着材が形成されており、
Ｅ．半導体チップ搭載後、前記配線のない前記半導体チップ搭載領域内において、前記半導体チップと前記フィルム状接着材間に空隙が形成されるよう構成されたことを特徴とする半導体パッケ−ジ用チップ支持基板。A. A plurality of sets of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part and a semiconductor chip mounting area part connected to the semiconductor chip electrode,
B. The insulating support substrate is provided with an opening at a location where the wiring of the insulating support substrate is formed and where an outer connection portion is provided which is electrically connected to the inner connection portion. ,
C. At least one through hole is provided in the semiconductor chip mounting region of the insulating support substrate at a location without the wiring,
D. Insulating film-like adhesive is formed at the place where the semiconductor chip is mounted including the semiconductor chip mounting region portion of the wiring,
E. A chip support substrate for a semiconductor package, wherein a gap is formed between the semiconductor chip and the film adhesive in the semiconductor chip mounting area without the wiring after mounting the semiconductor chip. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01898297A JP3661822B2 (en) | 1997-01-31 | 1997-01-31 | Chip support substrate for semiconductor packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01898297A JP3661822B2 (en) | 1997-01-31 | 1997-01-31 | Chip support substrate for semiconductor packaging |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10214918A JPH10214918A (en) | 1998-08-11 |
| JP3661822B2 true JP3661822B2 (en) | 2005-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01898297A Expired - Fee Related JP3661822B2 (en) | 1997-01-31 | 1997-01-31 | Chip support substrate for semiconductor packaging |
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| JP (1) | JP3661822B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422346B1 (en) | 2001-06-12 | 2004-03-12 | 주식회사 하이닉스반도체 | chip scale package and method of fabricating the same |
| JP2010171216A (en) * | 2009-01-23 | 2010-08-05 | Kyushu Institute Of Technology | Mems device package device and method of manufacturing the same |
| JP6884595B2 (en) * | 2017-02-28 | 2021-06-09 | キヤノン株式会社 | Manufacturing methods for electronic components, electronic devices and electronic components |
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| JPH10214918A (en) | 1998-08-11 |
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