JP3662626B2 - Multi-value storage element, memory array, storage and reproduction method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a multi-value storage element, a memory array, a storage and reproduction method, and more particularly to an element including a plurality of binary storage elements.
[0002]
[Prior art]
As a nonvolatile memory, a floating gate type EPROM is used. FIG. 14 shows the structure of the memory cell 2 constituting the conventional EPROM.
[0003]
A source 6 and a drain 8 are formed on the semiconductor substrate 4. A silicon oxide film 12, a floating gate 14, a silicon oxide film 16, and a control gate 18 are stacked in this order on the channel formation region 10 formed between the source 6 and the drain 8. These constitute the memory cell 2.
[0004]
In order to write “1” information in the memory cell 2, as shown in FIG. 14, the source 6 is grounded and a high voltage (20 V) is applied to the drain 8 and the gate 18. As a result, some of the accelerated electrons are taken into the floating gate 14. This is the state “1”. On the other hand, a state where electrons are not taken into the floating gate 14 is a state of “0”. These states are maintained even when the power is turned off, and are maintained semipermanently unless erased or written.
[0005]
In order to read the information in the memory cell 2, as shown in the circuit diagram of FIG. 15A, the source 6 is grounded, and a low voltage (5 V) is applied to the drain 8 and the gate 18, and the drain current at this time is measured. By doing.
[0006]
That is, when the memory cell 2 is in the “1” state, no channel is formed in the channel formation region 10 due to the influence of electrons taken in the floating gate 14. For this reason, no drain current flows. On the other hand, when the memory cell 2 is in the “0” state, electrons are not taken into the floating gate 14, so that a channel is formed in the channel formation region 10. For this reason, a drain current flows.
[0007]
In this manner, information can be written to and read from the memory cell 2.
[0008]
[Problems to be solved by the invention]
However, the conventional EPROM as described above has the following problems. The memory cell 2 constituting the conventional EPROM can store only “0” or “1”, that is, binary values. Therefore, for example, two memory cells 2 are required to store any integer from “0” to “3” (four numerical values).
[0009]
Generally 2 ⁿ In order to store a numerical value, n memory cells 2 are required. On the other hand, both writing and reading can access only one memory cell 2 in one operation. Therefore, 2 ⁿ When writing or reading a numerical value, n times of operations are required, and therefore, it takes n times as long as a binary numerical value.
[0010]
In order to solve this problem, the following method has been proposed. In the write operation shown in FIG. 14, the number of electrons taken into the floating gate 14 depends on the time for applying a high voltage. Therefore, when storing the numerical value of the m value, the time for applying the high voltage is set to m steps (T0 to Tm-1) corresponding to the numerical values "0" to "m-1". For example, when “3” is written in a certain memory cell 2, a high voltage is applied to the memory cell 2 for a time T3.
[0011]
The m-value information thus written is read from the memory cell 2 by connecting as shown in the circuit diagram of FIG. 15A and measuring the drain current. That is, in this case, the drain current depends on the number of electrons taken into the floating gate 14. Therefore, by measuring the drain current, the number of electrons taken into the floating gate 14, that is, the application time of the high voltage, that is, the numerical value of the m value written in the memory cell 2 can be read.
[0012]
When this method is used, a multi-valued numerical value can be stored in one memory cell 2, so that the time required for writing and reading can be reduced.
[0013]
However, the difference in drain current based on the difference in the number of electrons taken into the floating gate 14 is extremely small, so that there is a drawback that erroneous reading is likely to occur. Therefore, when reading, a highly accurate and complex current measurement circuit is required to identify the difference in drain current with high accuracy.
[0014]
The present invention improves the problems of storage elements such as the memory cell 2 constituting such a conventional EPROM, and enables simple and reliable multi-value storage elements, memory arrays, storages capable of high-speed writing and reading. And to provide a reproduction method.
[0015]
[Means for Solving the Problems]
This invention The multi-value storage element is a multi-value storage element including a plurality of binary storage elements, and is in a binary state corresponding to the magnitude or application time of a voltage applied to the multi-value storage element at the time of writing. It is configured to determine the number of binary storage elements that cause a change in the number and to output in accordance with the number of binary storage elements that have caused a change in the binary state at the time of reading. .
[0016]
This invention The multi-value storage element is a transistor in which the binary storage element determines a binary state corresponding to the number of electrons captured in the electron capture region, and the electron capture rate of the transistors differs between the transistors. It was configured as described above.
[0017]
This invention In the multi-value storage element, the transistor is a floating gate type transistor, and the multi-value storage element is formed by a plurality of the transistors connected in parallel, and between the channel formation region of the transistor and the floating gate. The capacitance ratio between the first capacitor formed in the second capacitor and the second capacitor formed between the floating gate and the control gate is different between the transistors.
[0018]
This invention The multi-value storage element is configured such that the capacitance ratio of the first capacitor and the second capacitor is different among the plurality of transistors by changing the area of the second capacitor.
[0019]
This invention The multi-value storage element further includes a read-only gate, and a capacitance ratio between the third capacitor formed between the read-only gate and the floating gate and the first capacitor is substantially the same between the transistors. It is characterized by being comprised.
[0020]
This invention In the multi-value storage element, the transistor is an MNOS type transistor, and the multi-value storage element is formed by a plurality of the transistors connected in parallel, and is formed immediately above the channel formation region of the transistor. A feature is that the thickness of one insulating film or the total thickness of insulating films formed between a channel formation region and a gate electrode is different between the transistors.
[0021]
This invention The memory array includes a plurality of multi-value storage elements.
[0022]
This invention In the storage and reproduction method, a plurality of binary storage elements are prepared, and at the time of writing, the number of binary storage elements that cause a state change is determined and read in accordance with the magnitude of the applied voltage or the application time. Sometimes, an output corresponding to the number of binary storage elements that have caused a state change is obtained.
[0023]
[Action]
This invention Multi-value storage elements and a plurality of binary storage elements are prepared, and the number of binary storage elements that cause a state change corresponding to the magnitude or application time of a voltage applied to the multi-value storage elements at the time of writing is prepared. It is characterized in that an output corresponding to the number of binary storage elements having undergone a state change is obtained upon determination and reading.
[0024]
Therefore, by making the number of binary storage elements that cause a state change at the time of writing correspond to the multi-value number, it is possible to make the applied voltage or application time correspond to the multi-value number. For this reason, by applying an applied voltage or application time corresponding to the multi-value number to the multi-value storage element, the multi-value number can be stored in one write operation.
[0025]
The output and the multi-value number correspond to each other. For this reason, a multi-value number can be read by one output reading operation. Further, at the time of reading, the output takes a stepwise value determined by the number of binary storage elements that have caused a change in state. For this reason, the difference between the outputs corresponding to each multi-value number is relatively large and erroneous reading is unlikely to occur. Therefore, a simple output detection device can be used.
[0026]
This invention The multi-value storage element further includes a transistor that determines a binary state corresponding to the number of electrons trapped in the electron capture region as a binary storage element, and the electron capture rate of the transistor is determined between the transistors. It is characterized by being configured differently.
[0027]
Therefore, when a voltage is applied to the multi-value storage element at the time of writing, the number of electrons captured in the electron capture region is determined corresponding to the electron capture rate of each transistor. Further, the binary state of each transistor is determined in accordance with the number of captured electrons. Therefore, by changing the voltage or application time applied to the multilevel memory element, the number of transistors in a specific state among the binary states can be changed. Further, at the time of reading, the number of transistors in a specific state in the binary state corresponds to the output.
[0028]
Therefore, by associating the number of transistors in a specific state in the binary state with the multi-value number, the multi-value number can be stored in one write operation, and output can be performed once. A multi-value number can be read by the reading operation.
[0029]
This invention The multi-value storage element further includes a plurality of floating gate type transistors connected in parallel to form a multi-value storage element so that the capacitance ratio between the first capacitor and the second capacitor differs between the transistors. It is characterized by comprising.
[0030]
Therefore, when a voltage is applied to the multi-value storage element at the time of writing, the voltage applied to each transistor is determined corresponding to the capacitance ratio of each transistor. Further, the electron capture rate of each transistor depends on the voltage applied to each transistor. For this reason, the binary state of each transistor is determined corresponding to the capacitance ratio of each transistor.
[0031]
This invention The multi-value storage element is further characterized in that the capacitance ratio between the first capacitor and the second capacitor is different among the plurality of transistors by making the area of the second capacitor different.
[0032]
Therefore, in the step of forming the second capacitor, the only difference between the transistor constituting the multi-value storage element and the general floating gate type transistor is the mask pattern for determining the area of the second capacitor.
[0033]
This invention The multi-value storage element further includes a read-only gate, and the capacitance ratio between the third capacitor formed between the read-only gate and the floating gate and the first capacitor is substantially the same among the transistors. It is characterized by having comprised as follows.
[0034]
Therefore, at the time of reading, substantially the same voltage is applied to the floating gate of each transistor. For this reason, the output takes a step-like value that is substantially proportional to the number of binary storage elements that have not changed state. For this reason, the difference between the outputs corresponding to the multi-value number becomes almost uniform, and erroneous reading is less likely to occur.
[0035]
This invention The multi-value storage element of This invention In the multi-value storage element, the multi-value storage element is formed by a plurality of MNOS transistors connected in parallel so that the thickness of the first insulating film or the total thickness of the insulating films differs among the transistors. It is characterized by comprising.
[0036]
Therefore, when a voltage is applied to the multi-value storage element at the time of writing, the electric field strength generated in the first insulating film is determined corresponding to the thickness of the first insulating film of each transistor or the total thickness of the insulating film. Is done. Further, the electron capture rate of each transistor depends on the electric field strength generated in each transistor. For this reason, the binary state of each transistor is determined corresponding to the thickness of the first insulating film or the total thickness of the insulating film of each transistor. Further, by changing the voltage or application time applied to the multilevel memory element, the number of transistors in a specific state among the binary states can be changed.
[0037]
【Example】
FIG. 8A shows a circuit diagram of a memory cell 22 which is a multi-value storage element according to one embodiment of the present invention. The memory cell 22 is formed by connecting a plurality of transistors each having a floating gate which is an electron trapping region in parallel.
[0038]
In this embodiment, three transistors TR1 to TR3 are connected in parallel. That is, the drains D1 to D3 of the transistors TR1 to TR3 are all connected to the drain terminal TD. The sources S1 to S3 are all connected to the source terminal TS. The control gates CG1 to CG3 are all connected to the gate terminal TG.
[0039]
As will be described later, by applying a predetermined voltage to the drain terminal TD, the source terminal TS, and the gate terminal TG, writing, reading, and erasing of a multivalued number in the memory cell 22 are performed.
[0040]
FIG. 1 shows a planar structure of the memory cell 22. FIG. 2 is a diagram showing the dimensions of the gate portion of the memory cell 22. FIG. 3 is a diagram showing a cross-section PP of the memory cell 22. FIG. 4 is a diagram showing a cross section QQ and a cross section RR of the memory cell 22. The configuration of the memory cell 22 will be described with reference to FIGS.
[0041]
As described above, the memory cell 22 is configured by connecting three transistors TR1 to TR3 in parallel. First, the configuration of the transistor TR1 will be described.
[0042]
As shown in FIG. 4B, the substrate 24 is formed with a drain D1 and a source S1. A drain electrode TDA is provided in contact with the drain D1. A source electrode TSA is provided so as to be in contact with the source S1. Over the channel formation region CH1 between the drain D1 and the source S1, a gate oxide film MA1 and a floating gate FG1 are formed so as to be stacked in this order.
[0043]
As shown in FIG. 3, an interlayer oxide film MB1 and a control gate CG1 are further stacked in this order on the floating gate FG1.
[0044]
The channel formation region CH1, the gate oxide film MA1, and the floating gate FG1 form a first capacitor CA1. A second capacitor CB1 is formed by the floating gate FG1, the interlayer oxide film MB1, and the control gate CG1.
[0045]
As shown in FIG. 1, the transistors TR2 and TR3 are configured in substantially the same manner as the transistor TR1. However, the source S2 of the transistor TR2 is formed in an active region common to the source S1 of the transistor TR1. For this reason, the source electrode TSA is shared by the source S2 and the source S1. Further, the drain D2 of the transistor TR2 is formed in an active region common to the drain D3 of the transistor TR3. For this reason, the drain electrode TDB is shared by the drain D2 and the drain D3.
[0046]
The sources S1 to S3 of the transistors TR1 to TR3 are connected to the source terminal TS via the source electrodes TSA and TSB. The drains D1 to D3 are connected to the drain terminal TD via the drain electrodes TDA and TDB. The control gates CG1 to CG3 of the transistors TR1 to TR3 are all connected to the gate terminal TG.
[0047]
As shown in FIG. 1, the areas of the first capacitors CA1 to CA3 are all the same between the transistors TR1 to TR3. On the other hand, the areas of the second capacitors CB1 to CB3 are not the same. The second capacitor CB1 has the largest area, followed by the second capacitor CB2, and then the second capacitor CB3.
[0048]
Next, a method for manufacturing the memory cell 22 will be described with reference to FIGS. First, as shown in FIG. 5, a field oxide film 26 for element isolation is formed in a region other than the element formation region 30 of the substrate 24 made of a P-type semiconductor.
[0049]
Next, as shown in FIG. 6B, a gate oxide film MA is formed in the element formation region 30, and then floating gates FG1 to FG3 made of polysilicon are provided so as to be stacked on the gate oxide film MA. One ends of the floating gates FG1 to FG3 are formed so as to extend to the top of the field oxide film 26 in the control gate formation region 32 shown in FIG. 6A (see FIG. 3).
[0050]
Next, as shown in FIG. 7A, interlayer oxide films MB1 to MB3 are formed so as to cover the floating gates FG1 to FG3 in the control gate formation region 32, and thereafter, they are made of polysilicon so as to cover them. Control gates CG1 to CG3 are formed (see FIG. 3). As shown in FIG. 7A, the control gates CG1 to CG3 are formed to be connected to each other.
[0051]
Next, as shown in FIG. 4, after forming sources S1 to S3 and drains D1 to D3 in the element formation region 30, and forming an interlayer film (BPSG) 28 (see FIG. 3), as shown in FIG. 4A. Source electrodes TSA and TSB and drain electrodes TDA and TDB are formed.
[0052]
Thereafter, in a wiring process (not shown), the source electrodes TSA and TSB are connected to the source terminal TS, the drain electrodes TDA and TDB are connected to the drain terminal TD, and the control gates CG1 to CG3 are all connected to the gate terminal TG. Is done. In this way, the memory cell 22 is formed.
[0053]
Next, writing, reading, and erasing of a multi-valued number (any one of the four values “0”, “1”, “2”, and “3” in this embodiment) with respect to the memory cell 22 is performed. Each operation will be described.
[0054]
The correspondence relationship between the stored contents (multi-valued number) and the state of the memory cell 22 is as follows. The state in which the binary states of the transistors TR1 to TR3 are all “0” corresponds to the stored content “0” of the memory cell 22.
[0055]
The state in which only the binary state of the transistor TR1 is “1” corresponds to the stored content “1” of the memory cell 22. The state in which only the binary state of the transistors TR1 and TR2 is “1” corresponds to the stored content “2” of the memory cell 22. The state in which the binary states of the transistors TR1 to TR3 are all “1” corresponds to the stored content “3” of the memory cell 22.
[0056]
First, the operation for writing a multivalued number in the memory cell 22 will be described with reference to FIGS. When the electric field strength E generated in the gate oxide film MA1 of the first capacitor CA1 of the transistor TR1 shown in FIG. 3 exceeds a certain value Ec, electrons pass through the gate oxide film MA1 and are taken into the floating gate FG1 of the first capacitor CA1. (See FIG. 14). When the electrons are taken into the floating gate FG1, the binary state of the transistor TR1 becomes “1”.
[0057]
When the electric field strength E1 generated in the gate oxide film MA1 does not exceed the critical electric field strength Ec, electrons cannot pass through the gate oxide film MA1 and are not taken into the floating gate FG1 of the first capacitor CA1. Therefore, in this case, the binary state of the transistor TR1 remains “0”.
[0058]
In this way, by adjusting the electric field strengths E1 to E3 generated in the gate oxide films MA1 to MA3 of the transistors TR1 to TR3 constituting the memory cell 22, the state of each of the transistors TR1 to TR3 is set to “1” or “ Or 0 ".
[0059]
In this embodiment, when a multi-value number is written in the memory cell 22, as shown in FIG. 8A, the drain terminal TD is grounded, the source terminal TS is opened, and the multi-value number to be written to the gate terminal TG. A gate voltage Vtg corresponding to is applied.
[0060]
An equivalent circuit of the memory cell 22 at the time of writing is shown in FIG. 8B. The voltage V1 generated in the first capacitor CA1 is defined as follows. The capacitance of the first capacitor CA1 is CA1, the capacitance of the second capacitor CB1 is CB1, and the gate voltage applied to the gate terminal TG of the memory cell 22 is Vtg. It is expressed by the following formula.
[0061]
V1 = 1 / (1 + CA1 / CB1) * Vtg
On the other hand, the electric field strength E1 generated in the gate oxide film MA1 of the first capacitor CA1 is expressed by the following equation, where the thickness of the gate oxide film MA1 is da1.
[0062]
E1 = V1 / da1
Therefore, the critical voltage Vtg1 to be applied to the gate terminal TG of the memory cell 22 when the electric field intensity E1 becomes the critical electric field intensity Ec is expressed by the following equation.
[0063]
Vtg1 = (1 + CA1 / CB1) * da1 * Ec
Similarly, the critical voltages Vtg2 and Vtg3 are expressed by the following equations.
[0064]
Vtg2 = (1 + CA2 / CB2) * da2 * Ec
Vtg3 = (1 + CA3 / CB3) * da3 * Ec
That is, as shown in FIG. 8C, the gate terminal TG of the memory cell 22
Vtg <Vtg1
Even when the voltage Vtg is applied, all the binary states of the transistors TR1 to TR3 remain “0”, so that the stored content “0” of the memory cell 22 is maintained.
[0065]
Also, the gate terminal TG
Vtg1 ≦ Vtg <Vtg2
When the voltage Vtg is applied, only the binary state of the transistor TR1 is “1”, so that the memory content of the memory cell 22 is “1”.
[0066]
Similarly, the gate terminal TG
Vtg2 ≦ Vtg <Vtg3
When the voltage Vtg is applied, only the binary state of the transistors TR1 and TR2 is “1”, so that the memory content of the memory cell 22 is “2”.
[0067]
Also, the gate terminal TG
Vtg3 ≦ Vtg
When the voltage Vtg is applied, the binary state of all the transistors TR1 to TR3 is “1”, so that the memory content of the memory cell 22 is “3”.
[0068]
In this manner, by applying a predetermined gate voltage Vtg to the gate terminal TG of the memory cell 22, a desired multi-value number can be written into the memory cell 22 by one write operation.
[0069]
In this embodiment, the plane dimensions of the first capacitors CA1 to CA3 and the second capacitors CB1 to CB3 are set as shown in FIG. Further, the thicknesses da1 to da3 of the gate oxide films MA1 to MA3 forming the insulating films of the first capacitors CA1 to CA3 are set to 100 angstroms, and the interlayer oxide films MB1 to MB3 forming the insulating films of the second capacitors CB1 to CB3 are set. The film thickness is set to 200 angstroms.
[0070]
Therefore, the capacitance ratio CA1 / CB1 between the first capacitor CA1 and the second capacitor CB1 in the transistor TR1 is
CA1 / CB1 = 0.405
It becomes.
[0071]
Similarly, the capacity ratio CA2 / CB2 and the capacity ratio CA3 / CB3 are:
CA2 / CB2 = 0.6
CA3 / CB3 = 0.789
It becomes.
[0072]
Here, the critical electric field strength Ec is
Ec = 0.1 (V / Angstrom)
Assuming that critical voltages Vtg1, Vtg2, and Vtg3 are
Vtg1 = 14.05 (V)
Vtg2 = 16. (V)
Vtg3 = 17.89 (V)
It becomes.
[0073]
Therefore, in this embodiment, for example, the gate terminal TG of the memory cell 22 is
Vgt = 16 (V)
Is applied, the multi-value number “2” can be written into the memory cell 22.
[0074]
Next, the operation when reading the multi-value number “2” written in the memory cell 22 will be described with reference to FIG. When reading the contents of the memory cell 22, the source terminal TS is grounded, a voltage of 2V is applied to the gate terminal TG, and a voltage of 5V is applied to the drain terminal TD.
[0075]
When the memory cell 22 is brought into such a state, electrons are not captured in the floating gate FG3 of the transistor TR3 in the state “0”, so that a channel is formed in the channel formation region CH3 and the drain current Id3 flows ( (See FIG. 15C). On the other hand, since electrons are trapped in the floating gates FG1 and FG2 of the transistors TR1 and TR2 in the state “1”, no channel is formed in the channel formation regions CH1 and CH2, and no drain current flows (FIG. 15B). reference).
[0076]
Therefore, as shown in FIG. 9B, if the relationship between the output current Iout flowing through the drain terminal TD and the memory content of the memory cell 22 is obtained in advance, the value of the output current Iout is detected to store the memory cell 22. You can know the contents. In the above example,
Output current Iout = Id3
Therefore, it can be seen that the memory content of the memory cell 22 is “2”.
[0077]
In addition,
Output current Iout = Id1 + Id2 + Id3
If so, the stored content of the memory cell 22 is “0”.
Output current Iout = Id2 + Id3
If it is “1”,
Output current Iout = 0
If it is, it turns out that it is "3". As described above, the multi-value number stored in the memory cell 22 can be read by only one operation of detecting the output current Iout flowing through the drain terminal TD.
[0078]
Next, the operation for erasing the multi-value number written in the memory cell 22 will be described with reference to FIG. When erasing the contents of the memory cell 22, a voltage of 18V is applied to the source terminal TS, the gate terminal TG is grounded, and the drain terminal TD is opened.
[0079]
When the memory cell 22 is brought into such a state, electrons captured by the floating gates FG1 and FG2 of the transistors TR1 and TR2 in the state “1” are emitted and taken into the sources S1 and S2. By discharging the trapped electrons, the states of the transistors TR1 and TR2 return to “0”. As described above, the multi-value number stored in the memory cell 22 can be erased by only one operation.
[0080]
In the above-described embodiment, the capacitance ratio of the first capacitors CA1 to CA3 and the second capacitors CB1 to CB3 is changed between the transistors TR1 to TR3 by making the areas of the second capacitors CB1 to CB3 different from each other. However, in order to change the capacitance ratio among the transistors TR1 to TR3, the areas of the first capacitors CA1 to CA3 may be different from each other. Moreover, you may comprise so that the film thickness or dielectric constant of 1st capacitor | condenser CA1-CA3 or 2nd capacitor | condenser CB1-CB2 may each differ.
[0081]
Even if the capacitance ratios of the first capacitors CA1 to CA3 and the second capacitors CB1 to CB3 are the same, the film thicknesses da1 to da3 of the gate oxide films MA1 to MA3 of the first capacitors CA1 to CA3 are set to the respective transistors TR1. By forming them differently between TR3, the critical voltages Vtg1, Vtg2, and Vtg3 can be made different.
[0082]
Next, FIG. 11 shows a configuration of a memory array 34 in which a plurality of the above-described memory cells 22 are arranged. In the memory array 34, a plurality of memory cells 22a, 22b,... Each storing a multivalued number are arranged in a matrix.
[0083]
A source electrode Sa of the cell selection transistor TRa is connected to the drain terminal TDa of the memory cell 22a. The drain electrode Da of the cell selection transistor TRa is connected to the second line L2 (m−1). The gate electrode Ga of the cell selection transistor TRa is connected to the first line L1 (n + 1). Other memory cells 22b,... Are also connected in the same manner as the memory cell 22a.
[0084]
The first decoder 36 selects one line from the first line group L1 including a plurality of first lines L1 (n−1), L1 (n), L1 (n + 1),. Has been placed. The second decoder 38 selects one line from the second line group L2 composed of a plurality of second lines L2 (m−1), L2 (m), L2 (m + 1),. Has been placed.
[0085]
Of the memory cells 22a, 22b,... Constituting the memory array 34, an operation when reading the contents of a desired memory cell, for example, the memory cell 22a will be described. First, a first line selection command for selecting a line connected to the gate electrode Ga of the cell selection transistor TRa of the memory cell 22a from the first line group L1 is input to the first decoder 36. The first decoder 36 selects the first line L1 (n + 1) according to the line selection command. A voltage of 5V is applied to the selected first line L1 (n + 1).
[0086]
When the first line L1 (n + 1) is selected, a voltage of 5V is applied to the first line L1 (n + 1), and at the same time, the memory cells 22a, 22b,... Connected to the first line L1 (n + 1). A voltage of 2 V is applied to each of the gate terminals TG (see FIG. 9A).
[0087]
Next, a second line selection command for selecting a line connected to the drain electrode Da of the cell selection transistor TRa of the memory cell 22a from the second line group L2 is input to the second decoder 38. . The second decoder 38 selects the second line L2 (m−1) according to the line selection command. A voltage of 5 V is applied to the selected second line L2 (m−1).
[0088]
By selecting the first line L1 (n + 1) and the second line L2 (m−1), the cell selection transistor TRa is turned on. Therefore, a current corresponding to the multi-value number written in the memory cell 22a flows from the second decoder 38 to the memory cell 22a via the second line L2 (m−1) and the cell selection transistor TRa. By detecting this current, the stored contents (multi-value number) of the memory cell 22a can be read.
[0089]
As described above, the multi-value number written in a desired memory cell among the memory cells 22a, 22b,... Constituting the memory array 34 can be read by one read operation.
[0090]
Next, FIG. 12 shows a planar configuration of a memory cell 40 which is a multi-value storage element according to another embodiment of the present invention. This memory cell 40 is obtained by adding read-only gates RG1 to RG3 to the memory cell 22 shown in FIG.
[0091]
In memory cell 40, one ends of floating gates FG1a to FG1c are formed to extend to read-only gate formation region 42. Interlayer oxide films MC1 to MC3 are formed so as to cover floating gates FG1a to FG3c in read only gate formation region 42, and read only gates RG1 to RG3 made of polysilicon are formed so as to cover these. Yes. The read-only gates RG1 to RG3 are formed so as to be connected to each other, and are all connected to the read gate terminal TGR.
[0092]
The write and erase operations of the memory cell 40 are performed using the gate terminal TG as in the case of the memory cell 22, while the read operation is performed using the read gate terminal TGR. The read operation is performed using the read gate terminal TGR for the following reason.
[0093]
Floating gates FG1a to FG3a, interlayer oxide films MC1 to MC3, and read-only gates RG1 to RG3 form third capacitors CC1 to CC3. As shown in FIG. 12, the areas of the third capacitors CC1 to CC3 are all formed identically. On the other hand, the areas of the first capacitors CA1 to CA3 (see FIG. 1) are all the same. Therefore, the capacitance ratios of the third capacitors CC1 to CC3 and the first capacitors CA1 to CA3 are the same between the transistors TR1 to TR3.
[0094]
Therefore, in the read operation, the voltages generated in the floating gates FG1a to FG3a of the transistors TR1 to TR3 are the same as in the memory cell 22 of FIG. For this reason, the output current Iout takes a step-like value substantially proportional to the number of transistors in the “0” state. That is, this is because the difference between the output currents Iout corresponding to the multi-value number becomes almost uniform, and erroneous reading is less likely to occur.
[0095]
In the above-described embodiment, the read-only gates RG1 to RG3 are provided, and by setting the same voltage to be applied to the floating gates FG1 to FG3 at the time of reading, the output currents Iout corresponding to the multivalued number are set. However, the channel formation regions CH1 to CH3 (see FIG. 4B) of the transistors TR1 to TR3 may be formed of an N-type semiconductor.
[0096]
With this configuration, the output current Iout can be obtained without applying a voltage to the floating gates FG1 to FG3, that is, the control gates CG1 to CG3, at the time of reading. For this reason, as in the above-described embodiment, the difference between the output currents Iout corresponding to the multi-value number is almost uniform at the time of reading.
[0097]
Next, FIG. 13 shows a cross-sectional structure of a transistor 52 constituting a memory cell which is a multi-value storage element according to still another embodiment of the present invention. The transistor 52 is an MNOS (Metal Nitride Oxide Semi-conductor) type transistor. The transistor 52 is formed by stacking a silicon oxide film 56, a silicon nitride film 58, and a gate electrode 60 in this order on a channel formation region 62 of the substrate 54.
[0098]
The substrate 54 is grounded and a high voltage is applied to the gate electrode 60, whereby electrons are trapped in the lowermost portion of the silicon nitride film 58. The state in which electrons are captured is “1” and the state in which electrons are not captured is “0”, as in the transistors TR1 to TR3 used in the memory cell 22 of FIG.
[0099]
By changing the thickness d1 of the silicon oxide film 56 or the total thickness d2 of the silicon oxide film 56 and the silicon nitride film 58, the electron capture rate of the transistor 52 can be changed. This is because, by changing these thicknesses, the electric field strength acting on the silicon oxide film 56 where electrons should jump is changed.
[0100]
Therefore, by arranging a plurality of transistors 52 having different electron capture rates in parallel, a memory cell capable of writing and reading a multi-valued number can be configured in the same manner as the transistors TR1 to TR3 in FIG.
[0101]
In each of the above-described embodiments, the case where the multi-value storage element is configured using the floating gate type transistors TR1 to TR3 and the MNOS type transistor 52 has been described as an example. It is not limited to transistors.
[0102]
Moreover, although the case where the binary storage element is a transistor that determines a binary state corresponding to the number of electrons captured in the electron capture region has been described as an example, the present invention is not limited to this. .
[0103]
In addition, the number of transistors that cause a change in the binary state is determined in accordance with the magnitude of the voltage applied to the multi-value storage element. Correspondingly, it can also be configured to determine the number of transistors that cause a change in the binary state.
[0104]
In each of the above-described embodiments, the case where the present invention is applied to a nonvolatile memory has been described as an example. However, the present invention can also be applied to a volatile memory.
[0105]
【The invention's effect】
This invention Multi-value storage element, This invention Memory arrays, and This invention The number of binary storage elements that cause a state change corresponding to the magnitude or application time of the voltage applied to the multi-value storage element during writing is prepared by preparing a plurality of binary storage elements. And at the time of reading, an output corresponding to the number of binary storage elements that have caused a state change is obtained.
[0106]
Therefore, by making the number of binary storage elements that cause a state change at the time of writing correspond to the multi-value number, it is possible to make the applied voltage or application time correspond to the multi-value number. For this reason, by applying an applied voltage or application time corresponding to the multi-value number to the multi-value storage element, the multi-value number can be stored in one write operation.
[0107]
The output and the multi-value number correspond to each other. For this reason, a multi-value number can be read by one output reading operation. Further, at the time of reading, the output takes a stepwise value determined by the number of binary storage elements that have caused a change in state. For this reason, the difference between the outputs corresponding to each multi-value number is relatively large and erroneous reading is unlikely to occur. Therefore, a simple output detection device can be used.
[0108]
That is, it is possible to obtain a simple and highly reliable multi-value storage element capable of high-speed writing and reading.
[0109]
This invention The multi-value storage element further includes a transistor that determines a binary state corresponding to the number of electrons trapped in the electron capture region as a binary storage element, and the electron capture rate of the transistor is determined between the transistors. It is characterized by being configured differently.
[0110]
Therefore, when a voltage is applied to the multi-value storage element at the time of writing, the number of electrons captured in the electron capture region is determined corresponding to the electron capture rate of each transistor. Further, the binary state of each transistor is determined in accordance with the number of captured electrons. Therefore, by changing the voltage or application time applied to the multilevel memory element, the number of transistors in a specific state among the binary states can be changed. Further, at the time of reading, the number of transistors in a specific state in the binary state corresponds to the output.
[0111]
Therefore, by associating the number of transistors in a specific state in the binary state with the multi-value number, the multi-value number can be stored in one write operation, and output can be performed once. A multi-value number can be read by the reading operation. That is, it is possible to easily obtain a multi-value storage element that can be written and read at high speed and that is simple and highly reliable.
[0112]
This invention The multi-value storage element further includes a plurality of floating gate type transistors connected in parallel to form a multi-value storage element so that the capacitance ratio between the first capacitor and the second capacitor differs between the transistors. It is characterized by comprising.
[0113]
Therefore, when a voltage is applied to the multi-value storage element at the time of writing, the voltage applied to each transistor is determined corresponding to the capacitance ratio of each transistor. Further, the electron capture rate of each transistor depends on the voltage applied to each transistor. For this reason, the binary state of each transistor is determined corresponding to the capacitance ratio of each transistor.
[0114]
That is, by a simple method of forming the transistors with different capacitance ratios, it is possible to obtain a simple and highly reliable multi-value storage element capable of high-speed writing and reading.
[0115]
This invention The multi-value storage element is further characterized in that the capacitance ratio between the first capacitor and the second capacitor is different among the plurality of transistors by making the area of the second capacitor different.
[0116]
Therefore, in the step of forming the second capacitor, the only difference between the transistor constituting the multi-value storage element and the general floating gate type transistor is the mask pattern for determining the area of the second capacitor. That is, a multi-value storage element can be easily manufactured without changing the conventional process.
[0117]
This invention The multi-value storage element further includes a read-only gate, and the capacitance ratio between the third capacitor formed between the read-only gate and the floating gate and the first capacitor is substantially the same among the transistors. It is characterized by having comprised as follows.
[0118]
Therefore, at the time of reading, substantially the same voltage is applied to the floating gate of each transistor. For this reason, the output takes a step-like value that is substantially proportional to the number of binary storage elements that have not changed state. For this reason, the difference between the outputs corresponding to the multi-value number becomes almost uniform, and erroneous reading is less likely to occur.
[0119]
That is, it is possible to obtain a simpler and more reliable multi-value storage element capable of high-speed writing and reading.
[0120]
This invention The multi-value storage element is formed of a plurality of MNOS-type transistors connected in parallel so that the thickness of the first insulating film or the total thickness of the insulating films differs among the transistors. It is characterized by comprising.
[0121]
Therefore, when a voltage is applied to the multi-value storage element at the time of writing, the electric field strength generated in the first insulating film is determined corresponding to the thickness of the first insulating film of each transistor or the total thickness of the insulating film. Is done. Further, the electron capture rate of each transistor depends on the electric field strength generated in each transistor. For this reason, the binary state of each transistor is determined corresponding to the thickness of the first insulating film or the total thickness of the insulating film of each transistor. Further, by changing the voltage or application time applied to the multilevel memory element, the number of transistors in a specific state among the binary states can be changed.
[0122]
That is, a simple and highly reliable multi-value storage element capable of high-speed writing and reading by a simple method in which the thickness of the first insulating film or the total thickness of the insulating film of each transistor is different. Can be obtained.
[Brief description of the drawings]
1 is a plan view of a memory cell according to an embodiment of the present invention;
FIG. 2 is a view showing dimensions of a first capacitor and a second capacitor of a memory cell according to an embodiment of the present invention.
FIG. 3 is a view showing a part of a cross-sectional structure of a memory cell according to an embodiment of the present invention;
FIG. 4 is a diagram showing a part of a cross-sectional structure of a memory cell according to an embodiment of the present invention.
FIG. 5 is a drawing showing part of a manufacturing process of a memory cell according to an embodiment of the present invention;
FIG. 6 is a drawing showing part of a manufacturing process of a memory cell according to an embodiment of the present invention;
FIG. 7 is a drawing showing part of a manufacturing process of a memory cell according to an embodiment of the present invention;
FIG. 8 is a diagram showing a state at the time of writing a memory cell according to an embodiment of the present invention;
FIG. 9 is a diagram showing a state when a memory cell is read according to an embodiment of the present invention;
FIG. 10 is a diagram showing a state at the time of erasing a memory cell according to an embodiment of the present invention;
FIG. 11 is a diagram showing a configuration of a memory array using memory cells according to an embodiment of the present invention.
FIG. 12 is a plan view of a memory cell according to another embodiment of the present invention.
FIG. 13 is a diagram showing a configuration of a transistor used in a memory cell according to still another embodiment of the present invention.
FIG. 14 is a cross-sectional view of a conventional memory cell.
FIG. 15 is a diagram showing a state of reading a conventional memory cell.
[Explanation of symbols]
22 .... Memory cell
CA1 ... 1st capacitor
CA2 ... 1st capacitor
CA3 ... 1st capacitor
CB1 ... Second capacitor
CB2 ... Second capacitor
CB3 ... 2nd capacitor
TD ... Drain terminal
TG ... Gate terminal
TR1 ... Transistor
TR2 ... Transistor
TR3: Transistor

Claims (7)

A multi-value storage element comprising a plurality of binary storage elements,
Each binary storage element having an electron trapping region, a transistor which determines the binary state corresponding to the number of electrons trapped in the electron capture region,
The electron capture rate of the transistors is configured to be different between the transistors,
Each of the gates, drains and sources of the transistors are all connected, and a plurality of transistors are connected in parallel .
By configuring so as to determine whether or not each transistor causes a change in the binary state according to the magnitude or application time of the voltage applied to the gates of the transistors connected in parallel at the time of writing, Enables multi-valued writing to memory elements,
At the time of reading, a drain current corresponding to the number of electrons captured by each transistor causing a change in the binary state flows between the drain and source of the transistors connected in parallel, and the multivalue written in the multivalue storage element By being configured to output a current according to the number, the multi-value number can be read from the multi-value storage element,
A multi-value storage element characterized by the above. The multi-value storage element according to claim 1.
The transistor is a floating gate type transistor;
The capacitance ratio between the first capacitor formed between the channel formation region and the floating gate of the transistor and the second capacitor formed between the floating gate and the control gate is different between the transistors. What
It is characterized by. The multi-value storage element according to claim 3,
The capacitance ratio between the first capacitor and the second capacitor is configured to be different among the plurality of transistors by changing the area of the second capacitor.
It is characterized by. The multi-value storage element according to claim 2 or claim 3,
In addition to a read-only gate,
The third capacitor formed between the read-only gate and the floating gate and the first capacitor have a capacitance ratio that is substantially the same between the transistors;
It is characterized by. The multi-value storage element according to claim 1.
The transistor is an MNOS transistor;
The multi-value storage element is formed by a plurality of the transistors connected in parallel,
The thickness of the first insulating film formed immediately above the channel formation region of the transistor or the total thickness of the insulating film formed between the channel formation region and the gate electrode is different between the transistors. Configured,
It is characterized by.   A memory array comprising a plurality of the multi-value storage elements according to claim 1.   Each binary storage element has an electron capture region, and is a transistor that determines a binary state corresponding to the number of electrons captured in the electron capture region,
  The electron capture rate of the transistors is configured to be different between the transistors,
  A method for storing and reproducing a multi-value storage element comprising a plurality of binary storage elements,
  Each of the gates, drains and sources of the transistors are all connected, and a plurality of transistors are connected in parallel.
By configuring so as to determine whether or not each transistor causes a change in the binary state according to the magnitude or application time of the voltage applied to the gates of the transistors connected in parallel at the time of writing, Enables multi-valued writing to memory elements,
At the time of reading, a drain current corresponding to the number of electrons captured by each transistor causing a change in the binary state flows between the drain and source of the transistors connected in parallel, and the multivalue written in the multivalue storage element By being configured to output a current according to the number, the multi-value number can be read from the multi-value storage element,
  A method for writing and reading a multi-value storage element.

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