JP3663562B2 - Interference canceller and channel estimation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multistage interference canceller and a channel estimation method in a CDMA communication system.
In the CDMA communication system, an interference canceller is used to improve a signal power to interference power ratio (SIR). In this case, there is a method in which pilot symbols are added before and after a fixed-length information symbol to form a slot, a frame is formed by a plurality of the slots, channel estimation is performed using the pilot symbol, and interference on the information symbol is removed. There is a need to reduce the delay in a known multistage interference canceller.
[0002]
[Prior art]
FIG. 12 is an explanatory diagram of a conventional multi-stage interference canceller. 71 is an interference canceller unit (interference replica generation unit) ICU corresponding to each stage._1,1~ ICU_{1, k}, ICU_2,1~ ICU_{2, k},... 72 is a combining unit, 73 is a reception processing unit REC corresponding to the user at the final stage.₁~ REC_k74 are delay circuits DL.
[0003]
As shown above, the received signal input to the interference canceller is a slot in which pilot symbols of a known data pattern are added before and after a fixed-length information symbol to form a slot, and a frame is composed of the plurality of slots. , First stage interference canceller unit 71 (ICU_1,1~ ICU_{1, k}) And the delay circuit 74. The delay circuit 74 in each stage is for compensating the processing time in each stage.
[0004]
This first stage interference canceller unit 71 (ICU_1,1~ ICU_{1, k}) Is output as an interference replica (interference residual estimation signal) d and a symbol replica s, and an interference replica d from each interference canceller unit 71 and a received signal via the delay circuit 74 are input to the combining unit 72. The error replica e is output by synthesizing and subtracting the interference replica d from the received signal.
[0005]
In the second stage, the error signal e from the combining unit 72 and the first stage interference canceller unit 71 (ICU)_1,1~ ICU_{1, k}) From the user-friendly interference canceller unit 71 (ICU)_2,1~ ICU_{2, k}) And each interference canceller unit 71 (ICU)_2,1~ ICU_{2, k}) Is output from the interference replica d and the symbol replica s, and the interference replica d is combined and subtracted from the error signal e via the delay circuit 74 to output an error signal e to be added to the next stage.
[0006]
The above-described operation is repeated at each stage, the error signal e approaches zero, and a symbol replica s from which interference is removed is obtained, and the reception processing unit 73 (REC) at the final stage is obtained.₁~ REC_k) Is input with the error signal e and the symbol replica s, RAKE reception processing is performed, and a user symbol is output.
[0007]
FIG. 13 is an explanatory diagram of a conventional interference canceller unit, showing the main part of each interference canceller unit (interference replica generation unit) 71 of FIG. 12, and in the case of a three-finger configuration in rake combining Indicates. In the figure, 81 is a despreading processing unit, 82 is a combining unit (Σ), 83 is a determining unit, 84 is a diffusion processing unit, 85 is a combining unit (Σ), 86 is a despreader, and 87 is an adder. , 88 are multipliers, 89 is a channel estimation circuit, 90 is a multiplier, 91 is an adder, and 92 is a respreader.
[0008]
The error signal e in the previous stage (received signal in the case of the first stage) and the symbol replica signal s in the previous stage (zero in the case of the first stage) are the inverse of the correspondence to the delay profile of the received signal (corresponding to the path of the delayed wave). The signal is input to the spread processing unit 81 and despread and demodulated by the spread code in the despreader 86. The received signal in this case is input to the interference canceller in a state where it is synchronized with the spreading code.
[0009]
The despread demodulated signal and the preceding symbol replica signal (zero in the first stage) are added by the adder 87, and the received symbol vector R of the i-th path is added._iIs generated, and the received symbol vector R of this i-th pass_iIs input to the channel estimation circuit 89, and the estimated value (estimated channel vector) ξ of the channel (fading vector) of the i-th path from the channel estimation circuit 89_iIs output.
[0010]
The multiplier 88 also includes a received symbol vector R._iAnd the channel estimate ξ_iComplex conjugate of_i ^*Are input and multiplied, and a signal subjected to weighting and phase compensation proportional to the amplitude of the channel estimation value is output, and maximum ratio combining is performed in the combining unit 82, and the combined received symbol vector ΣR_iξ_i ^*Is output.
[0011]
The determination unit 83 determines the combined received symbol vector ΣR_iξ_i ^*Is temporarily determined, and a user symbol is determined in a reception processing unit that inputs an error signal and a symbol replica signal from the final stage of the interference canceller. In the determination unit 83 at each stage, the combined received symbol vector ΣR_iξ_i ^*Estimated information symbol vector Z_sIs input to the multiplier 90 of the diffusion processing unit 84 corresponding to the path of the delayed wave. And the estimated information symbol vector Z_sFor the channel estimate ξ_iIs multiplied to generate a symbol replica signal s for each path and output to the next stage.
[0012]
Also, the symbol replica signal s of the previous stage is subtracted from the symbol replica signal s of each path by the adder 91, and the output signal of the adder 91 is spread by the spreading code by the respreader 92, and The spread output signal is synthesized by the synthesis unit 85 to output the interference replica signal d.
[0013]
The channel estimation processing in the above-described channel estimation circuit 89 is performed using known pilot symbols before and after the slot, and one slot sandwiched between pilot symbols by interpolation or averaging of the channel estimation values based on the known pilot symbols. The means for making the channel estimation value for the minute effective in a fast fluctuation fading environment in a mobile communication system or the like.
[0014]
[Problems to be solved by the invention]
In the conventional multi-stage interference canceller, by performing channel estimation using the pilot symbols before and after the slot for each stage, the time until the pilot symbol at the rear end of the slot is received, Since it takes time to perform channel estimation and to perform interference cancellation processing for the slot, processing in one stage requires time of two slots.
[0015]
In addition, in order to obtain sufficient interference cancellation characteristics, at least 3 to 4 stages are required. As described above, a processing time of 2 slots length is required for each stage, so that a delay time of 6 to 8 slots can be obtained. Become. Further, if the number of stages is increased in order to further improve the interference cancellation characteristic, there is a problem that the delay time becomes longer.
[0016]
Therefore, it is conceivable to reduce the delay time by performing channel estimation using only the pilot symbol at the front end of the slot and performing the interference removal processing of the slot using the result. However, in the fast fluctuation fading environment, there is a problem that the channel estimation accuracy is lowered, and thereby the interference cancellation characteristic is remarkably deteriorated, and the effect as an interference canceller is hardly obtained.
An object of the present invention is to reduce delay time by reducing a decrease in channel estimation accuracy.
[0017]
[Means for Solving the Problems]
  The interference canceller of the present invention inputs (1) a received signal having a frame structure composed of a plurality of slots in which pilot symbols are added before and after a fixed-length information symbol, and uses a channel estimation value based on the pilot symbols,After demodulating the information symbol,In a multi-stage type interference canceller in which stages including an interference canceller unit 1 that removes interference included in information symbols are cascade-connected,Interference canceller unit 1Transfer the channel estimation value of at least pilot symbols in the channel estimation circuit of the interference canceller unit to the channel estimation circuit of the interference canceller unit in the other stage.Then, the channel estimation circuit of the interference canceller unit of each stage performs the averaging process or the interpolation process between the channel estimation value in the stage and the channel estimation value transferred from the other stage, and performs the slot calculation. Perform channel estimationIt has a configuration. That is, assuming that the delay time between the stages is one slot length which is half that of the conventional example, the pilot symbol at the front end of the slotInChannel estimation withFor example,Since the processing time overlaps with the pilot symbol estimation at the rear end of the slot in the previous stage, the channel estimation value in this previous stageAlsoBy using this, it is equivalent to the case where the channel estimation values of pilot symbols before and after the information symbol are used, and the delay time between stages can be shortened.
[0018]
(2) The channel estimation value based on the pilot symbol at the front end of the slot in the channel estimation circuit of the interference canceller unit 1 is transferred to the channel estimation circuit of the interference canceller unit 1 in each of the preceding stage and the subsequent stage, The channel estimation value based on the pilot symbol at the rear end of the slot can be transferred to the channel estimation circuit of each interference canceller unit in the preceding stage, the succeeding stage, and the succeeding stage. In this case, the delay time between stages can be ½ slot length.
[0019]
(3) The channel estimation value based on the pilot symbol at the front end of the slot in the channel estimation circuit of the interference canceller unit 1 can be transferred to the channel estimation circuits of all the interference canceller units in the previous stage. . In this case, the delay time between stages can be set to one symbol length.
[0020]
(4) In the channel estimation circuit of the interference canceller unit of each stage in the first half of the cascaded stages, the channel estimation value by the pilot symbol at the front end of the slot is used as the channel estimate of all the interference canceller units in the previous stage. And a channel estimation value based on at least the pilot symbol in the channel estimation circuit of the interference canceller unit in each of the latter half stages is transferred to the channel estimation circuit of the interference canceller unit in the other stage. be able to. In this case, the delay time between the stages in the first half of the multistage interference canceller is set to one symbol length, the delay time between the stages in the second half is set to one slot length, and the overall delay time is shortened and the channel is shortened. The estimation accuracy can be improved.
[0021]
According to the channel estimation method of the present invention, (5) a received signal having a frame structure consisting of a plurality of slots in which pilot symbols are added before and after a fixed-length information symbol is input, and the channel estimation value based on the pilot symbols is used to In a channel estimation method in a multi-stage type interference canceller in which stages including interference canceller units for removing interference included in information symbols are cascaded, a channel based on a pilot symbol at the front end of the slot in the stage Using the estimated value and the channel estimated value based on the pilot symbol at the rear end of the slot in the preceding stage, the process of estimating the channel of the slot by the averaging process or the interpolation process is included. In this case, the delay time between stages can be one slot long.
[0022]
(6) A received signal having a frame structure composed of a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol is input, and interference included in the information symbol is removed using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage type interference canceller in which stages including interference canceller units are connected in cascade, a channel estimation value based on a pilot symbol at the front end of the slot in the stage, and Channel estimation using the pilot symbol at the rear end of the slot in the stage preceding the two stages and performing channel estimation in the first half of the slot, and the rear end of the slot in the previous stage for this stage. Channel with pilot symbols Value and, using the channel estimation value by the pilot symbols at the front end of in the slot to the subsequent stage for the stage, is intended to include a process of performing in channel estimation in the second half of the pilot. In this case, the delay time between stages can be ½ slot long.
[0023]
(7) A received signal having a frame structure composed of a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol is input, and interference included in the information symbol is removed using a channel estimation value based on the pilot symbol. In a channel estimation method in a multi-stage type interference canceller in which stages including interference canceller units are connected in cascade, in each stage in the subsequent stage, the symbol corresponds to the information symbol of the slot in the stage. The method includes channel estimation using a channel estimation value based on a pilot symbol at the front end of the slot. In this case, the delay time between stages can be set to one symbol length.
[0024]
(8) A received signal having a frame structure consisting of a plurality of slots with pilot symbols added before and after a fixed-length information symbol is input, and interference contained in the information symbol is removed using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage type interference canceller in which stages including interference canceller units connected in cascade are connected, in the channel estimation circuit of the interference canceller unit in each stage in the first half of the cascaded stages The channel estimation value based on the pilot symbol at the front end of the slot is transferred to the channel estimation circuit of all the interference canceller units in the previous stage, so that the channel estimation is performed for the symbol corresponding to the information symbol in the slot on the front stage side. , The interference key of each stage in the second half The channel estimation value of at least the pilot symbol in the channel estimation circuit of the canceller unit is transferred to the channel estimation circuit of the interference canceller unit of the other stage, and the channel estimation value by the pilot symbol of the front end of the slot; This includes a step of performing channel estimation of the slot using the channel estimation value of the pilot symbol at the rear end of the slot in the preceding stage. In this case, the delay time between the first half stages in the multi-stage type can be set to one symbol length, and the delay time between the second half stages can be set to one slot length.
[0025]
(9) Input a received signal having a frame structure composed of a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, and remove interference included in the information symbol using a channel estimation value of the pilot symbol. In a channel estimation method in a multistage type interference canceller in which stages including interference canceller units are connected in cascade, information symbols sandwiched between the pilot symbols and temporarily determined are estimated together with channel estimation using the pilot symbols. And performing channel estimation using the method.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is an explanatory diagram of a first embodiment of the present invention. 1 is an interference canceller unit (interference replica generation unit) ICU corresponding to a user for each stage._1,1~ ICU_{1, k}, ICU_2,1~ ICU_{2, k},... 2 is a combining unit, 3 is a reception processing unit REC corresponding to the user at the final stage.₁~ REC_kReference numeral 4 denotes a delay circuit DL.
[0027]
A received signal in which a frame is formed by slots in which pilot symbols are added before and after a fixed-length information symbol is a first stage interference canceller unit 1 (ICU)._1,1~ ICU_{1, k}) And the delay circuit 4. The delay circuit 4 in each stage is for compensating the processing time in each stage. When the processing time corresponds to 1 slot length, the delay time of the delay circuit 4 is set to 1 slot length. Select. Further, the channel estimation value ξ in the interference canceller unit 1 of a certain stage is configured to be used in the interference canceller unit of another stage.
[0028]
First stage interference canceller unit 1 (ICU) to which a received signal is input_1,1~ ICU_{1, k}) Is output from the interference replica d and the symbol replica s, and the interference replica d from each interference canceller unit 1 and the received signal via the delay circuit 4 are input to the combining unit 2 and combined from the received signal. The error signal e is output by subtracting the interference replica d.
[0029]
In the second stage, the error signal e from the synthesizer 2 and the interference canceller unit 1 (ICU) of the first stage._1,1~ ICU_{1, k}) From the user-friendly interference canceller unit 1 (ICU)_2,1~ ICU_{2, k}), And each interference canceller unit 1 (ICU)_2,1~ ICU_{2, k}) Is output as an interference replica d and a symbol replica s, and the interference replica d is combined and subtracted from the error signal e via the delay circuit 4 to output an error signal e to be applied to the next stage.
[0030]
Each stage is cascaded to form an interference canceller, and the above operation is repeated in each stage, the error signal e approaches zero, and a symbol replica s from which interference is removed is obtained, and the final stage is received. Processing unit 3 (REC₁~ REC_k) Is input with the error signal e and the symbol replica s, RAKE reception processing is performed, and a user symbol is output.
[0031]
FIG. 2 is an explanatory diagram of the interference canceller unit according to the first embodiment of the present invention, showing the main part of each interference canceller unit (interference replica generation unit) 1 of FIG. Similarly, the case of a three-finger configuration in RAKE synthesis is shown. In the figure, 11 is a despreading processing unit, 12 is a first combining unit (Σ), 13 is a determining unit, 14 is a diffusion processing unit, 15 is a second combining unit (Σ), and 16 is a despreading unit. , 17 is an adder, 18 is a multiplier, 19 is a channel estimation circuit, 20 is a multiplier, 21 is an adder, and 22 is a respreader.
[0032]
The error signal e in the previous stage (received signal in the case of the first stage) and the symbol replica signal s in the previous stage (zero in the case of the first stage) are the inverse of the correspondence to the delay profile of the received signal (corresponding to the path of the delayed wave). The signal is input to the spread processing unit 11 and despread and demodulated by the spread code in the despreader 16. The received signal in this case is input to the interference canceller in a state where it is synchronized with the spreading code.
[0033]
The despread demodulated signal and the preceding symbol replica signal (zero in the first stage) are added by the adder 17 to obtain the received symbol vector R of the i-th path._iIs generated, and the received symbol vector R of this i-th pass_iAre input to the channel estimation circuit 19 and estimated values ξ of the channel (fading vector) of the i-th path using pilot symbols added to the front and rear ends of each slot._iIs output. This channel estimate ξ_iIs forwarded to the user-facing interference canceller unit at the other stage and the channel estimate ξ at that stage_iAs a result, the processing time can be shortened.
[0034]
The multiplier 18 also receives a received symbol vector R._iAnd the channel estimate ξ_iComplex conjugate of_i ^*Are input and multiplied, and a signal subjected to weighting and phase compensation proportional to the amplitude of the channel estimation value is output, the maximum ratio combining is performed in the first combining unit 12, and the combined received symbol vector ΣR_iξ_i ^*Is output.
[0035]
The determination unit 13 uses the combined received symbol vector ΣR_iξ_i ^*Is temporarily determined, and a user symbol is determined in a reception processing unit that inputs an error signal and a symbol replica signal from the final stage of the interference canceller. In the determination unit 13 in each stage, the combined reception symbol vector ΣR_iξ_i ^*Estimated information symbol vector Z_sIs input to the multiplier 20 of the diffusion processing unit 14 corresponding to the path of the delayed wave. And the estimated information symbol vector Z_sFor the channel estimate ξ_iIs multiplied to generate a symbol replica signal s for each path and output to the next stage.
[0036]
Further, the symbol replica signal s of the previous stage is subtracted from the symbol replica signal s of each path by the adder 21, and the output signal of the adder 21 is spread by the spreading code by the respreader 22. The spread output signal is combined by the second combining unit 15 to output the interference replica signal d.
[0037]
FIG. 3 is a diagram for explaining the operation of the first embodiment of the present invention, showing slots A, B,... In the N-1 stage and the next N stage of the multistage interference canceller. In each of the slots A, B,..., Pilot symbols are added before and after the information symbols, respectively, and transferred from the N−1 stage to the next N stage.
[0038]
In that case, in the N-1 stage, channel estimation value ξa by the pilot symbol at the front end of slot A_N-1And channel estimation value ξb by the pilot symbol at the rear end of slot A_N-2The channel estimation of slot A is performed by the average or interpolation interpolation with the above, and the interference removal processing of slot A is performed. Note that the time for obtaining the channel estimation value by the pilot symbol at the rear end of the slot A in the N-1 stage and the time for obtaining the channel estimation value by the pilot symbol at the front end of the slot A in the next N stage are exactly the same. Indicates the case where they are equal.
[0039]
Therefore, when processing slot A in the N stage, the channel estimation value ξa based on the pilot symbol at the front end of the slot A estimated in the N stage_NAnd the channel estimated value ξb by the pilot symbol at the rear end of the slot A estimated at the N−1 stage of the preceding stage with respect to the N stage_N-1In the N stage, interference cancellation processing for slot A can be performed without waiting until the pilot symbol at the rear end of slot A is transferred. That is, the delay time between stages can be set to one slot length.
[0040]
FIG. 4 is a flowchart of the main part of the first embodiment of the present invention. In the N-1 stage, as described above, the channel estimation value ξa based on the pilot symbol at the front end of the slot A is shown._N-1And this channel estimate ξa_N-1And the channel estimation value ξb by the pilot symbol at the rear end of the slot A in the N-2 stage preceding the stage_N-2Are used to process slot A, and then the channel estimate ξb from the pilot symbol at the front end of slot B_N-1And the channel estimate ξb_N-1Are transferred to the N stage subsequent to the N-1 stage. That is, the channel estimation value ξb estimated by the channel estimation circuit 19 shown in FIG. 2 of the N-1 stage interference canceller unit._N-1Is transferred to the channel estimation circuit 19 shown in FIG. 2 of the interference canceller unit of the N stage subsequent to the N−1 stage.
[0041]
Also, the channel estimated value ξc by the pilot symbol at the rear end of the slot B estimated by the channel estimation circuit 19 shown in FIG. 2 of the N-2 stage interference canceller unit._N-2Is transferred to the channel estimation circuit 19 shown in FIG. 2 of the interference canceller unit of the N-1 stage, which is the subsequent stage, with respect to the N-2 stage. Therefore, in the N-1 stage, the channel estimation value ξb_N-1And the estimated channel value ξc from the preceding N-2 stage for this stage_N-2Are used to process slot B. Similarly, for the next slot C, the channel estimation value ξ by the pilot symbol at the front end thereof_cN-1And processing of slot C is performed using the channel estimation value from the N-2 stage.
[0042]
Similarly, in the N stage, the channel estimated value ξa based on the pilot symbol at the front end of the slot A transferred from the N−1 stage of the previous stage._NAnd this channel estimate ξa_NAnd the channel estimation value ξb in the N-1 stage_N-1(The channel estimation value transferred between the channel estimation circuits 19) is used to process the slot A, and then the channel estimation value ξb by the pilot symbol at the front end of the slot B_NAnd the channel estimate ξb_NAnd the channel estimate ξ in the N-1 stage_cN-1Are used to process slot B.
[0043]
Therefore, in each stage, processing time for one slot is sufficient. Thus, the delay time in the 3 to 4 stage interference canceller is 3 to 4 slots long, which is about half the delay time of the conventional example. Note that channel estimation values based on pilot symbols before and after the slot are generally averaged when the channel fluctuation is small, and on the contrary, interpolation processing is performed when the channel fluctuation is large. Accuracy is improved.
[0044]
In the multi-stage type interference canceller, there is no previous stage in the first stage. Therefore, only the channel estimation value based on the pilot symbol at the front end of the slot is used to process the slot. Thus, an increase in delay time can be prevented.
[0045]
FIG. 5 is an error rate characteristic curve diagram of the first embodiment of the present invention, where the vertical axis indicates the error rate, the horizontal axis indicates the S / N, and the interference removal process is performed three times with a four-stage configuration. The simulation result of the error rate characteristic is shown. A solid line curve (a1) shows an error rate characteristic in the case of the first embodiment of the present invention, a dotted line curve (b1) shows an error rate characteristic of a conventional example, and a solid line curve (c1) shows no interference canceller. The error rate characteristics in the case of That is, according to the first embodiment of the present invention, the delay time is one slot per stage, and the delay time can be reduced to half compared to the conventional example, and the error rate characteristic is thereby degraded. As shown by the solid line curve (a1) and the dotted line curve (b1), it becomes negligible compared to the conventional example.
[0046]
FIG. 6 is a diagram for explaining the operation of the second embodiment of the present invention. This embodiment shows N-2 to N + 1 stages in a multi-stage interference canceller, and in the N-2 stage. For example, a case is shown in which the channel estimation time based on the pilot symbol at the rear end of the slot A and the channel estimation time based on the pilot symbol at the front end of the slot A in N stages are just equal.
[0047]
Therefore, the processing of the slot A in the N stage includes the channel estimation value ξa by the pilot symbol at the front end of the slot A in the N stage._nAnd the channel estimation value ξb by the pilot symbol at the rear end of the slot A in the N-2 stage that is two stages before the N stage._N-2Are used to process the first half of the slot A, and the channel estimation value ξb by the pilot symbol at the rear end of the slot A in the N−1 stage, which is one stage before the N stage._N-1And the channel estimation value ξa based on the pilot symbol at the front end of slot A in the N + 1 stage that is one stage after the N stage_{N + 1}Are used to process the second half of the slot A.
[0048]
The processing of the next slot B in the N stage is performed by the channel estimation value ξb by the pilot symbol at the front end of the slot B in the N stage._NAnd channel estimation value ξc by the pilot symbol at the rear end of slot B in the N-2 stage, which is the stage preceding the two stages_N-2Are used to process the first half of the slot B, and the channel estimation value ξc by the pilot symbol at the rear end of the slot B in the N−1 stage one stage before_N-1And the channel estimation value ξb by the pilot symbol at the front end of slot B in the N + 1 stage, one stage later_{N + 1}Are used to process the second half of the slot B. Similarly, in each stage, the first half and the second half of each slot are processed. The delay between stages is 1/2 slot length, and the delay time is 1/4 compared to the conventional example. Can do.
[0049]
FIG. 7 is a main part flowchart of the second embodiment of the present invention, showing the processing of slot A in the N-2, N-1, N, and N + 1 stages shown in FIG. Channel estimation value ξb by pilot symbol at rear end of slot A in stage_N-2From the channel estimation circuit 19 (see FIG. 2) of the N-2 stage interference canceller unit, each of the N-3 stage, the N-1 stage after the 1st stage, the N-1 stage after the 1st stage, and the N stage after the 2nd stage. Transfer to the channel estimation circuit of the interference canceller unit.
[0050]
Also, the channel estimated value ξa by the pilot symbol at the front end of slot A in the N-1 stage_N-1Are transferred to the channel estimation circuit of N-2 stage, 1 stage, 1 stage, N stage, and 2 stages, N + 1 stage. Also, the channel estimated value ξb by the pilot symbol at the rear end of slot A in the N-1 stage._N-1From the channel estimation circuit of the interference canceller unit of the N-1 stage, the channel estimation circuit of the interference canceller unit of each of the N-2 stage, the N stage that is the first stage, the N stage that is the second stage, and the N + 1 stage that is the second stage. Forward to.
[0051]
Thereby, for example, the first half of the slot A in the N stage is changed to the channel estimation value ξa._NAnd channel estimation value ξb from the N-2 stage, which is the preceding stage of the second stage_N-2And the second half of the slot A is the channel estimation value ξa from the N + 1 stage that is one stage later_{N + 1}And the estimated channel value ξb from the N-1 stage one stage before_N-1And processed using.
[0052]
In this case, the channel estimation values in the first half and the second half of the slot are different. However, since the accuracy of the channel estimation value on the rear stage side of the stage is improved, the channel estimation accuracy associated with the shortening of the delay time is improved. Degradation can be minimized.
[0053]
That is, in the error rate characteristic curve diagram shown in FIG. 8, the dotted curve (b2) and the solid curve (c2) represent the error rate characteristics in the case of the conventional example and the case without the interference canceller similar to the case shown in FIG. The solid curve (a2) shows the simulation result of the error rate characteristic of the second embodiment. As is apparent from a comparison between the solid line curve (a2) and the dotted line curve (b2), the error rate characteristic is little deteriorated, and the delay time between the stages can be shortened.
[0054]
Also, in this embodiment, channel estimates based on pilot symbols at the rear end of the slots cannot be used for all slots in the first stage and for the first half of the slots in the second stage. Only the channel estimation value based on the pilot symbol at the front end of the slot is used.
[0055]
FIG. 9 is a diagram for explaining the operation of the third embodiment of the present invention, and shows a case where the delay between each stage is set to one symbol length. For example, for slot A, the pilot at the front end in N stages Channel estimated value ξa by symbol_NIs used to process the first data symbol of the information symbol and the channel estimate ξa by the pilot symbol at the front end of slot A in the next N + 1 stage_{N + 1}Is used to process the second data symbol of the information symbol and the channel estimate ξa by the pilot symbol at the front end of slot A in the next N + 2 stage_{N + 2}Are used to sequentially process the third data symbol of the information symbol.
[0056]
Therefore, each data symbol of the information symbol is processed using the channel estimation value from the subsequent stage, and the delay between stages can be set to one symbol length. In this case, the information symbols of the slots are sequentially processed using the channel estimation value with high estimation accuracy in the subsequent stage, so that the processing delay can be shortened and the deterioration of the channel estimation accuracy can be suppressed. .
[0057]
FIG. 10 is a diagram for explaining the operation of the fourth embodiment of the present invention. Between the N-1 stage and the N stage, the delay between stages is set to one symbol length as in the embodiment shown in FIG. Between the N stage and the N + 1 stage, the case where the delay between stages is set to one slot length as in the embodiment shown in FIG.
[0058]
That is, in a multi-stage interference canceller, the cascaded stages are divided into the first half and the second half, and in the first half stage on the input side of the received signal, each data symbol of the information symbol is associated with the latter stage. Then, the data symbol of each slot is processed using the channel estimation value in each stage, and in the latter half stage, for example, in the N + 1 stage, the channel estimation value ξa by the pilot symbol at the front end of slot A_{N + 1}And the channel estimation value ξb by the pilot symbol at the rear end of the slot A in the N stage one stage before_NAre used to process the information symbols in slot A.
[0059]
According to this embodiment, the balance between the processing delay and the channel estimation accuracy can be freely adjusted by selecting the number of the first half and the number of the second half, and is also applicable to a fast fluctuation fading environment. It becomes possible. Also, when measuring with the smallest possible delay time as in SIR (signal power to interference power ratio) measurement for transmission power control, data processed by several stages with a delay time between stages of 1 symbol length is used. By using it, it is possible to obtain delayed data having a length of several symbols from which a certain amount of interference has been removed, so that a desired SIR can be measured with a small delay. In this case, interference can be removed by channel estimation with desired accuracy in the latter stage.
[0060]
FIG. 11 is a diagram for explaining the operation of the fifth embodiment of the present invention, and shows a case where the channel estimation accuracy is improved using information symbols. For example, when processing of slot B is performed in the N stage, Channel estimation value ηb using information symbol of slot A tentatively determined in N stages_NAnd the channel estimation value ξb by the pilot symbol at the front end of slot B_NAnd a channel estimation value ηc using the information symbol of slot B tentatively determined in the N−1 stage one stage before_N-1And a channel estimation value ξc by a pilot symbol at the rear end of the slot B_N-1And use.
[0061]
The processing of each slot in each stage similarly uses a channel estimation value using information symbols, and the delay between stages is one slot long, and the processing delay is halved compared to the conventional example. However, channel estimation accuracy can be improved.
[0062]
【The invention's effect】
As described above, the present invention transfers a channel estimation value at each stage to another stage in a multi-stage interference canceller using a channel estimation value based on pilot symbols added before and after the information symbol. The channel estimation value by the pilot symbol at the front end of the slot in a certain stage and the channel estimation value by the pilot symbol at the rear end of this slot in the preceding stage. Thus, in this stage, before the pilot symbol at the rear end of this slot is transferred, interference cancellation processing can be performed by channel estimation of this slot. In this case, the delay time between stages can be one slot length, and there is an advantage that the delay time can be reduced to half that of the conventional example.
[0063]
Further, the first half of the slot is processed using the channel estimation value based on the pilot symbol at the front end of the slot and the channel estimation value based on the pilot symbol at the rear end of the slot in the stage preceding the two stages. The delay time between stages is processed by processing the second half of the slot using the channel estimation value by the pilot symbol at the rear end of the slot and the channel estimation value by the pilot symbol at the front end of the slot in the stage after one stage. Can be shortened to 1/2 slot length.
[0064]
Also, by setting the delay time between each stage to one symbol length and transferring the channel estimation value at each stage to the preceding stage, it is possible to perform channel estimation processing for each information symbol. . In this case, the delay time can be greatly shortened, and a channel estimation value with high accuracy in the subsequent stage can be used, so that deterioration in channel estimation accuracy as a whole can be suppressed.
[0065]
Further, it is easy to configure so as to obtain a desired delay time and channel estimation accuracy by combining the above-described means, and a configuration that can easily cope with a fading environment or the like can be provided.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of an interference canceller unit according to the first embodiment of this invention.
FIG. 3 is an operation explanatory diagram of the first embodiment of the present invention.
FIG. 4 is a main part flowchart of the first embodiment of the present invention;
FIG. 5 is an error rate characteristic curve diagram of the first embodiment of the present invention.
FIG. 6 is an operation explanatory diagram of a second embodiment of the present invention.
FIG. 7 is a main part flowchart of the second embodiment of the present invention;
FIG. 8 is an error rate characteristic curve diagram of the second embodiment of the present invention.
FIG. 9 is an operation explanatory diagram of the third embodiment of the present invention.
FIG. 10 is an operation explanatory diagram of the fourth embodiment of the present invention.
FIG. 11 is an operation explanatory diagram of the fifth embodiment of the present invention.
FIG. 12 is an explanatory diagram of a conventional multi-stage interference canceller.
FIG. 13 is an explanatory diagram of a conventional interference canceller unit.
[Explanation of symbols]
1 (ICU_1,1~ ICU_{1, k}, ICU_2,1~ ICU_{2, k}Interference canceller unit
2 synthesis unit
3 Receiver (REC₁~ REC_k)
4 Delay circuit (DL)
d Interference replica
s symbol replica
ξ Channel estimate

Claims (9)

Included in the information symbol after receiving a received signal having a frame structure consisting of a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, demodulating the information symbol using a channel estimation value based on the pilot symbol In a multi-stage interference canceller in which stages including an interference canceller unit that eliminates interference are cascaded,
The interference canceller unit transfers a channel estimation value based on at least the pilot symbol in the channel estimation circuit of the interference canceller unit to a channel estimation circuit of an interference canceller unit of another stage, and the interference canceller of each stage The channel estimation circuit of the unit is configured to perform channel estimation of the slot by performing an averaging process or an interpolation process on the channel estimation value at the stage and the channel estimation value transferred from the other stage. An interference canceller characterized by comprising: The channel estimation value by the pilot symbol at the front end of the slot in the channel estimation circuit of the interference canceller unit is transferred to the channel estimation circuit of each interference canceller unit of the front stage and the rear stage, and the rear end of the slot 2. An interference canceller according to claim 1, wherein the channel estimation value based on the pilot symbol is transferred to the channel estimation circuit of each interference canceller unit of the preceding stage, the subsequent stage, and the subsequent stage. . The channel estimation value of the pilot symbol at the front end of the slot in the channel estimation circuit of the interference canceller unit is transferred to the channel estimation circuits of all the interference canceller units in the preceding stage. The interference canceller according to 1. Transfer channel estimation values based on pilot symbols at the front end of the slot in the channel estimation circuit of the interference canceller unit of each stage in the first half of the cascaded stages to the channel estimation circuits of all the interference canceller units in the previous stage The channel estimation value of at least the pilot symbol in the channel estimation circuit of the interference canceller unit in each of the latter half stages is transferred to the channel estimation circuit of the interference canceller unit in another stage. The interference canceller according to claim 1. An interference canceller that receives a reception signal having a frame structure including a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, and removes interference included in the information symbol using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage interference canceller in which stages including units are cascaded,
Using the channel estimation value based on the pilot symbol at the front end of the slot in the stage and the channel estimation value based on the pilot symbol at the rear end of the slot in the previous stage, the slot is subjected to averaging processing or interpolation processing. A channel estimation method comprising the step of performing channel estimation. An interference canceller that receives a reception signal having a frame structure including a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, and removes interference included in the information symbol using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage interference canceller in which stages including units are cascaded,
In the first half of the slot, the channel estimation value based on the pilot symbol at the front end of the slot in the stage and the channel estimation value based on the pilot symbol at the rear end of the slot in the stage preceding the two stages are used. Channel estimation is performed, and the channel estimation value based on the pilot symbol at the rear end of the slot in the previous stage and the channel estimation value based on the pilot symbol at the front end of the slot in the subsequent stage are used to determine the second half of the pilot. A channel estimation method comprising the step of performing channel estimation. An interference canceller that receives a reception signal having a frame structure including a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, and removes interference included in the information symbol using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage interference canceller in which stages including units are cascaded,
The channel estimation includes a step of performing channel estimation using a channel estimation value based on a pilot symbol at the front end of the slot in each subsequent stage in association with the symbol corresponding to the information symbol of the slot in the stage. Method. An interference canceller that receives a reception signal having a frame structure including a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, and removes interference included in the information symbol using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage interference canceller in which stages including units are cascaded,
Channel estimation values based on pilot symbols at the front end of the slot in the channel estimation circuit of the interference canceller unit of each stage in the first half of the cascaded stages are transmitted to the channel estimation circuits of all the interference canceller units in the previous stage. And performing channel estimation corresponding to the symbol corresponding to the information symbol of the slot, and at least the channel estimation value by the pilot symbol in the channel estimation circuit of the interference canceller unit in each stage of the latter half is used as interference of the other stage. The channel of the slot is transferred to the channel estimation circuit of the canceller unit by using the channel estimation value by the pilot symbol at the front end of the slot and the channel estimation value by the pilot symbol at the rear end of the slot in the previous stage. Make an estimate Channel estimation method which comprises the degree. An interference canceller that receives a reception signal having a frame structure including a plurality of slots to which pilot symbols are added before and after a fixed-length information symbol, and removes interference included in the information symbol using a channel estimation value based on the pilot symbol. In a channel estimation method in a multistage interference canceller in which stages including units are connected in cascade, channel estimation is performed using information symbols sandwiched between the pilot symbols and temporarily determined together with channel estimation using the pilot symbols. The channel estimation method according to any one of claims 5 to 8, further comprising:

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