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JP3664566B2 - Semiconductor device and manufacturing method thereof - Google Patents
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JP3664566B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP3664566B2
JP3664566B2 JP10008397A JP10008397A JP3664566B2 JP 3664566 B2 JP3664566 B2 JP 3664566B2 JP 10008397 A JP10008397 A JP 10008397A JP 10008397 A JP10008397 A JP 10008397A JP 3664566 B2 JP3664566 B2 JP 3664566B2
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Japan
Prior art keywords
lead
semiconductor element
semiconductor device
resin
chip support
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JP10008397A
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JPH10294416A (en
Inventor
伸仁 大内
博 河野
悦夫 山田
靖 白石
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP10008397A priority Critical patent/JP3664566B2/en
Priority to US08/848,286 priority patent/US5969410A/en
Priority to KR1019970017636A priority patent/KR100373891B1/en
Priority to EP03022551A priority patent/EP1381084A1/en
Priority to EP97107671A priority patent/EP0807972B1/en
Priority to DE69739619T priority patent/DE69739619D1/en
Publication of JPH10294416A publication Critical patent/JPH10294416A/en
Priority to US09/240,612 priority patent/US6258621B1/en
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Publication of JP3664566B2 publication Critical patent/JP3664566B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/865Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置、特に樹脂封止型半導体装置の構造およびその製造方法に関するものである。
【0002】
【従来の技術】
近年、樹脂封止型半導体装置は、ペレット(チップ)の大型化に伴い、パッケージ側端と半導体素子との間の寸法が一段と狭くなる傾向にある。これは、半導体素子が大きくなっているのに、これを収納するパッケージのサイズが規格化されているため、大きくできないことに起因する。このような課題を解決するために特公平6−105721号公報に開示されるようなLOC(Lead On Chip)構造とした樹脂封止型半導体装置が用いられるようになってきている。
【0003】
このLOC(Lead On Chip)構造の樹脂封止型半導体装置は、半導体素子の表面に絶縁テープを介してリードを接着するとともに、リードの上面に施された金線メッキと半導体素子の電極上の金球とを金線で接続し、さらにその外側を樹脂材で封止した構造になっている。
【0004】
【発明が解決しようとする課題】
しかしながら、このような従来の樹脂封止型半導体装置の大きな課題として、基板実装時の熱によって、例えば樹脂材にクラックが生じて機能を損ねることがある。原因は、空気中に保管されたときに水分が吸収されて湿気ったところに、基板実装時の熱で水分が蒸気化され、その力でクラックに至ると考えられる。特に、絶縁テープは水分を吸収し易く、絶縁テープの箇所からのクラックの発生が多い。また、他の課題として、絶縁テープがあるため、半導体装置の薄型化が制約される。
【0005】
本発明は、上記問題点に鑑みてなされたものであり、その目的はクラックの発生を抑えて、かつ薄型化が可能な樹脂封止型半導体装置およびその製造方法を提供することにある。
【0006】
【課題を解決するための手段】
本発明は上記目的を達成するために、次の技術手段を講じたことを特徴とする。すなわち、リードとは個別にチップサポートを設け、チップサポートのみを半導体素子に固着し、リードと半導体素子との間は固定せずに、半導体素子の電極とリードとを接続した構成とした。
【0007】
この構成では、リードと半導体素子表面の間に特に固定するための材料がないので、リードと半導体素子の組み合わせの厚みを薄くできる。これにより、全体の薄型化が可能になる。また、絶縁テープは半導体素子とチップサポートとの接着のみに用いられるため、使用される絶縁テープのテープ面積は極めて少ない。これにより、絶縁テープに起因するクラックの発生を抑えて品質を向上させることができる。
【0008】
【発明の実施の形態】
第1の実施形態
図1及び図2は本発明の第1の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、図1はリードの配置を示す図、図2はチップサポートの配置を示す図である。また、図3は第1の実施形態の樹脂封止型半導体装置の製造途中の状態を示す上面図である。
【0009】
半導体素子1の回路形成面上には、ポリイミドウエハコート9が設けられている。この半導体素子1は、リード3とチップサポート10とが形成された、厚みが約0.125ミリのリードフレーム12に搭載されている。チップサポート10と半導体素子1との間には、約0.15ミリの厚みを有した絶縁テープ2が介装されており、この絶縁テープ2によりチップサポート10とポリイミドウエハコート9とが接着固定されている。チップサポート10は、半導体素子1の端部外側(図2中に符号11で示す部分)で絶縁テープ2の略厚み分(約0.15ミリ)だけ曲げ加工されている。これに対し、リード3とポリイミドウエハコート9とは互いに接しているだけで固定されていない。チップサポート10の下面10a(曲げ加工部11外側における下面)と、ポリイミドウエハコート9表面とは、略同一平面上に配置されている。図3はこのようにしてリードフレーム12に半導体素子1を位置決めした状態を示している。
【0010】
次に、リード3の上面に施されている金線メッキ(図示しない)と半導体素子1上の金球5とを金線6で接続し、さらにこれらを樹脂材7で封止し、リード3およびチップサポート10をリードフレーム12より切り離すと、図1及び図2に示す樹脂封止型半導体装置が完成する。
【0011】
上記のように、第1の実施形態の樹脂封止型半導体装置の構造では、リード3と半導体素子1の表面であるポリイミドウエハコート9とは接しているのみであり、その間にこれらを固定するための材料が介在しないので、リード3と半導体素子1の組み合わせの厚みを薄くできる。これにより、全体の薄型化が可能になる。また、半導体素子1を固定するのは、チップサポート10に接着されている絶縁テープ2のみであるため、テープ面積は極めて少ない。これにより、絶縁テープ2の水分吸収が減り、基板実装時に生じる熱によるクラックの発生を抑えることができ、品質を向上させることができる。
【0012】
第2の実施形態
図4及び図5は本発明の第2の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、図4はリードの配置を示す図、図5はチップサポートの配置を示す図である。また、図6は第2の実施形態の樹脂封止型半導体装置の製造途中の状態を示す上面図である。なお、図4乃至図6において図1乃至図3と同一符号を付したものは図1乃至図3と同一のものを示している。
【0013】
半導体素子1の回路形成面上にはポリイミドウエハコート9が設けられている。この半導体素子1は、リード3とチップサポート10とが形成されたリードフレーム12に搭載されている。リード3とポリイミドウエハコート9とは、接しているだけで固定されていない。リード3は、半導体素子1の端部外側(図4中に符号21で示す部分)で下方(半導体素子1側)に曲げ加工されている。リード3の上面3a(曲げ加工部21外側における上面)と、ポリイミドウエハコート9表面とは、略同一平面上に配置されている。これに対して、チップサポート10は、ポリイミドウエハコート9表面に対し、上面10bが略同一平面上に配置され、かつ先端が半導体素子1の側端部との間に所定の隙間S(図5参照)を保って配置されている。さらにポリイミドウエハコート9の上面とチップサポート10の上面とにまたがって絶縁テープ2が貼り付けられ、この絶縁テープ2でポリイミドウエハコート9とチップサポート10が接着固定されている。図6はこのようにしてリードフレーム12に半導体素子1を位置決めした状態を示している。
【0014】
次に、リード3の上面に施されている金線メッキ(図示しない)と半導体素子1上の金球5とを金線6で接続し、さらにこれらを樹脂材7で封止し、リード3およびチップサポート10をリードフレーム12より切り離すと、図4及び図5に示す樹脂封止型半導体装置が完成する。
【0015】
上記のように、第2の実施形態の樹脂封止型半導体装置の構造では、リード3と半導体素子1の表面であるポリイミドウエハコート9とは接しているのみであり、その間にこれらを固定するための材料が介在しないので、リード3と半導体素子1の組み合わせの厚みを薄くできる。これにより、全体の薄型化が可能になる。また、半導体素子1を固定するのは、ポリイミドウエハコート9とチップサポート10とにまたがって設けられている絶縁テープ2のみであるため、テープ面積は極めて少ない。これにより、絶縁テープ2の水分吸収が減り、基板実装時に生じる熱によるクラックの発生を抑え、品質を向上させることができる。
【0016】
第3の実施形態
図7乃至図9は本発明の第3の実施形態の樹脂封止型半導体装置の構造を示す図である。図7は製造途中の状態を示す上面図である。図8及び図9は要部構造を示す縦断側面図であり、図8は図7に示すA−A’線で縦断した図、図9は図7に示すB−B’線で縦断した図である。なお、図7乃至図9において図1乃至図6と同一符号を付したものは図1乃至図6と同一のものを示している。
【0017】
半導体素子1の回路形成面上にはポリイミドウエハコート9が施されている。このポリイミドウエハコート9上には、絶縁テープ2によりチップサポート10が固着されている。このチップサポート10とリード3とは略同一平面内に形成されている。図8に示すように、チップサポート10は絶縁テープ2により半導体素子1表面に接着されている。また図9に示すように、リード3の上面に形成された金線メッキ4と、半導体素子1の電極(図示しない)上に設けられた金球5とは、金線6により接続されており、これによりリード3と半導体素子1の電極とが接続されている。リード3は半導体素子1に接着されておらず、離間して、すなわち間隙部31を介して、半導体素子1上に配置されており、この間隙部31はモールド樹脂7で充填されている。
【0018】
このようにリード3下部には絶縁テープ2が存在せず、絶縁テープ2の使用はチップサポート10部分のみとなっているため、絶縁テープ2の使用量を極めて少なくすることができ、水分の吸湿を抑制することができる。また、チップサポート10とリード3とは同一平面内に形成されているため、リードフレーム12における曲げ加工などの加工工程が削除できる。
【0019】
次に図7乃至図9に示した樹脂封止型半導体装置の製造方法を図10を用いて説明する。まず、リードフレーム12のチップサポート10が絶縁テープ2により接着された半導体素子1を、図10(a)に示すようにヒートブロック13内に配置する。このとき、リードフレーム12において、リード3とチップサポート10とは略同一面内に形成されており、リード3はチップサポート10と半導体素子1とを固定する絶縁テープ2の厚み分だけ半導体素子1から離れて空中に浮いている。
【0020】
次に図10(b)に示すように、リード3の上面に配置されたリードクランパ14およびヒートブロック13によりリード3および半導体素子1を挟み込むことにより、リード3を半導体素子1に接触させる。その後、リード3の金メッキ4と半導体素子1上の金球5とをワイヤボンディングにより金線6で接続する。その後、固定したリードクランパ14を開放することによりリード3は図10(a)に示す位置に戻り、この状態でこれら半導体素子1、リード3、金線6とチップサポート10とを樹脂材7(図8、図9参照)にて封止する。このように製造することにより、リード3あるいはチップサポート10を曲げ加工することなく、チップサポート10のみを半導体素子1に固定した樹脂封止型半導体装置(図7乃至図9参照)を得ることができる。
【0021】
第4の実施形態
図11は本発明の第4の実施形態の樹脂封止型半導体装置の要部構造を示す縦断面図である。また図12は図11に示した樹脂封止型半導体装置の製造方法を説明する図である。なお、図11及び図12において図1乃至図10と同一符号を付したものは図1乃至図10と同一のものを示している。
【0022】
この第4の実施形態の樹脂封止型半導体装置は、概して上記第3の実施形態の樹脂封止型半導体装置と同じあるが、以下の点で異なる。すなわち、図11に示す樹脂封止型半導体装置のリード3の先端部15には曲げ加工が施されており、先端部15は半導体素子1表面に対して上方に曲がっている。これにより、製造工程において図12に示すようにリードクランパ14とヒートブロック13でリード3および半導体素子1を挟み込んだ際に、リード3の先端角部が直接半導体素子1上のポリイミドウエハコート9に触れることはなく、リード3の曲げ加工された先端部15の下面がポリイミドウエハコート9に接する。このため、リード3による半導体素子1の表面の傷の発生を防止することができる。
【0023】
第5の実施形態
図13は本発明の第5の実施形態の樹脂封止型半導体装置の製造方法を説明する図である。なお、図13において図1乃至図12と同一符号を付したものは図1乃至図12と同一のものを示している。この第5の実施形態の樹脂封止型半導体装置の構造は、図7乃至図9に示した上記第3の実施形態の樹脂封止型半導体装置と同じであるものとする。
【0024】
この第5の実施形態の樹脂封止型半導体装置の製造工程においては、電磁石を内蔵したリードクランパ16を用いて、リード3を半導体素子1表面に接触させずにリード3の金線メッキ4と半導体素子1の金球5とを接続する。図13において、まず、チップサポート10が絶縁テープ2により固着された半導体素子1を、ヒートブロック13に配置する。このときリード3はチップサポート10と半導体素子1とを接着する絶縁テープ2の厚さ分だけ半導体素子1から空中に浮いている。
【0025】
次に、リード3の上面に電磁石内蔵リードクランパ16を配置し、電磁石内蔵リードクランパ16の磁力により、リード3を電磁石内蔵リードクランパ16の下面に固定し、この状態でリード3と半導体素子1の金球5とを金線6によりワイヤボンディングする。このようにして金球5とリード3とを接続することにより、半導体素子1表面の傷、リード3の変形を防ぐことができる。
【0026】
尚、第5の実施形態の製造方法を図11に示した上記第4の実施形態の樹脂封止型半導体装置に適用することも可能である。
【0027】
第6の実施の形態
図14は本発明の第6の実施形態の樹脂封止型半導体装置の製造方法を説明する図である。なお、図14において図1乃至図13と同一符号を付したものは図1乃至図13と同一のものを示している。この第6の実施形態の樹脂封止型半導体装置の構造は、図7乃至図9に示した上記第3の実施形態の樹脂封止型半導体装置と同じであるものとする。
【0028】
この第6の実施形態の樹脂封止型半導体装置の製造工程においては、電磁石を内蔵したヒートブロック17を用いて、リード3を半導体素子1表面に接触させる。図14において、まず、チップサポート10を絶縁テープ2により固着した半導体素子1を、電磁石内蔵ヒートブロック17内に配置する。次に電磁石内蔵ヒートブロック17を作動させ、この磁力によりリード3を半導体素子1の表面に引き寄せて接触させ、この状態で金球5とリード3とを金線6により接続する。このようにして金球5とリード3とを接続することにより、リードクランパを用いずにリード3を安定して固定することができる。
【0029】
尚、第6の実施形態の製造方法を図11に示した上記第4の実施形態の樹脂封止型半導体装置に適用することも可能である。
【0030】
【発明の効果】
以上説明したとおり、本発明の半導体装置および製造方法によれば、半導体装置全体の薄型化が可能になるとともに、接着用の絶縁テープに起因するクラックの発生を抑えて品質を向上させることができるという効果がある。
【図面の簡単な説明】
【図1】本発明の第1の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、リードの配置を示す図である。
【図2】本発明の第1の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、チップサポートの配置を示す図である。
【図3】本発明の第1の実施形態の樹脂封止型半導体装置の製造途中の状態を示す上面図である。
【図4】本発明の第2の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、リードの配置を示す図である。
【図5】本発明の第2の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、チップサポートの配置を示す図である。
【図6】本発明の第2の実施形態の樹脂封止型半導体装置の製造途中の状態を示す上面図である。
【図7】本発明の第3の実施形態の樹脂封止型半導体装置の製造途中の状態を示す上面図である。
【図8】本発明の第3の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、図7のA−A’線で縦断した図である。
【図9】本発明の第3の実施形態の樹脂封止型半導体装置の要部構造を示す縦断側面図であり、図7のB−B’線で縦断した図である。
【図10】本発明の第3の実施形態の樹脂封止型半導体装置の製造工程を説明する図である。
【図11】本発明の第4の実施形態の樹脂封止型半導体装置の要部構造を示す縦断面図である。
【図12】本発明の第4の実施形態の樹脂封止型半導体装置の製造工程を説明する図である。
【図13】本発明の第5の実施形態の樹脂封止型半導体装置の製造工程を説明する図である。
【図14】本発明の第6の実施形態の樹脂封止型半導体装置の製造工程を説明する図である。
【符号の説明】
1 半導体素子、2 絶縁テープ、3 リード、10 チップサポート、11チップサポート曲げ加工部、12 リードフレーム、13 ヒートブロック、14 リードクランパ、15 リード先端部、16 電磁石内蔵リードクランパ、17 電磁石内蔵ヒートブロック、21 リード曲げ加工部
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a semiconductor device, particularly a resin-encapsulated semiconductor device, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, with the increase in size of pellets (chips) in resin-encapsulated semiconductor devices, the dimension between the package side end and the semiconductor element tends to be further narrowed. This is due to the fact that although the size of the semiconductor element is large, the size of the package that accommodates the semiconductor element cannot be increased because it is standardized. In order to solve such a problem, a resin-encapsulated semiconductor device having a LOC (Lead On Chip) structure as disclosed in Japanese Patent Publication No. 6-105721 has been used.
[0003]
In this resin-encapsulated semiconductor device having a LOC (Lead On Chip) structure, a lead is bonded to the surface of a semiconductor element via an insulating tape, and gold wire plating applied to the upper surface of the lead and on the electrode of the semiconductor element It has a structure in which a gold ball is connected with a gold wire and the outside is sealed with a resin material.
[0004]
[Problems to be solved by the invention]
However, a major problem with such a conventional resin-encapsulated semiconductor device is that, for example, a resin material is cracked by heat at the time of substrate mounting, and the function is impaired. The cause is considered to be that moisture is vaporized by heat at the time of substrate mounting where moisture is absorbed when stored in the air, and cracks are caused by the force. In particular, the insulating tape easily absorbs moisture, and many cracks are generated from the portion of the insulating tape. In addition, as another problem, since there is an insulating tape, a reduction in the thickness of the semiconductor device is restricted.
[0005]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a resin-encapsulated semiconductor device that can suppress the generation of cracks and can be thinned, and a method for manufacturing the same.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is characterized by taking the following technical means. That is, a chip support is provided separately from the lead, and only the chip support is fixed to the semiconductor element, and the electrode of the semiconductor element and the lead are connected without fixing between the lead and the semiconductor element.
[0007]
In this configuration, since there is no material for fixing between the lead and the surface of the semiconductor element, the thickness of the combination of the lead and the semiconductor element can be reduced. Thereby, the whole thickness can be reduced. Moreover, since the insulating tape is used only for bonding the semiconductor element and the chip support, the tape area of the insulating tape used is extremely small. Thereby, generation | occurrence | production of the crack resulting from an insulating tape can be suppressed, and quality can be improved.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment FIGS. 1 and 2 are longitudinal side views showing the main structure of a resin-encapsulated semiconductor device according to a first embodiment of the present invention. FIG. 1 is a diagram showing the arrangement of leads, FIG. FIG. 4 is a diagram showing an arrangement of chip supports. FIG. 3 is a top view showing a state in the middle of manufacturing the resin-encapsulated semiconductor device of the first embodiment.
[0009]
A polyimide wafer coat 9 is provided on the circuit formation surface of the semiconductor element 1. The semiconductor element 1 is mounted on a lead frame 12 having a thickness of about 0.125 mm, in which leads 3 and a chip support 10 are formed. An insulating tape 2 having a thickness of about 0.15 mm is interposed between the chip support 10 and the semiconductor element 1, and the chip support 10 and the polyimide wafer coat 9 are bonded and fixed by the insulating tape 2. Has been. The chip support 10 is bent by the approximate thickness (about 0.15 mm) of the insulating tape 2 outside the end of the semiconductor element 1 (the portion indicated by reference numeral 11 in FIG. 2). On the other hand, the lead 3 and the polyimide wafer coat 9 are in contact with each other and are not fixed. The lower surface 10a of the chip support 10 (the lower surface outside the bent portion 11) and the surface of the polyimide wafer coat 9 are arranged on substantially the same plane. FIG. 3 shows a state in which the semiconductor element 1 is positioned on the lead frame 12 in this way.
[0010]
Next, gold wire plating (not shown) applied to the upper surface of the lead 3 and the gold ball 5 on the semiconductor element 1 are connected by a gold wire 6, and these are sealed with a resin material 7. When the chip support 10 is separated from the lead frame 12, the resin-encapsulated semiconductor device shown in FIGS. 1 and 2 is completed.
[0011]
As described above, in the structure of the resin-encapsulated semiconductor device according to the first embodiment, the lead 3 and the polyimide wafer coat 9 which is the surface of the semiconductor element 1 are only in contact with each other, and these are fixed therebetween. Therefore, the thickness of the combination of the lead 3 and the semiconductor element 1 can be reduced. Thereby, the whole thickness can be reduced. Further, since the semiconductor element 1 is fixed only by the insulating tape 2 bonded to the chip support 10, the tape area is extremely small. As a result, moisture absorption of the insulating tape 2 is reduced, generation of cracks due to heat generated during substrate mounting can be suppressed, and quality can be improved.
[0012]
Second Embodiment FIGS. 4 and 5 are longitudinal sectional side views showing the main structure of a resin-encapsulated semiconductor device according to a second embodiment of the present invention. FIG. 4 is a diagram showing the arrangement of leads. FIG. 4 is a diagram showing an arrangement of chip supports. FIG. 6 is a top view showing a state in the middle of manufacturing the resin-encapsulated semiconductor device of the second embodiment. 4 to 6, the same reference numerals as those in FIGS. 1 to 3 denote the same components as those in FIGS.
[0013]
A polyimide wafer coat 9 is provided on the circuit formation surface of the semiconductor element 1. The semiconductor element 1 is mounted on a lead frame 12 in which leads 3 and a chip support 10 are formed. The lead 3 and the polyimide wafer coat 9 are in contact but not fixed. The lead 3 is bent downward (on the semiconductor element 1 side) outside the end of the semiconductor element 1 (the part indicated by reference numeral 21 in FIG. 4). The upper surface 3a of the lead 3 (the upper surface outside the bent portion 21) and the surface of the polyimide wafer coat 9 are arranged on substantially the same plane. On the other hand, the chip support 10 has an upper surface 10b disposed on the substantially same plane with respect to the surface of the polyimide wafer coat 9, and a predetermined gap S between the tip and the side end of the semiconductor element 1 (FIG. 5). (See below). Further, the insulating tape 2 is applied across the upper surface of the polyimide wafer coat 9 and the upper surface of the chip support 10, and the polyimide wafer coat 9 and the chip support 10 are bonded and fixed by the insulating tape 2. FIG. 6 shows a state in which the semiconductor element 1 is positioned on the lead frame 12 in this way.
[0014]
Next, gold wire plating (not shown) applied to the upper surface of the lead 3 and the gold ball 5 on the semiconductor element 1 are connected by a gold wire 6, and these are sealed with a resin material 7. When the chip support 10 is separated from the lead frame 12, the resin-encapsulated semiconductor device shown in FIGS. 4 and 5 is completed.
[0015]
As described above, in the structure of the resin-encapsulated semiconductor device according to the second embodiment, the lead 3 and the polyimide wafer coat 9 which is the surface of the semiconductor element 1 are only in contact with each other, and these are fixed therebetween. Therefore, the thickness of the combination of the lead 3 and the semiconductor element 1 can be reduced. Thereby, the whole thickness can be reduced. Further, since the semiconductor element 1 is fixed only by the insulating tape 2 provided across the polyimide wafer coat 9 and the chip support 10, the tape area is extremely small. Thereby, the moisture absorption of the insulating tape 2 is reduced, the generation of cracks due to heat generated during mounting on the substrate can be suppressed, and the quality can be improved.
[0016]
Third Embodiment FIGS. 7 to 9 are views showing the structure of a resin-encapsulated semiconductor device according to a third embodiment of the present invention. FIG. 7 is a top view showing a state during manufacture. 8 and 9 are longitudinal side views showing the main structure, FIG. 8 is a longitudinal sectional view taken along line AA ′ shown in FIG. 7, and FIG. 9 is a longitudinal sectional view taken along line BB ′ shown in FIG. It is. 7 to 9, the same reference numerals as those in FIGS. 1 to 6 denote the same components as those in FIGS.
[0017]
A polyimide wafer coat 9 is applied on the circuit forming surface of the semiconductor element 1. A chip support 10 is fixed on the polyimide wafer coat 9 by an insulating tape 2. The chip support 10 and the lead 3 are formed in substantially the same plane. As shown in FIG. 8, the chip support 10 is bonded to the surface of the semiconductor element 1 by the insulating tape 2. As shown in FIG. 9, the gold wire plating 4 formed on the upper surface of the lead 3 and the gold ball 5 provided on the electrode (not shown) of the semiconductor element 1 are connected by a gold wire 6. Thereby, the lead 3 and the electrode of the semiconductor element 1 are connected. The leads 3 are not bonded to the semiconductor element 1 but are spaced apart, that is, disposed on the semiconductor element 1 via the gap 31, and the gap 31 is filled with the mold resin 7.
[0018]
Thus, the insulating tape 2 does not exist at the lower part of the lead 3 and the insulating tape 2 is used only for the chip support 10 portion. Therefore, the usage amount of the insulating tape 2 can be extremely reduced, and moisture is absorbed. Can be suppressed. Further, since the chip support 10 and the lead 3 are formed in the same plane, a processing step such as bending in the lead frame 12 can be eliminated.
[0019]
Next, a method for manufacturing the resin-encapsulated semiconductor device shown in FIGS. 7 to 9 will be described with reference to FIGS. First, the semiconductor element 1 to which the chip support 10 of the lead frame 12 is bonded by the insulating tape 2 is disposed in the heat block 13 as shown in FIG. At this time, in the lead frame 12, the lead 3 and the chip support 10 are formed in substantially the same plane, and the lead 3 corresponds to the thickness of the insulating tape 2 that fixes the chip support 10 and the semiconductor element 1. Floating away from the air.
[0020]
Next, as shown in FIG. 10B, the lead 3 and the semiconductor element 1 are sandwiched between the lead clamper 14 and the heat block 13 disposed on the upper surface of the lead 3, thereby bringing the lead 3 into contact with the semiconductor element 1. Thereafter, the gold plating 4 of the lead 3 and the gold ball 5 on the semiconductor element 1 are connected by a gold wire 6 by wire bonding. Thereafter, by releasing the fixed lead clamper 14, the lead 3 returns to the position shown in FIG. 10A. In this state, the semiconductor element 1, the lead 3, the gold wire 6 and the chip support 10 are connected to the resin material 7 ( Sealing is performed with reference to FIGS. By manufacturing in this way, it is possible to obtain a resin-encapsulated semiconductor device (see FIGS. 7 to 9) in which only the chip support 10 is fixed to the semiconductor element 1 without bending the lead 3 or the chip support 10. it can.
[0021]
Fourth Embodiment FIG. 11 is a longitudinal sectional view showing the main structure of a resin-encapsulated semiconductor device according to a fourth embodiment of the present invention. FIG. 12 is a view for explaining a method of manufacturing the resin-encapsulated semiconductor device shown in FIG. 11 and 12, the same reference numerals as those in FIGS. 1 to 10 denote the same components as those in FIGS.
[0022]
The resin-encapsulated semiconductor device of the fourth embodiment is generally the same as the resin-encapsulated semiconductor device of the third embodiment, but differs in the following points. That is, the tip 15 of the lead 3 of the resin-encapsulated semiconductor device shown in FIG. 11 is bent, and the tip 15 is bent upward with respect to the surface of the semiconductor element 1. As a result, when the lead 3 and the semiconductor element 1 are sandwiched between the lead clamper 14 and the heat block 13 as shown in FIG. 12 in the manufacturing process, the tip corner portion of the lead 3 directly contacts the polyimide wafer coat 9 on the semiconductor element 1. The lower surface of the bent tip portion 15 of the lead 3 is in contact with the polyimide wafer coat 9 without being touched. For this reason, generation | occurrence | production of the damage | wound of the surface of the semiconductor element 1 by the lead | read | reed 3 can be prevented.
[0023]
Fifth Embodiment FIG. 13 is a diagram for explaining a method for manufacturing a resin-encapsulated semiconductor device according to a fifth embodiment of the present invention. In FIG. 13, the same reference numerals as those in FIGS. 1 to 12 denote the same components as those in FIGS. The structure of the resin-encapsulated semiconductor device of the fifth embodiment is the same as that of the resin-encapsulated semiconductor device of the third embodiment shown in FIGS.
[0024]
In the manufacturing process of the resin-encapsulated semiconductor device according to the fifth embodiment, the lead clamper 16 with a built-in electromagnet is used to connect the lead 3 to the gold wire plating 4 without contacting the surface of the semiconductor element 1. The gold ball 5 of the semiconductor element 1 is connected. In FIG. 13, first, the semiconductor element 1 to which the chip support 10 is fixed by the insulating tape 2 is placed on the heat block 13. At this time, the lead 3 floats in the air from the semiconductor element 1 by the thickness of the insulating tape 2 that bonds the chip support 10 and the semiconductor element 1.
[0025]
Next, the lead clamper 16 with a built-in electromagnet is disposed on the top surface of the lead 3, and the lead 3 is fixed to the bottom surface of the lead clamper 16 with a built-in electromagnet by the magnetic force of the lead clamper 16 with a built-in electromagnet. The gold ball 5 is wire-bonded with the gold wire 6. By connecting the gold ball 5 and the lead 3 in this manner, scratches on the surface of the semiconductor element 1 and deformation of the lead 3 can be prevented.
[0026]
The manufacturing method of the fifth embodiment can also be applied to the resin-encapsulated semiconductor device of the fourth embodiment shown in FIG.
[0027]
Sixth Embodiment FIG. 14 is a view for explaining a method for manufacturing a resin-encapsulated semiconductor device according to a sixth embodiment of the present invention. In FIG. 14, the same reference numerals as those in FIGS. 1 to 13 denote the same components as those in FIGS. The structure of the resin-encapsulated semiconductor device of the sixth embodiment is the same as that of the resin-encapsulated semiconductor device of the third embodiment shown in FIGS.
[0028]
In the manufacturing process of the resin-encapsulated semiconductor device according to the sixth embodiment, the lead 3 is brought into contact with the surface of the semiconductor element 1 using the heat block 17 incorporating the electromagnet. In FIG. 14, first, the semiconductor element 1 to which the chip support 10 is fixed by the insulating tape 2 is arranged in the electromagnet built-in heat block 17. Next, the electromagnet built-in heat block 17 is operated, and the lead 3 is brought close to and brought into contact with the surface of the semiconductor element 1 by this magnetic force. In this state, the gold ball 5 and the lead 3 are connected by the gold wire 6. By connecting the gold ball 5 and the lead 3 in this way, the lead 3 can be stably fixed without using a lead clamper.
[0029]
The manufacturing method of the sixth embodiment can be applied to the resin-encapsulated semiconductor device of the fourth embodiment shown in FIG.
[0030]
【The invention's effect】
As described above, according to the semiconductor device and the manufacturing method of the present invention, the entire semiconductor device can be thinned, and the quality can be improved by suppressing the occurrence of cracks due to the insulating tape for bonding. There is an effect.
[Brief description of the drawings]
FIG. 1 is a longitudinal side view showing a main part structure of a resin-encapsulated semiconductor device according to a first embodiment of the present invention, and is a view showing an arrangement of leads.
FIG. 2 is a longitudinal side view showing the main structure of the resin-encapsulated semiconductor device according to the first embodiment of the present invention, and is a diagram showing the arrangement of chip supports.
FIG. 3 is a top view showing a state in the middle of manufacturing the resin-encapsulated semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a longitudinal side view showing a main structure of a resin-encapsulated semiconductor device according to a second embodiment of the present invention, and is a diagram showing the arrangement of leads.
FIG. 5 is a longitudinal side view showing a main part structure of a resin-encapsulated semiconductor device according to a second embodiment of the present invention, and is a diagram showing an arrangement of chip supports.
FIG. 6 is a top view showing a state in the middle of manufacturing of the resin-encapsulated semiconductor device according to the second embodiment of the present invention.
FIG. 7 is a top view showing a state in the middle of manufacturing a resin-encapsulated semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a longitudinal side view showing a main part structure of a resin-encapsulated semiconductor device according to a third embodiment of the present invention, which is a longitudinal sectional view taken along line AA ′ in FIG. 7;
FIG. 9 is a longitudinal side view showing a main part structure of a resin-encapsulated semiconductor device according to a third embodiment of the present invention, which is a longitudinal sectional view taken along line BB ′ of FIG. 7;
FIG. 10 is a diagram illustrating a manufacturing process of a resin-encapsulated semiconductor device according to a third embodiment of the present invention.
FIG. 11 is a longitudinal sectional view showing the main structure of a resin-encapsulated semiconductor device according to a fourth embodiment of the present invention.
FIG. 12 is a diagram illustrating a manufacturing process of a resin-encapsulated semiconductor device according to a fourth embodiment of the present invention.
FIG. 13 is a diagram illustrating a manufacturing process of a resin-encapsulated semiconductor device according to a fifth embodiment of the present invention.
FIG. 14 is a diagram illustrating a manufacturing process of a resin-encapsulated semiconductor device according to a sixth embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 Insulating tape, 3 Lead, 10 Chip support, 11 Chip support bending process part, 12 Lead frame, 13 Heat block, 14 Lead clamper, 15 Lead tip part, 16 Electromagnet built-in lead clamper, 17 Electromagnet built-in heat block , 21 Lead bending section

Claims (5)

表面に電極を有する半導体素子と、
前記半導体素子表面から離間して配置されたリードと、
前記半導体素子表面に固着されたチップサポートと、
前記電極と前記リードとを接続するワイヤと
を備え、
前記リードは、前記ワイヤが接続される側の端部が前記半導体素子の前記表面から遠のくように曲げられている
ことを特徴とする半導体装置。
A semiconductor element having an electrode on the surface;
Leads arranged spaced from the surface of the semiconductor element;
A chip support fixed to the surface of the semiconductor element;
A wire connecting the electrode and the lead,
The lead is bent so that an end on a side to which the wire is connected is far from the surface of the semiconductor element.
表面に電極が形成された半導体素子と、チップサポートおよびリードが略同一平面内に形成されたリードフレームとを準備する工程と、
前記半導体素子表面に前記チップサポートを固着すると共に、前記リードを前記半導体素子表面の上方に離間して配置する工程と、
前記リードを前記半導体素子表面に接触させた状態で、このリードと前記電極とを接続する工程と
を含み
前記リードを前記半導体素子表面の上方に配置する前記工程において、前記リードの端部は、前記半導体素子表面から遠のくように曲げられている
ことを特徴とする半導体装置の製造方法。
Preparing a semiconductor element having an electrode formed on a surface thereof, and a lead frame in which chip supports and leads are formed in substantially the same plane;
Fixing the chip support to the surface of the semiconductor element and disposing the leads above the surface of the semiconductor element; and
Connecting the lead and the electrode with the lead in contact with the surface of the semiconductor element ,
In the step of arranging the lead above the surface of the semiconductor element, an end portion of the lead is bent away from the surface of the semiconductor element .
前記リードと電極とを接続する工程は、前記半導体素子と前記リードとを、前記半導体素子の裏面に配置されたヒートブロックおよび前記リードの上面に配置されたリードクランパにより挟み込むことにより接触させることを含むことを特徴とする請求項2記載の半導体装置の製造方法。  The step of connecting the lead and the electrode includes bringing the semiconductor element and the lead into contact with each other by being sandwiched between a heat block disposed on the back surface of the semiconductor element and a lead clamper disposed on the top surface of the lead. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: 前記リードと電極とを接続する工程は、前記半導体素子の裏面に配置された、電磁石を内蔵したヒートブロックにより、前記リードを前記半導体素子に接触させることを含むことを特徴とする請求項2記載の半導体装置の製造方法。  3. The step of connecting the lead and the electrode includes bringing the lead into contact with the semiconductor element by a heat block having a built-in electromagnet disposed on the back surface of the semiconductor element. Manufacturing method of the semiconductor device. 表面に電極が形成された半導体素子と、チップサポートおよびリードが略同一平面に形成されたリードフレームとを準備する工程と、
前記半導体素子表面に前記チップサポートを固着すると共に、前記リードを前記半導体素子表面の上方に離間して配置する工程と、
前記リードの上面に、電磁石を内蔵したリードクランパを配置し、このリードと前記電極とを接続する工程と
を含み、
前記リードを前記半導体素子表面の上方に配置する前記工程において、前記リードの端部は、前記半導体素子表面から遠のくように曲げられている
ことを特徴とする半導体装置の製造方法。
Preparing a semiconductor element having an electrode formed on a surface thereof, and a lead frame in which chip supports and leads are formed in substantially the same plane;
Fixing the chip support to the surface of the semiconductor element and disposing the leads above the surface of the semiconductor element; and
The upper surface of the lead, placing the Ridokuranpa with a built-in electromagnet, viewed including the step of connecting the with the lead electrodes,
In the step of arranging the lead above the surface of the semiconductor element, an end portion of the lead is bent away from the surface of the semiconductor element .
JP10008397A 1996-05-09 1997-04-17 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3664566B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP10008397A JP3664566B2 (en) 1997-04-17 1997-04-17 Semiconductor device and manufacturing method thereof
US08/848,286 US5969410A (en) 1996-05-09 1997-04-29 Semiconductor IC device having chip support element and electrodes on the same surface
KR1019970017636A KR100373891B1 (en) 1996-05-09 1997-05-08 Semiconductor device and method of its fabrication
EP97107671A EP0807972B1 (en) 1996-05-09 1997-05-09 Semiconductor device and method of its fabrication
EP03022551A EP1381084A1 (en) 1996-05-09 1997-05-09 Semiconductor device and method of its fabrication
DE69739619T DE69739619D1 (en) 1996-05-09 1997-05-09 Semiconductor arrangement and manufacturing method
US09/240,612 US6258621B1 (en) 1996-05-09 1999-02-01 Method of fabricating a semiconductor device having insulating tape interposed between chip and chip support

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