JP3665183B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having memory cells, and more particularly to a semiconductor device having dynamic random access memory (hereinafter abbreviated as DRAM) cells and a method for manufacturing the same.
[0002]
[Prior art]
In a conventional semiconductor integrated circuit device having a DRAM cell as an information storage unit and an information processing unit in addition, the following consideration is made. That is, it answers the request for ensuring the withstand voltage and reliability in the information storage unit and the request for ensuring the high speed of information processing in the information processing unit. The following are some attempts.
[0003]
First, there is an example in which the thicknesses of the gate oxide films of the MOS transistors in both portions are different. For example, it can be found in Japanese Patent Publication No. 3-220766 (Article 1). In this example, the gate oxide film of the MOS transistor of the information storage unit is used as an information processing unit so that the reliability of the gate oxide film under word line boosting can be ensured and high-speed information reading / writing can be performed. This is thicker than the gate oxide film of the MOS transistor. Similarly, in JP-A-4-165670, JP-A-5-102415, and JP-A-6-342891, JP-A-7-297298, the gate insulating film in the memory cell region is formed thicker than the gate insulating film in the peripheral circuit region. There is a structure disclosure.
[0004]
In addition, in the example shown in Japanese Published Patent Publication No. 56-120166 (Article 2) for the same type of semiconductor integrated circuit as described above, the threshold voltage is set independently in the information storage unit and the information processing unit. Yes. In order to realize this, two types of gate oxide films are used. That is, the impurity concentration of the semiconductor substrate under the thick gate oxide film is set lower than that under the thin gate oxide film.
[0005]
In Japanese Patent Laid-Open Publication No. 61-194770 (Article 3), a device for ensuring the reliability of the gate oxide film of a MOS transistor driven at high voltage is devised. That is, the MOS transistor of the input / output circuit section and the gate oxide film of the MOS transistor that requires a high threshold voltage of the memory cell section are replaced with the low threshold voltage of the MOS transistor of the internal circuit section and the memory cell section. This is thicker than the gate oxide film of the MOS type transistor that requires the transistor.
[0006]
On the other hand, the thickness of each gate oxide film is devised also in a semiconductor integrated circuit having a flash memory cell as an information storage unit and an information processing unit in addition. For example, an example can be seen in Japanese Published Patent Publication, JP-A-8-8350 (Article 4). In order to reduce the leakage current between the floating gate electrode and the drain diffusion layer, the gate oxide film on the drain diffusion layer is thickened. Even if such a method of increasing the thickness of the gate oxide film on the drain diffusion layer is applied to a semiconductor integrated circuit including a DRAM, the electric field at the junction end at the gate electrode end of the MOS transistor of the information storage section does not change. . That is, since the thickness of the gate oxide film, which is the distance from the end of the high concentration drain diffusion layer to the gate electrode, does not change at all, the electric field at the junction end does not change. Thus, article 4 does not consider the influence of the electric field at the junction end in the DRAM.
[0007]
In addition, in the semiconductor integrated circuit having a DRAM cell as an information storage unit and an information processing unit in addition, a device for impurity concentration of the semiconductor substrate is also seen. For example, Japanese Patent Publication No. JP-A-3-204969 (Article 5). The diffusion layer in contact with the charge storage electrode of the MOS transistor of the information storage unit is composed of only the low concentration layer of the diffusion layer in contact with the charge storage electrode, and the concentration is the source / drain diffusion layer of the MOS transistor of the information processing unit It was almost the same as the low concentration layer. This is to prevent an increase in leakage current affected by defects due to high concentration ion implantation when forming this layer.
[0008]
Further, in a semiconductor integrated circuit having a DRAM cell as an information storage unit and an information processing unit in addition, another device for improving the refresh characteristics of the DRAM can be seen. For example, Japanese Patent Laid-Open Publication No. 6-61486 (Article 6). That is, the same conductive type low concentration layer as that of the diffusion layer is formed under the high concentration layer of the diffusion layer only in the connection hole portion to the storage electrode in plan view. Then, the impurity concentration of the low concentration layer is set so as to be completely depleted when the reverse voltage applied to the pn junction composed of the high concentration diffusion layer and the substrate is large. However, the influence of the electric field at the junction end in DRAM is not considered.
[0009]
On the other hand, the element separation by the groove can be found in Japanese Patent Laid-Open Publication No. 5-44934 (Article 7). In other words, in order to realize a fine element isolation region, element isolation is performed in a trench in which an insulator is embedded.
[0010]
A method of manufacturing a MOS transistor by changing the thickness of the gate oxide film between the information storage unit and the information processing unit can be found in, for example, Japanese Patent Application No. 62-275815 (Article 8). It takes the following method. First, a thin gate oxide film necessary for the information storage unit is formed, and a silicon film to be a floating gate electrode of the information storage unit is deposited. Thereafter, the floating gate electrode silicon film is processed into a desired shape, and an insulating film serving as an interlayer insulating film is deposited between the floating gate electrode silicon film and the control gate electrode silicon film. Thereafter, the interlayer insulating film of the information processing unit is removed, and a thick gate oxide film necessary for the information processing unit is formed. In addition, in a MOSFET using an element isolation trench, a thick gate insulation film is formed at the edge of the element isolation trench to prevent electric field concentration and gate breakdown voltage degradation due to the thin gate insulation film at the edge of the isolation trench and the element formation region. Such structures are disclosed in JP-A-5-47919, JP-A-10-223747, and JP-A-10-254638. Further, in a MOSFET using an element isolation groove, a structure for increasing the breakdown voltage by forming the gate insulating film at the edge of the element isolation groove at the drain end where the electric field is concentrated, on the drain end side in the channel direction, is increased. No. 5-283680 is disclosed.
[0011]
[Problems to be solved by the invention]
An object of the present invention is to realize a higher degree of integration in a semiconductor integrated circuit using a groove type isolation method and having a DRAM cell as an information storage unit and an information processing unit in addition to the breakdown voltage in the information storage unit, It answers both the request for ensuring reliability and the request for ensuring high-speed information processing in the information processing department.
[0012]
A further problem of the present invention is to take measures against the difficulty caused by the electric field at the junction of the impurity region formed in the semiconductor substrate and to make DRAM refresh characteristics better.
[0013]
In particular, the trench type element isolation method generally has a tendency that the junction electric field in the impurity diffusion region becomes large, and the leakage current resulting from this electric field cannot be ignored. If sufficient consideration is not given to this problem, the DRAM refresh characteristics will deteriorate as a result.
[0014]
The present invention is particularly useful for a semiconductor integrated circuit device in which an insulated gate transistor of a DRAM cell is isolated using a trench isolation method. Furthermore, the present invention is particularly useful when applied to a DRAM having a high degree of integration of 256 Mbit or more and a semiconductor device having such a DRAM. A typical example of an insulated gate transistor is a so-called MOS transistor that is practically useful. In the specification of the present application, the insulated gate type is abbreviated as a MOS type as a representative example.
[0015]
An object of the present invention is to solve the problems of the conventional semiconductor device and the method for manufacturing the same, to achieve high integration, to ensure breakdown voltage and reliability in the information storage unit, and to process information in the information processing unit It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that ensure high speed. Furthermore, another object is to provide a semiconductor device having a DRAM cell with improved refresh characteristics and a method for manufacturing the same.
[0016]
[Means for Solving the Problems]
Of the inventions disclosed in this specification, typical ones are listed as follows.
[0017]
(1) The first invention particularly relates to the thickness of the gate insulating film.
[0018]
In general, it is reasonable to change the element isolation method from the currently used selective oxide film (LOCOS (Local Oxidation of Silicon)) to the trench type isolation method from the viewpoint of integration of semiconductor integrated circuit devices. is there. However, in the case of a semiconductor device having both an information processing unit and a DRAM cell, it is necessary to set the threshold voltage of the MOS transistor in the information storage unit higher than the threshold voltage of the MOS transistor in the information processing unit. This is because it is necessary to reduce the subthreshold current when information is held.
[0019]
In the present specification, a method of positively separating a certain region by a groove is referred to as groove type separation or groove type element separation. In practice, an insulator, typically silicon oxide, is embedded in this groove provided in the semiconductor substrate.
[0020]
That is, the first invention has at least an information storage unit having a memory cell and an information processing unit, and at least the memory cell has a MOS transistor separated by a trench, and the MOS separated by the trench The gate insulating film corresponding to the boundary with the gate electrode of the impurity diffusion region serving as the source or drain of the type transistor has a gate electrode of the diffusion layer serving as the source or drain of the MOS transistor included in the information processing unit. This is a semiconductor device characterized in that it is larger than the thickness of the gate insulating film corresponding to the boundary portion.
[0021]
In this case, the thickness of the gate insulating film corresponding to the boundary portion with the gate electrode of the impurity diffusion region serving as the source or drain of the MOS transistor separated by the trench is substantially uniform in the channel spacing. May be. Further, a difference in film thickness, that is, a film thickness distribution may be provided in a region corresponding to a boundary portion with the gate electrode of the impurity diffusion region serving as a source or drain of the MOS transistor and other regions.
[0022]
Among these forms, a form in which the gate insulating film has a substantially uniform thickness in the channel corresponding portion is very advantageous in manufacturing. When the gate insulating film has a film thickness distribution, it is necessary to sufficiently manage the manufacturing conditions in order to adjust the film thickness distribution in each cell to be the same.
[0023]
In the present invention, the use of a thick gate insulating film has the following effects in consideration of the substantial configuration.
[0024]
FIG. 1 shows a cross-sectional view of the main part in this state. A groove 101 is formed in the semiconductor substrate 100. In this groove 101, silicon oxide 102 is embedded.
[0025]
According to the trench type element isolation method, after the silicon oxide 102 is buried in the trench, the surface is flattened. However, at this time, in the actual process, the surface of the silicon oxide portion of the groove-type isolation region recedes to a position 104 lower than the region corresponding to the channel 103. In this case, if the gate insulating film 105 is thin, a substantial channel portion 106 is formed at the end face portion that transitions from the original channel region 103 to the groove.
[0026]
Therefore, in addition to the original channel region, a channel also exists on the side wall of the groove portion, and the source-drain current increases. As a result, when information is held (that is, when the gate voltage is 0 V), the leakage current is effectively increased, and the information holding characteristic (that is, the refresh characteristic) is deteriorated.
[0027]
On the other hand, when a thick gate insulating film is used as in the present invention, the end face portion that transitions from the original channel region to the groove also becomes a thick insulating film as compared with the above case. Therefore, there is no problem as described above. As a result, it is possible to prevent an increase in leakage current during information retention.
[0028]
In the following description and examples, the description and illustration are omitted for more detailed points such as that the silicon oxide film embedded in the trenches recedes slightly lower during the planarization process.
[0029]
<Technical background to be further considered for ensuring refresh characteristics>
Next, the physical background will be described in order to help understanding of the present invention described below. First, as a method for element isolation, a method using a selective oxide film and a method using a trench type isolation are compared, and a specific problem in the case of the trench type isolation is clarified specifically.
[0030]
A more detailed background that occurs in the MOS transistor of the information storage unit with respect to the refresh characteristics of DRAM is summarized as follows.
[0031]
(1) Consider the phenomenon that the electric field determined by the distance between the high impurity concentration region of the impurity diffusion region and the gate electrode leaks into the depletion layer of the junction and increases the junction electric field.
[0032]
(2) Consider the effect of an increase in electric field due to precipitates resulting from knock-on oxygen atoms. This knock-on atom is related to the thickness of the gate insulating film.
[0033]
(3) Consider the leakage current caused by the electric field at the gate electrode end.
[0034]
And in terms of configuration, they consider three points: (1) impurity concentration at the end of the junction, (2) the position of the region where the electric field increases, and (3) the distance between the gate electrode and the high concentration portion of the junction. There is a need to.
[0035]
<Electric field strength in the vicinity of impurity region junction>
2 and 3 are diagrams illustrating the distribution of the electric field strength at the junction end between the gate electrode and the high impurity concentration region. From these, the difference between the trench type separation and the separation by the usual selective oxide film can be easily understood. 2A and 2B show the case of separation by a selective oxide film. FIG. 2A is a plan view of the main part, and FIG. 2B is a cross-sectional view taken along AB in FIG. FIG. 3 shows the case of groove type separation. FIG. 3A is a plan view of the main part, and FIG. 3B is a cross-sectional view taken along AB in FIG.
[0036]
In the case of the selective oxide film, an intrusion portion into the semiconductor region of the oxide film, which is usually called a bird's beak, is generated at the end of the selective oxide film. For this reason, the edge part comprised by this selective oxide film is not steep, and a semiconductor region becomes a shape which spreads below. Accordingly, the diffusion of impurities under the gate electrode expands in the lateral direction. On the other hand, in the case of groove type separation, although there is a displacement due to processing, it has an end face that is much steeper than that of the selective oxide film. For this reason, even if the impurity region is formed by the same method as in the case of using the selective oxide film, there is no impurity diffusion in the lateral direction. Therefore, the impurity concentration distribution in the semiconductor substrate is steeper than in the case of the selective oxide film.
[0037]
First, a case where element isolation is performed using a selective oxide film will be described with reference to FIG. In FIG. 2A, an impurity diffusion region 27 is formed below the gate electrode 28. Both sides of the impurity diffusion region 27 are separated from adjacent element regions by a selective oxide film 26. The impurity diffusion region 27 is formed by introducing impurities from the active region 27 (in FIG. 2A, above the paper surface of the region 27) that is not covered with the gate electrode. At this time, the impurity diffuses under the gate electrode 28 and under the selective oxide film 26. A portion where the impurity concentration of the impurity diffusion region 27 matches the substrate concentration (metallurgical bonding position) is indicated by a broken line 29.
[0038]
The impurity concentration in the vicinity of the surface of the impurity region under the gate electrode 28 is as shown in FIG. 2B for the cross section AB in FIG. The impurity concentration near the surface of the impurity region is lower than the surface concentration of the active region not covered with the gate electrode 28.
[0039]
In addition, each line of the impurity concentration in FIG. ¹⁸ cm ^-3 Iso-impurity concentration line 30, 1 × 10 ¹⁷ cm ^-3 Isoimpurity concentration line 31, 1 × 10 ¹⁶ cm ^-3 The equivalent impurity concentration line 32 is shown.
[0040]
As can be understood from FIG. 2A, when the selective oxide film is used, the portion 33 where the electric field is large is a portion where the influence of the curvature of the junction end portion is large. In the portion 33 where the electric field is large, the distance between the gate electrode 28 and the high concentration portion of the impurity diffusion region is equal to the oxide film thickness of the end portion of the selective oxide film 26 thicker than the gate oxide film 34. Therefore, there is little leakage of the electric field between the gate electrode 28 and the impurity diffusion region to the depletion layer, and the influence on the junction electric field is small. In addition, the electric field at the junction end under the gate electrode 28 becomes smaller as the impurity concentration in the impurity diffusion region becomes lower.
[0041]
On the other hand, the case of FIG. 3 in which the trench type element isolation 35 embedded with an insulating film is performed will be described. As seen in FIG. 3, the lateral extension 36 of the impurity in the impurity diffusion region 27 is only under the gate electrode 28. That is, no diffusion occurs in principle on both sides where the groove type separation 35 has been made. Therefore, the diffusion in the direction of the both sides which has occurred in the case of the selective oxide film does not occur. Therefore, the surface concentration of the impurity diffusion layer under the gate electrode 27 becomes higher than that in the case where element isolation is performed with a selective oxide film, as shown in FIG. Further, when the impurity concentration of the impurity diffusion layer under the gate electrode is large, the concentration distribution becomes steep, and the electric field strength generated thereby increases.
[0042]
At this time, as shown in FIG. 3 a), the position of the portion 37 where the junction electric field is large is below the gate oxide film 34. Therefore, the leakage of the electric field between the gate electrode and the impurity diffusion layer to the depletion layer increases. For this reason, in the region where the junction electric field is large, it is further increased due to the influence of the leakage electric field.
[0043]
As described above, the position of the portion where the junction electric field is large is different between the case where the above-described selective oxide film is used and the case where the groove type separation is used, which causes an inherent problem in the case of the groove type separation. As described above, when the element isolation is changed from the selective oxide film to the trench, the junction electric field becomes large, and the leak current caused by the electric field cannot be ignored. As a result, the refresh characteristics of the DRAM are degraded.
[0044]
<Groove element isolation and thick gate insulating film>
Each of (a) and (b) of FIG. 4 shows two examples of a semiconductor integrated circuit device having a DRAM cell having a trench-type separated MOS transistor as an information storage unit, and further having an information processing unit. It is sectional drawing which shows the principal part typically. 4A shows an example in which the gate insulating film has a difference in thickness between the central portion of the channel and the boundary portion thereof, and FIG. 4B substantially shows the portion in which the gate insulating film corresponds to the channel. An example having a uniform thickness is shown.
[0045]
In FIG. 4, the information storage unit is denoted by 42, the information processing unit is denoted by 40, and the element isolation groove is denoted by 35. When the gate insulating film has a film thickness distribution, the boundary portions of the gate insulating film are indicated as 39 and 41, and the central portions of the gate insulating film are indicated as 38 and 49. When the gate insulating film is uniform, the entire gate insulating film is shown as 47 and 48. Further, impurity diffusion regions 36, 50, 51, 52, 53, 54, 55, and 56, which are sources or drains, respectively, a gate electrode layer 37, an insulating film 150 on this gate electrode layer, and a side spacer 151.
[0046]
4A and 4B, the thickness of the gate insulating film corresponding to the boundary portion with the gate electrode of the diffusion layer serving as the source or drain of the MOS transistor included in the information storage unit 42 (see FIG. 4). 4 (a) is 39, and FIG. 4 (b) is 47), the gate insulating film corresponding to the boundary portion with the gate electrode of the impurity diffusion layer serving as the source or drain of the MOS transistor included in the information processing unit 40. The film thickness is larger than 41 (41 in FIG. 3A and 48 in FIG. 3B). As a result, it is possible to answer the request for ensuring the breakdown voltage and reliability in the information storage unit and the request for ensuring the high speed of information processing in the information processing unit while ensuring high integration by groove type separation.
[0047]
In an example in which the thickness of the gate insulating film is different between the central portion and the boundary portion, the following advantages can be obtained in addition to configuring the impurity diffusion region serving as the source or drain as a region having a plurality of impurity concentrations. Can have it. The first is useful in preventing leakage of the electric field of the gate insulating film to the junction region at the gate end. Second, since the center of the gate insulating film is thin, the threshold voltage can be reduced while reducing the leakage current between the source and the drain.
[0048]
FIG. 4C is a sectional view of the device for explaining this effect. In the information storage unit 42, the thickness of the gate oxide film 1045 at the boundary with the diffusion layer serving as the source and drain is larger than the thickness of the gate oxide film 1074 at the boundary of the MOS transistor of the information processing unit 40. It is getting bigger. By adopting this configuration, the distance between the gate electrode 1057 and the high concentration portion 1047 of the diffusion layer can be increased. That is, the electric field of the oxide film 1045 sandwiched between the gate electrode 1057 and the diffusion layer is prevented from leaking to the depletion region at the junction of the end portion of the gate electrode 1057.
[0049]
Therefore, although the electric field in the region 1046 at the gate electrode end of the MOS transistor separated from the trench type element is relatively strong, the influence of the electric field leakage can be eliminated.
[0050]
Since the gate oxide film 1045 on the depleted surface of the junction at the gate electrode end is also thickened, the threshold voltage can be increased accordingly. In this way, the leakage current between the source and drain during information retention can be reduced. The refresh characteristics of DRAM are affected by the junction leakage current caused by the junction electric field and the source-drain leakage current during information retention. Therefore, according to this structure, the increase in the electric field can be prevented. Further, the threshold voltage can be increased in consideration of the case where this electric field increase does not occur due to the effect of preventing the electric field increase. In this way, the DRAM characteristics can be further improved.
[0051]
In this case, since the gate oxide film near the center of the gate electrode is thinned, the drain current-gate voltage characteristics can reduce the threshold voltage while reducing the source-drain leakage current. As a result, the gate voltage can be lowered when reading or writing information, so that a booster circuit is not required or a slight boost is required. In this way, DRAM word lines can be driven at high speed and with low power.
[0052]
In FIG. 4C, the semiconductor substrate is 1040, the low impurity concentration impurity regions are 1046 and 1076, the high impurity concentration impurity regions are 1047 and 1077, and the insulating films on the gate electrodes 1057 and 1067 are 1150 and 1160. The silicon nitride films are shown as 1151 and 1161, and the side spacers are shown as 1058 and 1068, respectively.
[0053]
FIG. 5 shows various comparisons of drain current-gate voltage characteristics. (A) In the case of a thin gate insulating film (6 nm), (b) In the case of a thick gate insulating film (8 nm), and (c) When the gate insulating film has a film thickness distribution in the channel direction (over 6-8 nm) Examples of changing) are shown. FIG. 5 shows characteristics of an example in which the substrate and source are grounded and the drain is applied with 3V. From the viewpoint of drain current-gate voltage characteristics, it is most preferable that the gate insulating film has a film thickness distribution in the channel direction.
[0054]
<Local electric field concentration near the drain junction and knock-on atoms>
In addition to the application of the above-described invention, it is practically important to avoid the problems that may newly arise by increasing the thickness of the gate insulating film.
[0055]
First of all, the problem of knock-on atoms and local electric field concentration can be considered. Therefore, the relationship between the thickness of the gate insulating film and the knock-on atom is considered.
[0056]
FIG. 6 is a cross-sectional view showing the state of knock-on atoms in implantation of impurity ions 1 for forming the low-concentration impurity diffusion region. At the end of the gate electrode 2, oxygen atoms 4 in the gate oxide film 3 are knocked into the semiconductor substrate 5.
[0057]
FIG. 7 is a cross-sectional view showing a state in which a low concentration impurity region after ion implantation is formed. A depletion region 7 is generated at the junction formed by the low concentration diffusion layer 6 and the semiconductor substrate 5. However, in this depletion region, the oxygen precipitates 8 due to the aforementioned knock-on atoms are formed. The oxygen precipitates 8 are formed by the implantation damage becoming precipitation nuclei and the knock-on oxygen 4 being captured by the precipitation nuclei in the heat treatment after implantation.
[0058]
FIG. 7 illustrates a general situation when the gate insulating film is thin. When the gate oxide film 3 is sufficiently thinner than the implantation depth, the energy of the impurity ions 1 when passing through the gate oxide film 3 is sufficiently high. Therefore, the process of losing energy in the gate oxide film 3 is due to collision with electrons. There are few nuclear collisions with oxygen atoms, so there is less oxygen knock-on. Further, since impurities are implanted to a relatively deep depth in the substrate 5, the probability that oxygen precipitates 8 are formed in the depletion region 7 is low even when oxygen knock-on occurs.
[0059]
However, as shown in FIG. 8, when the gate oxide film 9 becomes thicker, the energy of impurity ions immediately before reaching the substrate through the gate oxide film 9 becomes lower. For this reason, the process in which impurity ions lose energy due to collision with atomic nuclei increases. For this reason, nuclear collisions between implanted ions and oxygen atoms increase, and oxygen knock-on also increases. In particular, since more impurities are implanted in the vicinity of the interface between gate oxide film 9 and substrate 5, the amount of knock-on oxygen also increases. Further, since the impurities implanted into the substrate 5 remain in a relatively shallow portion, the probability that the oxygen precipitates 11 are formed in the depleted region 10 is increased.
[0060]
In such a phenomenon, if the gate oxide film of the transistor in the DRAM cell portion is thickened as described above, the probability that the precipitate 11 is generated near the substrate surface at the end of the gate electrode increases.
[0061]
FIG. 9 shows the relationship between the electric field distribution at the end of the gate electrode and the problem of oxygen precipitates. In the figure, an isoelectric field 14 of 0 MV / cm, an isoelectric line 15 of 0.1 MV / cm, an isoelectric line 16 of 0.2 MV / cm, an isoelectric line 17 of 0.3 MV / cm, an 0.4 MV / cm, etc. Electric field lines 18 are shown. The electric field in the depletion layer 13 increases at the end portion of the gate electrode 2 due to the curvature of the end portion of the low concentration impurity diffusion layer 12.
[0062]
If the oxygen precipitates 11 are present in the portion where the electric field is large (the shaded portion 18 in the figure), local electric field concentration occurs and the junction leakage current due to the electric field increases. As a result, the refresh characteristic which is an important characteristic of the DRAM is deteriorated. For example, Japanese Patent Laid-Open No. 6-61486 (Article 6) is an example in which this is considered.
[0063]
In the element isolation method using the selective oxide film, the influence of knock-on atoms must be taken into consideration. FIG. 10 shows an example of element isolation by a selective oxide film. FIG. 10B shows an example in which the gate oxide film 3 is thin. In this case, the oxide film is substantially thick at the end of the selective oxide film 19. For this reason, oxygen knock-on also increases, and there is a possibility that a large amount of oxygen precipitates 20 is generated. However, since the electric field 16 in the depletion layer 13 is small in that portion, even if local electric field concentration occurs, the junction leakage current due to the electric field is negligible.
[0064]
However, in the example where the gate oxide film 9 is thick as shown in FIG. 10A, the oxygen precipitate 20 generated due to the knock-on of oxygen tends to exist in the strong electric field portion (shaded portion in the drawing) 17. For this reason, the junction leakage current caused by the electric field cannot be ignored.
[0065]
For example, even if two types of gate oxide films are set so that the threshold voltage can be set independently in the information storage unit and information processing unit, further measures are required for more advanced characteristics requirements. It is. For example, Japanese Patent Application Laid-Open No. 56-120166 shows a semiconductor integrated circuit device including a DRAM having a gate oxide film having two types of film thickness and a method of lowering the substrate concentration below the thick oxide film than that below the thin oxide film. (Article 9) is considered the same situation.
[0066]
That is, the threshold voltage increases as the gate oxide film of the MOS transistor in the information storage section is thickened to lower the impurity concentration of the semiconductor substrate. Therefore, it becomes impossible to reduce the leakage current between the source and the drain when holding information. Further, when the gate oxide film of the MOS transistor of the information storage unit is thinned to increase the impurity concentration of the semiconductor substrate, the electric field at the junction end at the gate electrode end increases. For this reason, the leakage current resulting from the electric field cannot be reduced. As a result, the refresh characteristic which is an important characteristic of the DRAM is affected.
[0067]
The invention described below avoids the more detailed problems described above.
[0068]
<Further enumeration of representative ones of inventions disclosed in this specification>
(2) The second invention relates to the impurity concentration of the impurity region in the semiconductor substrate.
[0069]
That is, the main point is that it has at least an information storage unit having a DRAM cell and an information processing unit, and at least the DRAM cell has a MOS transistor separated by a groove, and the MOS transistor separated by the groove. The concentration of the impurity region at the boundary between the impurity region serving as the source or drain and the gate electrode is set lower than the concentration of the impurity region at the boundary of the MOS transistor of the information processing section.
[0070]
FIG. 11 is a cross-sectional view schematically showing the main part of the second invention. That is, in FIG. 11, the information storage unit 50 and the information processing unit 52 are formed on the semiconductor substrate 1040. The MOS transistor of the information storage unit 50 is separated by the groove type 49. The thick gate insulating film is shown as 55, and the thinner gate insulating film is shown as 32. The side spacer portion is 56.
[0071]
The impurity concentration of the impurity diffusion layer serving as the source or drain of the MOS transistor is determined at the boundary portion 51 with the gate electrode at the boundary portion having the same relationship as that of the MOS transistor of the information processing unit 52. In this example, the concentration is lower than 53. In the MOS transistor of the information storage unit 50, the impurity concentration of the semiconductor substrate at the gate electrode end is lower, so that the junction electric field at the end of the gate electrode 54 can be reduced.
[0072]
By implementing this technique in combination with the first invention, a more useful semiconductor device can be realized.
[0073]
In this case, as described with respect to the first invention, the gate insulating film of the MOS transistor separated by the trench may have a substantially equivalent thickness at the channel corresponding portion, and becomes the source or drain. There may be a form in which there is a difference in film thickness between the region corresponding to the boundary portion of the diffusion layer and the gate electrode and the other region. As described above, it is advantageous in manufacturing that the gate insulating film has a substantially uniform thickness at the channel-corresponding portion.
[0074]
(3) The third invention further relates to the distance between the high concentration region of the source region or the drain region and the gate electrode.
[0075]
That is, the point is that the distance between the high concentration impurity region on the channel side of the diffusion layer serving as the source or drain of the MOS transistor and the gate electrode is the channel of the diffusion layer serving as the source or drain of the MOS transistor in the information processing section. It is characterized by being larger than the distance between the high concentration impurity region on the side and the gate electrode.
[0076]
The third invention is summarized as follows. That is, it has at least an information storage unit having a DRAM cell and an information processing unit, and at least the DRAM cell has a MOS transistor separated by a groove, and the source of the MOS transistor separated by the groove Alternatively, the thickness of the gate insulating film corresponding to the boundary between the impurity region serving as the drain and the gate electrode corresponds to the boundary between the gate electrode of the diffusion layer serving as the source or drain of the MOS transistor included in the information processing unit. The distance between the high-concentration impurity region on the channel side of the impurity region which is larger than the thickness of the gate insulating film to be separated and is the source or drain of the MOS transistor separated by this groove and the gate electrode is the MOS type of the information processing unit From the distance between the high concentration impurity region on the channel side of the impurity region that becomes the source or drain of the transistor and the gate electrode A wherein a heard.
[0077]
As described with respect to the first invention, the gate insulating film of the MOS transistor separated by the trench may have substantially the same thickness in the channel corresponding portion. In addition, the film thickness may be different between a region corresponding to the boundary between the impurity region serving as the source or drain and the gate electrode and the other region. As described above, it is advantageous in manufacturing that the gate insulating film has substantially the same thickness in the channel corresponding portion.
[0078]
In addition, as for the distance between the high concentration region of the source region or the drain region and the gate electrode, element isolation can be applied to a method using a selective oxide film. In FIG. 11 described above, the element isolation 49 may be made of a selective oxide film. In the MOS transistor of the information storage part that is element-isolated, an oxide film that is thicker than the gate oxide film 32 of the information processing part is used for the gate oxide film 55. Then, the concentration of the low-concentration diffusion layer 51 formed below the side spacer 56 of the gate electrode 54 of the MOS transistor of the information storage unit 50 is set to the concentration of the side spacer 56 of the gate electrode 54 of the MOS transistor of the information processing unit 52. The concentration is lower than that of the low concentration diffusion layer 53 formed in the lower portion. Thereby, the junction electric field at the end of the gate electrode 54 in the information storage unit 50 can be further reduced.
[0079]
(4) The fourth invention relates to a form having a structure having side spacers in particular with respect to the gate electrode.
[0080]
That is, it includes at least an information storage unit having a DRAM cell and an information processing unit. At least the DRAM cell has an element-isolated MOS transistor, and the element-isolated MOS transistor The thickness of the gate insulating film corresponding to the boundary portion with the gate electrode of the impurity region which has a side spacer portion on both sides of the electrode and which is the source or drain of the element-isolated MOS transistor The side spacer of the gate electrode of the MOS transistor that is larger than the film thickness of the gate insulating film corresponding to the boundary portion with the gate electrode of the diffusion layer serving as the source or drain of the MOS transistor included in the MOS transistor The impurity concentration of the low-concentration diffusion region of the semiconductor region located substantially corresponding to the lower part of the part is the gate of the MOS transistor of the information A wherein a lower concentration of the impurity concentration of the low concentration diffusion region of the semiconductor region located in substantially corresponding to the lower of the side spacer of the electrode.
[0081]
The gate insulating film of the MOS transistor separated by the trench may have a substantially equivalent thickness at the channel corresponding portion, and a region corresponding to the boundary portion with the gate electrode of the impurity region serving as the source or drain. A form having a difference in film thickness with other regions may also be used. As described above, it is advantageous in manufacturing that the gate insulating film has substantially the same thickness in the channel corresponding portion.
[0082]
In the case of the fourth invention, element isolation can also be performed by groove type isolation or isolation by a selective oxide film.
[0083]
An example of the fourth invention will be specifically described with reference to FIG. The concentration of the low-concentration diffusion layer 59 formed substantially corresponding to the lower part of the side spacer 58 of the gate electrode 57 of the MOS transistor of the information storage unit 50 in which the elements are separated is the gate electrode 60 of the MOS transistor of the information processing unit 52. The concentration of the low-concentration diffusion layer 62 formed substantially corresponding to the lower portion of the side spacer 61 is lower.
[0084]
A diffusion layer 68 having a concentration similar to that of the lower concentration diffusion layer 59 formed under the side spacer 58 is provided under the high concentration diffusion layer 65 of the MOS transistor of the information storage unit 50, and the information The substrate concentration distribution under the gate oxide film 63 of the MOS transistor of the storage unit 50 is made the same as described above. As a result, the junction electric field can be effectively reduced while keeping the threshold voltage high as described above.
[0085]
According to the present invention, it is possible to answer the request for ensuring the breakdown voltage and reliability in the information storage unit and the request for ensuring the high speed of information processing in the information processing unit.
[0086]
(5) The fifth invention further relates to an impurity concentration in the semiconductor substrate. In the case of the fifth invention, element isolation can also be performed by groove type isolation or isolation by a selective oxide film.
[0087]
In a semiconductor integrated circuit having a DRAM cell as an information storage unit and an information processing unit in addition, a low-concentration diffusion layer formed under the side spacer of the gate electrode of the MOS transistor of the element-isolated information storage unit. When the concentration is lower than the concentration of the low concentration diffusion layer formed under the side spacer of the gate electrode of the MOS transistor of the information processing unit, the substrate concentration under the gate oxide film of the MOS transistor of the information storage unit is To the same depth as the low-concentration diffusion layer, low from about the same depth as the low-concentration diffusion layer to about the same depth as the high-concentration diffusion layer, and higher than about the same depth as the high-concentration diffusion layer. It is a semiconductor device characterized by the above.
[0088]
As shown in FIG. 12A, the lower portion of the side spacer 58 of the gate electrode 57 of the MOS transistor of the information storage section 50 in which the element isolation 57 (either of the groove type isolation or the method using the selective oxide film) may be performed. When the concentration of the low-concentration diffusion layer 59 formed in the information processing unit 52 is lower than the concentration of the low-concentration diffusion layer 62 formed under the side spacer 61 of the gate electrode 60 of the MOS transistor of the information processing unit 52, the information storage unit The concentration distribution of the substrate 64 under the gate oxide film 63 of the 50 MOS transistor is high from the surface to substantially the same depth as the low concentration diffusion layer 59, and from the same depth as the low concentration diffusion layer 59 to the high concentration diffusion layer 65. The depth is lowered to substantially the same depth as that of the high-concentration diffusion layer 65 and higher than that of the high concentration diffusion layer 65.
[0089]
Thereby, the junction electric field between the low concentration diffusion layer 59 and the high concentration region 66 in contact therewith and the junction electric field between the high concentration diffusion layer 65 and the low concentration region 67 in contact therewith can be reduced. Therefore, the junction leakage current and the subthreshold current due to the electric field can be reduced while setting the threshold voltage of the MOS transistor of the information storage unit 50 high.
[0090]
FIG. 12A shows an example in which the thickness of the gate insulating film has a distribution, whereas FIG. 12B shows an example in which the gate insulating film has a substantially uniform thickness in a region corresponding to the channel. It is. Other configurations are the same as in FIGS. 12A and 12B.
[0091]
(C) of FIG. 12 shows an example in which the distance of the high concentration impurity region is made larger than that of the gate electrode by making the thickness of the side spacer of the information storage unit larger than that of the information processing unit. FIG. 12B is an example in which the thickness of the side spacer is the same in the information storage unit and the information processing unit. Each side spacer is 58 and 61. In the figure, the other regions of the semiconductor device are indicated by the same reference numerals as in FIG.
[0092]
FIG. 12C shows an example in which the thickness of the side spacer 581 of the information storage unit is larger than that of the information processing unit 61. For example, the side spacer 581 is 70 nm and the side spacer 61 is 50 nm. In this case, in the example in which the lateral extension of the high concentration impurity region 65 is 40 nm, the distance between the gate electrode 57 and the high concentration impurity region 65 is 30 nm on the side spacer 581 side and 10 nm on the side spacer 61 side. In the figure, other regions of the semiconductor device are indicated by the same reference numerals as those in FIG.
[0093]
FIG. 13 is a diagram showing the relationship between the distance between the high-concentration impurity region 65 and the gate electrode and the electric field strength at the gate electrode end when the gate insulating film is 8 nm. In this example, a low concentration impurity region 59 and an electric field relaxation layer 68 are formed for the high concentration impurity region 65. From FIG. 13, it is understood that the electric field intensity can be reduced from about 0.5 MV / cm to about 0.3 MV / cm.
[0094]
<Multilayer gate electrode for improvement of refresh characteristics>
The invention described below relates to a gate electrode. This electrode structure reduces the junction electric field while keeping the threshold voltage of the MOS transistor high. It is practically preferable to use these gate electrode inventions in combination with the above-mentioned inventions.
[0095]
(6) The sixth invention relates to an improvement in which the gate electrode of the MOS transistor of the information storage section has a multilayer structure.
[0096]
This gate electrode has at least a stacked layer of a polycrystalline silicon layer doped with an n-type impurity or a non-doped polycrystalline silicon layer on a gate insulating film, and a polycrystalline silicon layer doped with a p-type impurity thereon. It is. This improvement ensures a long DRAM refresh time. The polycrystalline silicon layer doped with the p-type impurity described above can also use metal or so-called metal silicide. In the present invention, element isolation can also be performed by groove type isolation or isolation by a selective oxide film.
[0097]
In a semiconductor integrated circuit having a DRAM cell as an information storage unit and an information processing unit in addition, the gate electrode of the MOS transistor of the information storage unit which is separated from each other has a multilayer structure. The lower part has at least two layers. Then, the upper part is a polycrystalline silicon layer into which p-type impurities are introduced, and the lower layer, that is, the gate oxide film is formed into a polycrystalline silicon layer into which n-type impurities are introduced or a polycrystalline silicon layer without introducing impurities. The featured semiconductor device is useful.
[0098]
FIG. 14 is a diagram showing a band structure of a cross section perpendicular to the semiconductor substrate of the gate electrode portion when the present invention is applied. An example using a polycrystalline silicon layer into which an n-type impurity is introduced as a lower layer of the gate electrode and an example using a polycrystalline silicon layer without introducing an impurity are shown.
[0099]
FIGS. 14 (a) and 14 (c) show the case when the transistor is in the ON state, and FIGS. 14 (b) and 14 (d) show the case when the transistor is in the OFF state. In the figure, the gate electrode is shown as 69, the gate insulating film as 70, and the semiconductor substrate as 71. The lower ends of the conduction bands are indicated as 80 and 81, and the upper ends of the valence bands are indicated as 83 and 84, respectively.
[0100]
As shown in FIG. 14A, when the transistor is in the ON state, it operates in the same manner as a normal gate. An inversion (channel) layer 72 is formed on the surface of the semiconductor substrate 71 under the gate oxide film 70. This is because the bending of the band structure becomes the forward direction at the junction of the p layer and the n layer provided below the gate electrode 69.
[0101]
On the other hand, when the transistor is in the OFF state, as shown in FIG. 14B, the band bend is reversed at the junction of the p layer and the n layer of the gate electrode 69, so that the depletion layer 73 is formed. This depleted region acts so that the gate oxide film is substantially thickened. Therefore, the subthreshold current when the transistor is OFF can be reduced without increasing the impurity concentration of the semiconductor substrate.
[0102]
As a result, the junction electric field can be effectively reduced while keeping the threshold voltage high.
[0103]
FIGS. 14C and 14D show band structures in the case where a polycrystalline silicon layer without introduction of impurities is used. FIG. 14C shows that when the transistor is in the ON state, and FIG. 14D shows that when the transistor is in the OFF state. Also in this case, the above-described embodiment has the same effect.
[0104]
Further, here, by including nitrogen in the interface between the polycrystalline silicon layer into which the p-type impurity is introduced and the polycrystalline silicon layer immediately above the gate oxide film, the p-type impurity is subjected to heat treatment during the manufacturing process of the semiconductor device. Can be prevented from diffusing into the polycrystalline silicon layer immediately above the gate oxide film. This makes it possible to obtain the above effect more effectively. It should be noted that the influence of the impurity diffusion can be ignored by making the polycrystalline silicon layer into which the p-type impurity is introduced into a metal or metal silicide.
[0105]
Furthermore, the above-described electrode structure can be used properly in various regions of the semiconductor integrated circuit device. FIG. 15 schematically shows the state of proper use. In the figure, regions 74 and 75 schematically show that various regions exist in one semiconductor substrate.
[0106]
The basis of the proper use is the portion 74 where the gate electrode having the polycrystalline silicon layer containing the impurity of the first conductivity type exists on the gate oxide film of the first thickness, and the gate of the second thickness. A portion 75 where a gate electrode having a polycrystalline silicon layer containing an impurity of the second conductivity type exists is provided on the oxide film. Two examples are given below. Each can obtain an effect specific to its form.
[0107]
(1) The first embodiment uses a polycrystalline silicon layer in which the first thickness is made larger than the second thickness and a p-type impurity is introduced on the thick first gate oxide film. In this case, a polycrystalline silicon layer in which an n-type impurity is introduced on the gate oxide film 2 is used.
[0108]
In this case, the operation of the p-channel MOS transistor having the first thickness gate oxide film is a surface channel type, and the operation of the n-channel MOS transistor having the first thickness gate oxide film is a buried channel type. On the other hand, the operation of the p-channel MOS transistor having the second thickness gate oxide film is the buried channel type, and the operation of the n-channel MOS transistor having the second thickness gate oxide film is the surface channel type.
[0109]
In this configuration, the speed of the surface channel type transistor can be increased, and the buried channel type n channel transistor can avoid the increase in the substrate concentration because the gate oxide film can be thickened. For example, if a buried channel type n-channel transistor is used as a transistor in the information storage section, the junction electric field can be reduced as described above. It is obvious that transistors having various operating speeds can be realized.
[0110]
(2) The second embodiment uses a polycrystalline silicon layer in which the first thickness is made larger than the second thickness and an n-type impurity is introduced on the thick first gate oxide film. In this case, a polycrystalline silicon layer in which a p-type impurity is introduced on the gate oxide film 2 is used.
[0111]
In this case, the operation of the n-channel MOS transistor having the first thickness gate oxide film is a surface channel type, and the operation of the p-channel MOS transistor having the first thickness gate oxide film is a buried channel type. On the other hand, the operation of the n-channel MOS transistor having the second thickness gate oxide film is the buried channel type, and the operation of the p-channel MOS transistor having the second thickness gate oxide film is the surface channel type. In this embodiment, an n-channel transistor using a thin gate oxide film can be realized, and an ultra-high speed operation is possible.
[0112]
Next, a method for forming the gate oxide film of the MOS transistor of the information storage unit having the above characteristics will be described.
[0113]
First, a method for manufacturing a transistor having a gate oxide film that is thick in the information storage unit and thin in the information processing unit will be described with reference to FIGS.
[0114]
<First Method for Forming Thick Oxide Film>
FIG. 16 is a cross-sectional view in order of steps for explaining the first method. The figure shows only the part of the method for forming the gate insulating film. Therefore, it goes without saying that various circuit element regions are formed in the semiconductor substrate in accordance with a usual method for manufacturing a semiconductor device.
[0115]
(1) A gate oxide film 123 having substantially the same thickness is formed by a well-known method for the information storage unit 120 and the information processing unit 121 of a predetermined semiconductor substrate 122.
[0116]
(2) A silicon film 124 to be a gate electrode is deposited.
[0117]
(3) An implantation mask 125 is formed on the surface of the silicon film 124 only in a region other than the information storage unit 120 (FIG. 16A).
[0118]
(4) Oxygen ions are implanted into the semiconductor substrate thus prepared, and then heat treatment is performed to thicken the gate oxide film 126 under the silicon film 124 of the information storage unit 120 (FIG. 16B). Note that the surface of the silicon film 124 of the information storage unit 120 is also oxidized.
[0119]
(5) After obtaining each gate insulating film having a plurality of desired thicknesses, the silicon film 124 and the silicon oxide film 127 may be removed, for example, and then a semiconductor device may be manufactured by a usual method.
[0120]
<Second Method for Forming Thick Oxide Film>
FIG. 17 is a cross-sectional view in the order of steps for explaining the second method. The figure shows only the part of the method for forming the gate insulating film. Therefore, it goes without saying that various circuit element regions are formed in the semiconductor substrate in accordance with a usual method for manufacturing a semiconductor device.
[0121]
(1) A first gate oxide film 129 having a film thickness necessary for the information storage unit 128 is formed for the information storage unit 128 and the information processing unit 131 of the predetermined semiconductor substrate 122.
[0122]
(2) A first silicon film 130 that becomes a part of the gate electrode of the information storage section is deposited on the first gate oxide film 129 (FIG. 17A).
[0123]
(3) Next, the first silicon film 130 and the first gate oxide film 129 of the information processing unit 131 are removed (FIG. 17B).
[0124]
(4) A second gate oxide film 132 having a film thickness necessary for the information processing section 131 is formed (FIG. 17C).
[0125]
(5) The gate of the information processing unit 131 on the surface of the second gate oxide film 132 of the information processing unit 131 and the oxide film 133 formed on the surface of the first silicon film 130 formed in the information storage unit 128 A second silicon film 134 to be a part of the electrode is deposited to remove the second silicon film 134 and the oxide film 133 formed on the surface of the first silicon film 130 ((d) in FIG. 17). .
[0126]
(6) A third silicon film 135 to be part of the gate electrodes of the information storage unit 128 and the information processing unit 131 is formed ((e) of FIG. 17).
[0127]
(7) Finally, gate electrode processing, low-concentration diffusion layer 137, side spacer 138 and high-concentration diffusion layer 139 are formed using a normal process, and gate oxide film 129 under silicon films 130 and 135 of information storage unit 128 is formed. A thick transistor is manufactured (FIG. 17F).
[0128]
In this system, a processing mask for obtaining the structure shown in FIG. 17B can be used as an ion implantation mask for controlling the substrate concentration of the information processing unit 131. Further, a processing mask for obtaining the structure shown in FIG. 17D can be used as an ion implantation mask for controlling the substrate concentration in the information storage unit 128. Furthermore, if ions are implanted before the silicon film 34 is processed, the influence of charge-up at the time of implantation on the gate oxide film 129 of the information storage unit 128 can be eliminated. Note that, using the above method, a structure can be obtained similarly even if the process is started from the step of forming the thin gate oxide film 132 of the information processing unit 131.
[0129]
Next, a method for providing the gate insulating film with a film thickness distribution will be described. That is, this is a method in which the thickness distribution in the channel direction of the gate oxide film of the MOS transistor in the information storage section is made larger than the thickness distribution in the channel direction of the gate oxide film of the MOS transistor in the information processing section.
[0130]
<First method for providing gate insulating film with thickness distribution>
FIG. 18 is a cross-sectional view in order of steps for explaining a first method for providing a gate insulating film thickness distribution. The figure shows only the part of the method for forming the gate insulating film. Therefore, it goes without saying that various circuit element regions are formed in the semiconductor substrate in accordance with a usual method for manufacturing a semiconductor device.
[0131]
(1) The gate oxide film 142 having the same thickness is formed on the predetermined semiconductor substrate 122 in the information storage unit 140 and the information processing unit 141.
[0132]
(2) A silicon film 143 which is a gate electrode is deposited and processed into a predetermined shape.
[0133]
(3) A silicon nitride film 144 is formed on the surface of the silicon film 143 in the information storage unit 140 ((a) of FIG. 18).
[0134]
(4) By thermally oxidizing the semiconductor substrate thus prepared, the thickness of the gate oxide film 142 under the silicon film 143 of the information storage unit 140 is increased toward the outside in the channel direction (FIG. 18B). ).
[0135]
Since the silicon nitride film 144 warps in a concave state during the above-described thermal oxidation, a tensile stress is generated in the oxide film at the end of the gate electrode. In this region, oxygen diffusion becomes faster. Therefore, a gate oxide film 145 having a large film thickness is formed with the channel direction outward. The warp of the silicon nitride film becomes larger as the deposition temperature of the silicon nitride film 144 is lower and the deposited film thickness is larger. As a result, the film thickness distribution in the channel direction can be controlled by the deposition temperature and deposited film thickness of the silicon nitride film 144.
[0136]
<Second Method of Giving Gate Insulating Film to Film Thickness Distribution>
FIG. 19 is a cross-sectional view in the order of steps for explaining a second method for providing a gate insulating film thickness distribution.
[0137]
(1) A gate oxide film 148 having the same thickness is formed on a predetermined semiconductor substrate 152 in the information storage unit 146 and the information processing unit 147.
[0138]
(2) Next, the silicon film 149 and the insulating film 150 are sequentially deposited, and the insulating film 150 and the silicon film 149 are processed into a predetermined shape to form a gate electrode (FIG. 19A).
[0139]
(3) Thereafter, a silicon nitride film 151 is formed so as to cover the surface and side walls of the gate electrode and the source and drain portions of the MOS transistor.
[0140]
(4) Cover the information processing unit 147 of the semiconductor substrate thus prepared with a mask.
[0141]
(5) Next, the silicon nitride film 151 is etched so that the silicon nitride film 151 remains on the side wall of the gate electrode of the information storage unit 146 (FIG. 19B).
[0142]
There are three possible methods for the following steps.
[0143]
(6) The first is a method of thermal oxidation and thermal oxidation in the state (5) described above ((c) in FIG. 19).
[0144]
(7) Second, a method in which the gate oxide film 148 is etched using the silicon nitride film 151 on the side wall of the gate electrode of the information storage portion as a mask and then thermally oxidized ((d) of FIG. 19).
[0145]
(8) Third, a method in which the gate oxide film 148 and the semiconductor substrate 152 are etched using the silicon nitride film 151 on the side wall of the gate electrode of the information storage unit 146 as a mask and then thermally oxidized ((e) of FIG. 19) It is.
[0146]
After this step, a transistor is manufactured by forming a diffusion layer to be a source and a drain. In this method, the film thickness distribution in the channel direction can be controlled by a method before thermal oxidation.
[0147]
According to the manufacturing method of the present invention, gate oxide films having different thicknesses can be obtained with good quality.
[0148]
To date, gate oxide films having different film thicknesses between the information storage unit and the information processing unit have been used in, for example, conventional flash memories. However, before the gate oxide film is formed, the information processing section is affected by the processing damage of the floating gate electrode silicon film and the removal damage of the interlayer insulating film of the information processing section. As a result, a high-quality gate oxide film cannot be formed. Usually, since dry etching is used for processing a silicon film and removing an interlayer insulating film, dry etching damage occurs on a semiconductor surface. Since an oxide film is formed on the damaged portion by thermal oxidation, the quality of the oxide film is deteriorated under the influence of the damage. The present invention does not have such a problem.
[0149]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
FIG. 20 is a cross-sectional view of the semiconductor device showing the manufacturing steps of the first embodiment. The information storage unit is schematically shown as 155 and the information processing unit as 156, respectively.
[0150]
As the silicon substrate 153, a p-type substrate having a (100) plane orientation of 10Ω-cm is prepared. First, a trench having a depth of 0.4 μm was formed in a portion to be an element isolation region, and then a silicon oxide film 154 was embedded in the trench by a known method.
[0151]
Next, boron was ion-implanted into the portion 157 of the information storage unit 155 and the information processing unit 156 forming the n-type MOS transistor under the following conditions. Boron implantation conditions are (1) 360xV and 2xe ¹³ /cm ² (2) 8xe at 200keV ¹² /cm ² And (3) 2xe at 50keV ¹² /cm ² There are three types. In addition, phosphorus implantation was performed on a portion 158 of the information processing unit 156 where the p-type MOS transistor was formed. The conditions are (1) 1xe at 500keV ¹³ /cm ² (2) 5xe at 240keV ¹² /cm ² And (3) 2xe at 100keV ¹² /cm ² (FIG. 20A). These impurities are not shown. Thereafter, heat treatment was performed at 1000 ° C. for 20 minutes.
[0152]
These three types of ion implantation are for the following purpose which is usually performed in the manufacture of a semiconductor device. (1) Lower substrate resistance. (2) A well is formed in a semiconductor substrate. (3) A channel stopper for preventing parasitic MOS is formed.
[0153]
Next, a silicon oxide film 159 having a thickness of 5 nm was formed by a known thermal oxidation method. Further, a silicon film 160 having a thickness of 150 nm was deposited on the oxide film 159. Here, in the silicon film 160, 2xe ²⁰ /cm ^Three Phosphorus has been introduced.
[0154]
A photoresist film having a thickness of 1 μm was formed only on the information processing unit 156. Here, oxygen ions are 2xe at 20keV ¹⁶ /cm ² Imprinting was performed to remove the mask of the photoresist film. The oxygen is implanted only into the silicon film of the information storage unit 155.
[0155]
Thereafter, a heat treatment was performed at 1000 ° C. for 20 minutes in a nitrogen atmosphere containing 1% oxygen to thicken the silicon oxide film 161 under the silicon film 160 of the information storage unit 155 to about 7 nm. This thick silicon oxide film is used as the gate insulating film of the information storage unit. A silicon oxide film 162 of about 5 nm was also formed on the surface of the silicon film 160 of the information storage unit 155 ((b) of FIG. 20).
[0156]
Next, for controlling the threshold voltage of the n-type MOS transistor 157 of the information processing unit 156, boron is set to 25 keV, 2e ¹² /cm ² Ion implantation is performed. Also, phosphorus is controlled to 2 e at 50 keV to control the threshold voltage of the p-type MOS transistor 158 of the information processing unit 156. ¹² /cm ² Ion implantation. Further, boron is controlled at 25 keV, 3e for threshold voltage control of the n-type MOS transistor 157 of the information storage unit 155. ¹² /cm ² I was ion-implanted.
[0157]
These ion implantations are customary.
[0158]
In the case of a conventional structure that does not implement the present invention, boron is 25 keV, 4.5 e for controlling the threshold voltage of the n-type MOS transistor 157 of the information storage unit 155. ¹² /cm ² It was necessary to implant ions.
[0159]
Next, the silicon oxide film 162 on the surface of the silicon film 160 is removed. A tungsten silicide film 163 having a thickness of 50 nm and a silicon oxide film 164 having a thickness of 150 nm were sequentially deposited. Then, the silicon oxide film 164, the tungsten silicide film 163, and the silicon film 160 were processed into a predetermined shape for forming a gate electrode.
[0160]
Thereafter, phosphorus is added to the portions where the n-type MOS transistors of the information storage unit 155 and the information processing unit 156 are formed at 25 keV, 5e ¹³ /cm ² Drive in. Also, boron difluoride is added at 25 keV, 2e to the portion 157 forming the n-type MOS transistor of the information processing section. ¹³ /cm ² I ion-implanted. Then, a side spacer is formed of a silicon nitride film 165 having a thickness of 50 nm on the side wall of the gate electrode.
[0161]
Further, arsenic is added at 25 keV, 1e to the part 157 of the information processing unit 156 forming the n-type MOS transistor. ¹⁵ /cm ² Ion implantation is performed. Further, boron difluoride is added at 25 keV, 1e to the portion 158 of the information processing unit 156 forming the p-type MOS transistor. ¹⁵ /cm ² I was ion-implanted. Next, heat treatment was performed at 950 ° C. for 30 seconds in a nitrogen atmosphere ((c) of FIG. 20).
[0162]
A glass film 166 containing phosphorus having a thickness of 500 nm is deposited as an interlayer insulating film. A contact hole in the information storage unit 155 and a contact hole in the information processing unit 156 are formed in the phosphor glass film 166. Then, a titanium nitride film 167 having a film thickness of 500 nm was embedded as a connecting conductor in the opening.
[0163]
Next, a glass film 168 containing phosphorus having a thickness of 100 nm is deposited as an interlayer insulating film. A bit line contact hole in the information storage unit and a contact hole in the information processing unit are formed in the phosphor glass film. Further, a tungsten film 169 having a thickness of 50 nm was deposited as a conductor and processed into a predetermined shape.
[0164]
A glass film 170 containing phosphorus having a film thickness of 300 nm is deposited on the semiconductor substrate thus prepared, and contact holes for forming capacitor electrodes of the information storage unit 155 are formed in the phosphorus glass film. A tungsten film 171 with a film thickness of 100 nm serving as a capacitor storage electrode was deposited and processed into a predetermined shape.
[0165]
Thereafter, a tantalum pentoxide film 172 having a thickness of 2.5 nm in terms of silicon oxide film thickness is formed as a capacitor insulating film. Further, a titanium nitride film 173 having a thickness of 100 nm, which is the other capacitor electrode, was deposited and processed into a predetermined shape (FIG. 20 (d)).
[0166]
After this state, the same wiring manufacturing process as that in the conventional method is used. In this way, a semiconductor integrated circuit device having the DRAM cell of the present invention as an information storage unit and also having an information processing unit is realized.
[0167]
According to this embodiment, the trench type element isolation is used and the gate oxide film of the transistor of the information storage unit can be thickened, so that the p-type impurity concentration on the substrate surface can be lowered to obtain the necessary threshold voltage. Can do. As a result, when information is held in a state where positive charges are stored in the capacitor, the electric field strength in the depletion layer of the pn junction composed of the n-type layer and the n-type substrate in contact with the storage electrode can be reduced. And the junction leakage current resulting from this electric field can be reduced. As a result, the information holding time of the bit having the shortest information holding time among all bits can be increased from about 0.05 seconds to 0.1 seconds.
[0168]
Example 2
FIG. 21 is a sectional view showing the apparatus showing the second embodiment in the order of steps. In the example of FIG. 21, the information storage unit is schematically shown as 155 and the information processing unit as 156.
[0169]
As the silicon substrate 173, an n-type substrate having a (100) plane orientation of 10 Ω-cm is prepared. First, a trench having a depth of 0.4 μm was formed in a portion to be an element isolation region, and a silicon oxide film 154 was buried in this trench by a well-known method.
[0170]
Next, a silicon oxide film 174 having a film thickness of 12 nm required for the n-type MOS transistor of the information storage unit 155 was formed by thermal oxidation, and a silicon film 175 having a film thickness of 20 nm was further deposited thereon.
[0171]
Ion implantation of boron is performed in the information storage unit 155 and the information processing unit 156 in the portion 157 where the n-type MOS transistor is formed under the following conditions. Boron implantation conditions are (1) 8e at 200keV ¹² /cm ² (2) 2e at 50keV ¹² /cm ² And (3) 2e at 25keV ¹² /cm ² It is. In addition, in the portion 158 of the information processing unit 156 forming the p-type MOS transistor, (1) 1e at 500 keV ¹³ /cm ² (2) 5e at 240keV ¹² /cm ² (3) 2e at 100keV ¹² /cm ² And (4) 2e at 25keV ¹² /cm ² The phosphorus implantation was carried out. Thereafter, heat treatment was performed at 1000 ° C. for 10 minutes (FIG. 21A). Each impurity is not shown. The meaning of ion implantation is also as described in the first embodiment.
[0172]
Then, the silicon film 175 and the silicon oxide film 174 were processed so that the area of the information storage unit 155 remained. A silicon oxide film 176 necessary for the MOS transistor of the information processing unit 156 was formed to a thickness of 5 nm by a thermal oxidation method. At this time, a silicon oxide film of approximately 10 nm is formed on the surface of the silicon film 177 of the information storage section (FIG. 21B).
[0173]
In this embodiment, the thickness of the gate insulating film 174 in the information storage unit is 12 nm, while the thickness of the gate insulating film in the information processing unit is 5 nm. Thus, the thickness of the gate insulating film 174 in the information storage unit is thicker than the thickness of the gate insulating film in the information processing unit.
[0174]
Next, a silicon film 178 having a thickness of 10 nm is deposited. Only in the information processing unit 156, a photoresist film having a thickness of 2 μm is formed on the surface of the silicon film 178. 400keV, 2e on the substrate thus prepared ¹³ /cm ² Then, boron was implanted to form a p-type high concentration buried layer. This p-type high concentration buried layer can improve hot carrier resistance. Here, 1e at 25keV ¹² /cm ² The threshold voltage of the transistor of the information processing unit 156 can be set by performing boron implantation.
[0175]
The silicon film 178 was etched using the photoresist film as a mask, and the silicon oxide film 177 formed on the surface of the silicon film 175 of the information storage unit 155 was removed (FIG. 21C).
[0176]
Thereafter, the photoresist film was removed, and a silicon film 179 having a thickness of 140 nm, a tungsten silicide film 180 having a thickness of 50 nm, and a silicon oxide film 181 having a thickness of 150 nm were deposited. Then, in order to form the gate electrode, the silicon oxide film, the tungsten silicide film, and the silicon film were processed into a predetermined shape (FIG. 21D). Subsequent steps are the same as those in the first embodiment.
[0177]
According to this embodiment, the threshold voltage necessary for the transistor of the information storage unit can be secured, and the substrate surface concentration can be reduced to half or less than the conventional one. Therefore, when information is held in a state where positive charges are stored in the capacitor, the electric field strength in the depletion layer of the pn junction composed of the n-type layer and the n-type substrate in contact with the storage electrode can be reduced. And the junction leakage current resulting from this electric field can be reduced. As a result, the information holding time of the bit having the shortest information holding time among all the bits can be increased from about 0.05 seconds to 0.3 seconds.
[0178]
Further, a gate oxide film can be formed before ion implantation for substrate concentration control or heat treatment. For this reason, the breakdown voltage deterioration of the gate oxide film can be prevented and the reliability thereof can be improved. Since ion implantation for controlling the substrate concentration can be performed before patterning of the silicon film to be the gate electrode, there is no problem of charge up at the time of implantation.
[0179]
Example 3
FIG. 22 is a cross-sectional view of the apparatus showing the third embodiment. In this example, the information storage unit is schematically shown as 155 and the information processing unit as 156. In this example, the gate insulating film has a film thickness distribution in the channel direction.
[0180]
As the silicon substrate 182, a p-type substrate having a (100) plane orientation of 10 Ω-cm is prepared. The steps until the gate oxide film 183 and the silicon film 184 are deposited are the same as those in the first embodiment.
[0181]
In this embodiment, boron is set to 25 keV, 2e for threshold voltage control of the n-type MOS transistor 157 of the information storage unit 155 and the information processing unit 156. ¹² /cm ² Ion implantation is performed.
[0182]
In addition, for controlling the threshold voltage of the p-type MOS transistor 158 of the information processing unit 156, phosphorus is set to 50 keV, 2e ¹² /cm ² I was ion-implanted. Here, the tungsten silicide film 185 used in the first embodiment was deposited on the surface of the silicon film 184. Next, a silicon nitride film 186 having a thickness of 100 nm was deposited. Then, after partially removing the silicon nitride film 186 other than the information storage section 155, a 150 nm silicon oxide film 187 was deposited on the entire substrate (FIG. 22A).
[0183]
Next, a stacked body of the silicon oxide film 187, the silicon nitride film 186, the tungsten silicide film 185, and the silicon film 184 was processed into a predetermined shape for forming a gate electrode (FIG. 22B).
[0184]
Thereafter, heat treatment was performed at 1000 ° C. for 10 minutes in an oxygen atmosphere. By this heat treatment, the silicon oxide film 183 under the silicon film 184 in the information storage unit 155 has a structure that is thick at the end of the gate electrode and thin at the center of the gate electrode. That is, a silicon oxide film having a film thickness distribution in the channel direction was obtained.
[0185]
Thereafter, phosphorus is supplied to the portion 157 forming the n-type MOS transistor in both the information storage unit 155 and the information processing unit 156 at 25 keV, 5e. ¹³ /cm ² I made a drive. Further, boron difluoride is added at 25 keV, 2e to the portion 158 of the information processing unit 156 forming the p-type MOS transistor. ¹³ /cm ² I made a drive. Then, side spacers were formed with a silicon nitride film 188 having a thickness of 50 nm on the side wall of the gate electrode (FIG. 22C). Here, the film thickness distribution in the channel direction has a film thickness distribution of 5 nm to 6 nm in portions other than the phosphorus implantation layer.
[0186]
The subsequent steps are the same as those shown in the first embodiment.
[0187]
According to this embodiment, when information is held in a state where positive charges are stored in the capacitor, a leakage current (subthreshold current) of a pn junction composed of an n-type layer and an n-type substrate in contact with the storage electrode is obtained. Therefore, the substrate concentration for obtaining the required threshold voltage can be reduced. As a result, the electric field strength in the depletion layer of the junction can be reduced. By reducing the junction leakage current due to the electric field, the information holding time of the bit having the shortest information holding time among all bits can be increased from the conventional 0.05 seconds to 0.1 seconds.
[0188]
In addition, since the thin gate oxide film portion where the withstand voltage failure increases is reduced, the occurrence frequency of the withstand voltage failure can be reduced.
[0189]
Example 4
FIG. 23 is a sectional view showing a semiconductor device according to the fourth embodiment. FIG. 23 schematically shows the information storage unit as 155 and the information processing unit as 156. This example is another example in which the thickness of the gate insulating film has a thickness distribution in the channel direction.
[0190]
The steps up to deposition of the silicon substrate 182 and the tungsten silicide film 185 to be the gate electrode are the same as in the third embodiment.
[0191]
It should be noted that the amount of implantation with boron implantation having the lowest implantation energy for controlling the threshold voltage of the transistor of the information storage unit 155 was performed by changing the following method relating to formation of the gate insulating film to methods 1 to 3. Specifically, method 1 is 3xe ¹² /cm ² In method 2, 2xe ¹² /cm ² And in method 3, 1xe ¹² /cm ² It was. Details of each of these methods will be described later.
[0192]
A silicon oxide film 189 having a thickness of 150 nm was deposited on the silicide film 185. Then, in order to form the gate electrode, the stacked body of the silicon oxide film 189, the tungsten silicide film 185, and the silicon film 184 was processed into a predetermined shape (FIG. 23A).
[0193]
Next, a silicon nitride film 190 having a thickness of 10 nm is deposited. An etching mask for only the information processing unit 156 was formed, and the silicon nitride film 190 was processed by anisotropic dry etching. Thus, the silicon nitride film 190 remains on the side wall of the gate electrode of the information storage unit 155, and so-called side spacers are formed.
[0194]
Furthermore, as a method for forming the gate insulating film, the following method was adopted by the following three methods.
[0195]
(1) Method 1: Method 1 performs heat treatment in an oxygen atmosphere at 900 ° C. for 10 minutes in this state.
[0196]
(2) Method 2: In Method 2, after the gate oxide film 183 of the information storage unit 155 is etched, heat treatment is performed in an oxygen atmosphere at 900 ° C. for 10 minutes.
[0197]
(3) Method 3: In Method 3, after the silicon substrate 182 is further etched by 20 nm, heat treatment is performed in an oxygen atmosphere at 900 ° C. for 10 minutes.
[0198]
The cross-sectional structure of the semiconductor device when each method is adopted corresponds to FIGS. 23 (c) to 23 (e).
[0199]
In the heat treatment in an oxygen atmosphere at 900 ° C. for 10 minutes, a silicon oxide film of approximately 50 nm is formed on the surface of the silicon substrate 182. After that, phosphorus is added to the portion 157 of the information storage unit 155 and the information processing unit 156 forming the n-type MOS transistor at 25 keV, 5e ¹³ /cm ² I typed in. Also, boron difluoride is added at 25 keV to the portion 158 of the information processing unit 156 forming the p-type MOS transistor at 2 keV. ¹³ /cm ² I struck it.
[0200]
Here, the film thickness distribution of the gate oxide film 183 in the channel direction in the portion other than the phosphorus implantation layer is as follows. In the method 1 (FIG. 23 (c)), the film thickness distribution of 5 nm to 6 nm, in the method 2 (FIG. 23 (d)), the film thickness distribution of 5 nm to 7 nm, and in the method 3 (FIG. 23 (e)). It has a thickness distribution of 5 nm to 9 nm.
[0201]
Next, side spacers are formed with a silicon nitride film 191 having a thickness of 50 nm on the sidewall of the gate electrode. Further, arsenic is added at 25 keV, 1e to the part 157 of the information processing unit 156 forming the n-type MOS transistor. ¹⁵ /cm ² Drive in. In addition, boron difluoride is added to the portion of the information processing unit 156 where the p-type MOS transistor is formed 158 at 25 keV for 1e. ¹⁵ /cm ² I struck it.
[0202]
The subsequent steps are the same as those shown in the first embodiment.
[0203]
According to this embodiment of the above-described method 1 to method 3, it is possible to reduce the substrate concentration while maintaining the required threshold voltage of the transistor by the film thickness distribution of the gate oxide film in each channel direction. It is. As a result, the information holding time of the bit having the shortest information holding time among all bits can be extended from the conventional 0.05 seconds. The information retention time was 0.1 seconds for method 1, 0.2 seconds for method 2, and 0.4 seconds for method 3.
[0204]
In addition, according to the present embodiment, the frequency of occurrence of the breakdown voltage failure can be reduced by reducing the thin gate oxide film portion where the breakdown voltage failure increases.
[0205]
<Summary of characteristics of examples>
FIG. 24 and FIG. 25 collectively show the results when the present invention is adopted as the structure of the gate oxide film of the transistor in the information storage section. FIG. 24 shows information retention characteristics. The horizontal axis represents the DRAM refresh time, and the vertical axis represents the cumulative frequency corresponding to the horizontal axis in standard deviation. FIG. 25 shows the gate oxide film breakdown voltage occurrence density. The horizontal axis indicates the thickness of the minimum portion of the gate insulating film, and the vertical axis indicates the breakdown voltage occurrence density. In the figure, “uniform SiO2 film” indicates that the gate insulating film has substantially no film thickness distribution. As a result, the “bird's beak SiO2 film” indicates that the gate insulating film is in the channel direction. It is a result of having a film thickness distribution.
[0206]
From FIG. 24, it can be understood that the information holding time is increased by increasing the thickness of the gate oxide film of the transistor in the information storage portion and by providing a film thickness distribution in the channel direction. Increasing the thickness of the gate oxide film is useful by making it possible to reduce the substrate concentration and extending the information holding time.
[0207]
Further, it can be seen from FIG. 25 that the density of occurrence of defective breakdown voltage of the gate oxide film becomes smaller as the film thickness distribution in the channel direction is larger than in the case of the gate oxide film uniform in the channel direction.
[0208]
Example 5
FIG. 26 is a cross-sectional view of the semiconductor device showing the fifth embodiment. In FIG. 26, the information storage unit is schematically illustrated as 155 and the information processing unit is illustrated as 156.
[0209]
The silicon substrate and the process are basically the same as those in the third embodiment, but the following three ion implantation conditions were selected.
[0210]
(1) Method 4: Method 4 is a case in which the phosphorus implantation amount before forming the side spacer is reduced in the information storage unit 155. This state is shown in FIG.
[0211]
(2) Method 5: Method 5 uses the following two means. First, shallower boron implantation is added for controlling the threshold voltage of the transistor of the information storage unit 155. In addition, secondly, phosphorus implantation at a low concentration was added following the arsenic implantation after the formation of the side spacers in the information storage unit 155. This state is shown in FIG.
[0212]
(3) Method 6: Method 6 is a case where method 4 and method 5 described above are combined.
In these methods, the conditions were slightly changed from those of the ion implantation methods of the previous examples. Specifically, in the method 4, the phosphorus implantation amount is half that of the third embodiment, and in the method 5, 5e at 25 keV. ¹¹ /cm ² 3e with boron difluoride implant and 150keV ¹² /cm ² Added phosphorus implant.
[0213]
According to the examples of the above method 4 and method 6, the electric field of the low concentration layer between the gate electrode and the high concentration layer can be reduced while maintaining the threshold voltage of the transistor. In addition, the electric field strength in the depletion layer of the pn junction composed of the high concentration diffusion layer and the substrate could be reduced. As a result, the information holding time of the bit with the shortest information holding time among all the bits can be increased from the conventional 0.05 seconds. The information retention time described above was 0.5 seconds for Method 4, 0.5 seconds for Method 5, and 0.6 seconds for Method 6.
[0214]
Example 6
FIG. 27 is a sectional view of an apparatus for explaining the sixth embodiment. This embodiment is an example in which the gate electrode of the MOS transistor of the information processing unit has a multilayer structure. An example of this gate electrode is one having at least a stacked layer of a polycrystalline silicon layer doped with n-type impurities or non-doped on a gate insulating film, and a polycrystalline silicon layer doped with p-type impurities thereon.
[0215]
FIG. 27 schematically shows a main part of a semiconductor integrated circuit having a DRAM cell as an information storage unit and an information processing unit. In the figure, a semiconductor device using trench type element isolation is shown. However, in the implementation of this gate electrode, element isolation may be performed by a selective oxide film (usually referred to as LOCOS).
[0216]
After forming the gate oxide film 77 of the MOS transistor of the information storage section 76 that has been subjected to element isolation, ¹⁶ /cm ^Three An n-type polycrystalline Si layer 78 mixed to the extent is formed to a thickness of 10 nm. Next, the surface of the n-type polycrystalline Si layer 78 is treated in ammonia (700 ° C., 10 seconds) to mix nitrogen in the vicinity of the surface. On the n-type polycrystalline Si layer 78 subjected to such treatment, 10% of boron is present. ²⁰ /cm ^Three A p-type polycrystalline Si layer 79 mixed to some extent was deposited to 200 nm.
[0217]
Thereafter, similarly to the above example, the gate electrode was formed by processing into a predetermined shape including the laminated polycrystalline Si layer.
[0218]
In this embodiment, the gate electrode portion of the MOS transistor other than the information storage portion has a usual structure. That is, after forming the gate oxide film 77, a p-type polycrystalline Si layer 79 mixed with about 1020 / cm 3 of boron was deposited to 200 nm.
[0219]
By applying the gate electrode structure to the information storage unit, the following three improvements could be made.
[0220]
(1) The equivalent gate oxide film thickness when the transistor is OFF can be increased by about 3 nm.
[0221]
(2) The substrate concentration was able to be halved.
[0222]
(3) The junction electric field could be reduced by 30%.
[0223]
As a result, the refresh time could be tripled compared to the case of the same gate oxide film thickness.
[0224]
Further, after forming the gate oxide film, the polycrystalline silicon layer 78 containing no impurities is deposited to 10 nm, and the same effect as above is obtained even when the p-type polycrystalline silicon layer 79 similar to the above is deposited to 200 nm. I was able to.
[0225]
Furthermore, the following structure can also be taken. That is, (1) a case where a tungsten film 79 having a thickness of 200 nm is formed on the 10 nm polycrystalline Si layer 78, and (2) a case where a titanium silicide film having a thickness of 200 nm is formed. In this case, the same junction electric field as in the case of the above-described structure in the present embodiment can be realized. On the other hand, the junction leakage current slightly increased in this case, and the refresh time was about twice. Of course, the refresh time has the advantage that it can be longer than before.
[0226]
Example 7
FIG. 28 is a sectional view showing the main part of a semiconductor device according to the seventh embodiment. This example shows an example in which the thickness of the gate insulating film and the conductivity type of the gate electrode are variously selected according to the demand of the semiconductor integrated circuit device to be produced. Specifically, in this example, various types of MOS transistors are properly used for an information storage unit, an information processing unit, a high voltage generation circuit, and an information input / output circuit in a semiconductor integrated circuit.
[0227]
In the figure, n-type wells 84 and 86 and p-type wells 85 and 87 are formed on a semiconductor substrate.
[0228]
A p-channel MOS transistor is formed as a surface channel type on the surface of the n-type well 84, and this is used as the MOS transistor of the information storage section. In this case, a thick gate insulating film 80 is used.
[0229]
On the other hand, an n-channel MOS transistor is formed as a buried channel type on the surface of the p-type well 85 and used as a high voltage generation circuit or an information input / output circuit. In this case, a thick gate insulating film 80 is used for high breakdown voltage.
[0230]
A thin gate insulating film 80 is formed in each of the n-type well and the p-type well. These are used as MOS transistors in the information processing section.
[0231]
Hereinafter, processes related to the formation of the gate electrode portion will be described. Other steps may be performed using usual methods. First, a gate oxide film 80 having a thickness of 10 nm is formed in a region that requires a thick gate insulating film on a semiconductor substrate that has been prepared in advance. Then, a polycrystalline silicon layer 81 into which a p-type impurity similar to that described in Example 6 is introduced is formed thereon.
[0232]
On the other hand, in a region requiring a thin gate insulating film, a gate oxide film 82 having a thickness of 5 nm is formed in a predetermined region on the semiconductor substrate. And on this there are 10 phosphorus ²⁰ /cm ^Three A polycrystalline silicon layer 83 introduced to the extent is deposited to 200 nm.
[0233]
Thus, on the surface of the n-type well layer 84 having the gate oxide film having a thickness of 10 nm, the operation of the p-channel MOS transistor is used as the surface channel type for the transistor of the information storage portion. On the other hand, on the surface of the p-type well layer 85 having a gate oxide film having a thickness of 10 nm, the operation of the n-channel MOS transistor is made a buried channel type and used as a transistor of a high voltage generation circuit and an information input / output circuit.
[0234]
In addition, on the surface of the n-type well layer 86 having a gate oxide film having a thickness of 5 nm, the operation of a p-channel MOS transistor is used as a buried channel type transistor. On the other hand, on the surface of the p-type well layer 87 having a gate oxide film having a thickness of 5 nm, the operation of the n-channel MOS transistor is used as a surface channel transistor in the information processing section.
[0235]
As a result, the access time can be reduced to half of the conventional time, and the refresh time can be increased to five times. Note that this embodiment is an example, and as described above, the combination of the gate oxide film thickness and the conductivity type of the gate electrode can be implemented in various semiconductor elements according to respective requirements.
[0236]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0237]
According to the first invention of the present application, a semiconductor integrated circuit device having a DRAM cell having an information storage unit and an information processing unit can realize higher integration and ensure reliability in the information storage unit. And high speed in the information processing unit can be secured.
[0238]
In addition, by using a gate oxide film having a film thickness distribution in the channel direction of the MOS transistor, the occurrence frequency of gate breakdown voltage failure can be reduced.
[0239]
According to the second to fourth inventions of the present application, a semiconductor integrated circuit device having a DRAM cell having an information storage unit and an information processing unit can realize a higher degree of integration and improve its refresh characteristics. I can do it.
[0240]
According to the fifth aspect of the present invention, the junction leakage current and the subthreshold current can be reduced while increasing the threshold voltage of the MOS transistor.
[0241]
According to the sixth invention of the present application, the junction electric field can be reduced while keeping the threshold voltage of the MOS transistor high.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a gate electrode portion for explaining one of the roles of a thick gate insulating film.
FIG. 2 is a diagram illustrating an impurity concentration distribution when a selective oxide film is used.
FIG. 3 is a diagram illustrating an impurity concentration distribution when a selective oxide film is used.
FIG. 4 is a cross-sectional view of a main part of a MOS transistor in an information storage unit and an information processing unit.
FIG. 5 is a diagram comparing sub-threshold characteristics of various MOS transistors.
FIG. 6 is a cross-sectional view for explaining a knock-on state of oxygen at an end portion of the gate electrode at the time of ion implantation.
FIG. 7 is a cross-sectional view showing a relationship between a depletion layer and an oxygen precipitate at an end portion of a gate electrode.
FIG. 8 is a cross-sectional view showing the relationship between a depletion layer and oxygen precipitates at the end of a gate electrode.
FIG. 9 is a cross-sectional view showing the relationship between the electric field distribution at the edge of the gate electrode and oxygen precipitates.
FIG. 10 is a cross-sectional view showing the relationship between the electric field distribution at the element isolation end and oxygen precipitates.
FIG. 11 is a cross-sectional view of a main part of a MOS transistor in an information storage unit and an information processing unit.
FIG. 12 is a cross-sectional view of the main part of an information storage unit having a MOS type transistor having an improved gate insulating film and an information processing unit having a MOS type transistor having a usual gate insulating film.
FIG. 13 is a diagram showing the relationship between the distance between the gate insulating film edge and the high-concentration impurity region and the electric field strength at the gate electrode edge.
FIG. 14 is a diagram showing a band structure in a gate electrode / oxide film / semiconductor substrate system;
FIG. 15 is a plan view illustrating the arrangement of various transistors according to the present invention.
FIG. 16 is a cross-sectional view showing a thick gate oxide film forming method according to the present invention in the order of steps.
FIG. 17 is a cross-sectional view showing another method of forming a thick gate oxide film according to the present invention.
FIG. 18 is a cross-sectional view showing a method for forming a gate oxide film having a film thickness distribution according to the present invention.
FIG. 19 is a cross-sectional view showing another method of forming a gate oxide film having a film thickness distribution according to the present invention in the order of steps.
FIG. 20 is a cross-sectional view of a main part for explaining the semiconductor device shown in the first embodiment;
FIG. 21 is a cross-sectional view of a main part for explaining the semiconductor device shown in the second embodiment;
FIG. 22 is a cross-sectional view of the main part for explaining the semiconductor device shown in the third embodiment;
FIG. 23 is a cross-sectional view of the main part for explaining the semiconductor device shown in the fourth embodiment;
FIG. 24 is a diagram showing information retention characteristics of various semiconductor devices shown in the first to fourth embodiments.
FIG. 25 is a diagram showing the relationship between the gate insulating film thickness and the gate breakdown voltage density when the gate insulating film has a film thickness distribution.
FIG. 26 is a cross-sectional view of the main part for explaining the semiconductor device shown in the fifth embodiment;
FIG. 27 is a cross-sectional view of the main part for explaining the semiconductor device shown in the sixth embodiment;
FIG. 28 is a cross-sectional view of the main part for explaining the semiconductor device shown in the seventh embodiment;
[Explanation of symbols]
1 ... impurity ions, 2, 9, 28, 37, 43, 54, 57, 60, 69 ... gate electrodes, 3, 34, 38, 45, 47, 48, 55, 63, 70 ... gate oxide films, 4 ... Knock-on oxygen, 5, 64, 71 ... semiconductor substrate, 6, 12, 25, 27, 44, 51, 53, 59, 62, 65, 68 ... diffusion layer, 7, 10, 13, 24 ... depletion region (depletion Layer), 8, 11, 20, 23 ... oxygen precipitates, 14, 15, 16, 17, 18 ... isoelectric lines, 19, 26 ... selective oxide films, 29, 36 ... metallurgical bonding positions, 30, 31, 32 ... iso-impurity concentration line, 33 ... strong electric field part, 35, 49 ... groove type element isolation, 39, 41, 46 ... gate end, 56, 58, 61 ... side spacer, 66 ... high concentration layer of substrate, 67 ... Low concentration layer of substrate, 74 ... First conductivity type on gate oxide film of first thickness A region having a polycrystalline Si film containing an impurity, 75... A region having a polycrystalline Si film containing a second conductivity type impurity on a gate oxide film having a second thickness
42, 50, 120, 128, 140, 146, 155 ... Information storage unit, 40, 52, 121, 131, 141, 147, 156 ... Information processing unit, 123, 126, 129, 132, 142, 145, 148, 161, 174, 183 ... gate oxide film, 119, 137, 139 ... n-type diffusion layer, 21, 171 ... storage electrode, 122, 152, 153, 173, 182 ... semiconductor substrate, 124, 130, 134, 135, 143 149, 160, 175, 178, 184 ... silicon film, 125 ... mask, 22, 127, 133, 136, 150, 162, 164, 177, 181, 187, 189 ... silicon oxide film, 138, 165, 166, 168, 170, 188 ... insulating film, 144, 151, 186, 190, 191 ... silicon nitride film, 163, 180, 185 ... tungsten silicide film, 167, 173 ... titanium nitride film, 169, 171 ... tungsten film, 172 ... Tantalum oxide film.

Claims (11)

At least an information storage unit having a dynamic random access memory cell, and an information processing unit, wherein at least the dynamic random access memory cell has a first insulated gate transistor separated by a trench The upper surface of the isolation groove of the groove type isolation is formed lower than the channel region of the first insulated gate transistor, and the gate insulating film of the first insulated gate transistor isolated from the trench type is the channel region. The gate insulating film of the second insulated gate transistor included in the information processing section has a central portion along the channel direction in the channel region. more has a thick film thickness at both ends, and groove-type isolated saw of the first insulated gate transistor Alternatively, the gate insulating film corresponding to the boundary with the gate electrode of the impurity diffusion region serving as the drain has a gate electrode in the impurity diffusion region serving as the source or drain of the second gate insulating transistor included in the information processing unit. A semiconductor device characterized in that it is larger than the thickness of the gate insulating film corresponding to the boundary portion between the gate insulating film and the gate insulating film.   At least an information storage unit having a dynamic random access memory cell and an information processing unit, wherein at least the dynamic random access memory cell has a first insulated gate transistor separated by a trench The upper surface of the isolation groove of the groove type isolation is formed lower than the channel region of the first insulated gate transistor, and the gate insulating film of the first insulated gate transistor isolated from the trench type is the channel region. The gate insulating film of the second insulated gate transistor included in the information processing section has a uniform thickness along the channel direction in the channel region. The thickness of the central portion of the gate insulating film of the first insulated gate transistor having the thickness and separated by the trench is The gate of the impurity diffusion region which is equal to the thickness of the central portion of the gate insulating film of the second insulated gate transistor included in the information processing section and which serves as the source or drain of the first insulated gate transistor separated by the trench The gate insulation film corresponding to the boundary portion with the gate electrode of the impurity diffusion region serving as the source or drain of the second gate insulating transistor included in the information processing unit has a film thickness of the gate insulating film corresponding to the boundary portion with the electrode A semiconductor device characterized by being larger than the film thickness.   The thickness of the insulating film that forms the boundary between the insulating film in the trench isolation region of the first insulating gate transistor and the gate insulating film included in the information storage unit including the dynamic random access memory cell is: 3. The thickness of the insulating film that forms a boundary between the insulating film in the groove type isolation region of the second insulating gate type transistor and the gate insulating film of the second insulating gate type transistor included in the information processing unit. The semiconductor device according to any one of the above.   In the channel region of the first insulated gate transistor included in the information storage unit, the channel has a first concentration in the depth direction of the channel, from the substrate surface to the first depth, and from the first depth to the first depth. A second concentration lower than the first concentration at a depth of 2 and a third concentration distribution higher than the second concentration from the second depth to the third depth; 3. The semiconductor device according to claim 1, wherein the channel region of the second edge-gate transistor included in the information processing unit does not have a concentration distribution in the depth direction of the channel. 4.   A second insulated gate type transistor having an information processing section in which the distance between the high concentration impurity region on the channel side of the impurity diffusion layer serving as the source or drain of the first insulated gate type transistor isolated from the groove type and the gate electrode is 3. The semiconductor device according to claim 1, wherein the distance between the high-concentration impurity region on the channel side of the impurity diffusion region serving as the source or drain of the gate electrode and the gate electrode is larger.   The concentration of the impurity diffusion region at the boundary with the gate electrode of the impurity diffusion region serving as the source or drain of the first insulated gate transistor isolated from the trench type is the second insulated gate of the information processing unit. 3. The semiconductor device according to claim 1, wherein the concentration is lower than a concentration of an impurity diffusion region in the boundary portion of the type transistor. The gate electrode of the first insulated gate transistor of the groove-separated information storage unit has a multilayer structure, and a polycrystalline silicon layer into which an n-type impurity is introduced immediately above the gate oxide film or a polycrystal without impurity introduction silicon layer, the semiconductor device according to the layer of the upper in any one of claims 1 or 2, characterized in that a polycrystalline silicon layer obtained by introducing a p-type impurity. The gate electrode of the insulated gate transistor of the information storage section separated into the groove type has a multi-layer structure, the upper two layers are polycrystalline silicon layers into which p-type impurities are introduced, and the n-type impurities are directly above the gate oxide film. The introduced polycrystalline silicon layer or a polycrystalline silicon layer without impurity introduction contains nitrogen at the interface between the polycrystalline silicon layer introduced with p-type impurities and the polycrystalline silicon layer introduced with n-type impurities immediately above the gate oxide film The semiconductor device according to claim 1 , wherein: Forming a separation groove for groove type separation on the substrate surface, forming a gate oxide film having a predetermined thickness on the first region and the second region on the substrate, a gate electrode on the gate oxide film, and Forming an insulating film on the gate electrode and forming the insulating film and the gate electrode in a desired shape; a surface and sidewalls of the gate electrode formed on the first and second regions; and a source of the insulated gate transistor And a step of forming a silicon nitride film so as to cover the substrate surface corresponding to the drain portion, the surface and sidewalls of the gate electrode on the second region, and the surface of the substrate corresponding to the source and drain portions of the insulated gate transistor A step of masking the silicon nitride film so as to cover the gate electrode in the first region and the source and drain portions of the insulated gate transistor; Removing the silicon nitride film on the body surface and leaving the silicon nitride film on at least the gate electrode side wall of the first region; at least on the gate electrode side wall of the second region and the source and drain portions of the insulated gate transistor; Thermal oxidation is performed with the silicon nitride film remaining on the surface of the corresponding substrate, and the film thickness of the gate oxide film in the first region close to the source and drain portions of the insulated gate transistor is determined as the film at the center of the gate electrode. A method for manufacturing a semiconductor device, comprising a step of making the thickness greater than the thickness. Forming a separation groove for groove type separation on the substrate surface, forming a gate oxide film having a predetermined thickness on the first region and the second region on the substrate, a gate electrode on the gate oxide film, and Forming an insulating film on the gate electrode and forming the insulating film and the gate electrode in a desired shape; a surface and sidewalls of the gate electrode formed on the first and second regions; and a source of the insulated gate transistor And a step of forming a silicon nitride film so as to cover the substrate surface corresponding to the drain portion, the surface and sidewalls of the gate electrode on the second region, and the surface of the substrate corresponding to the source and drain portions of the insulated gate transistor A step of masking the silicon nitride film so as to cover the gate electrode in the first region and the source and drain portions of the insulated gate transistor; Removing the silicon nitride film on the body surface and leaving the silicon nitride film on at least the gate electrode side wall of the first region; at least on the gate electrode side wall of the second region and the source and drain portions of the insulated gate transistor; The gate oxide film in the first region is etched and thermally oxidized while leaving the silicon nitride film on the corresponding substrate surface, and the source and drain of the insulated gate transistor in the gate oxide film in the first region are etched. A method of manufacturing a semiconductor device, comprising the step of making the film thickness close to the portion thicker than the film thickness at the center of the gate electrode. Forming a separation groove for groove type separation on the substrate surface, forming a gate oxide film having a predetermined thickness on the first region and the second region on the substrate, a gate electrode on the gate oxide film, and Forming an insulating film on the gate electrode and forming the insulating film and the gate electrode in a desired shape; a surface and sidewalls of the gate electrode formed on the first and second regions; and a source of the insulated gate transistor And a step of forming a silicon nitride film so as to cover the substrate surface corresponding to the drain portion, the surface and sidewalls of the gate electrode on the second region, and the surface of the substrate corresponding to the source and drain portions of the insulated gate transistor A step of masking the silicon nitride film so as to cover the gate electrode in the first region and the source and drain portions of the insulated gate transistor; Removing the silicon nitride film on the body surface and leaving the silicon nitride film on at least the gate electrode side wall of the first region; at least on the gate electrode side wall of the second region and the source and drain portions of the insulated gate transistor; The gate oxide film and the semiconductor substrate in the first region are etched with the silicon nitride film remaining on the corresponding substrate surface, and then thermally oxidized, so that the gate oxide film in the first region of the insulated gate transistor is formed. A method of manufacturing a semiconductor device, comprising a step of making a film thickness close to a source and drain portions larger than a film thickness at a central portion of a gate electrode.

Images