JP3667528B2 - Digital delay circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital circuit, and more particularly to a digital delay circuit having a large additional delay time.
[0002]
[Prior art]
Also in a digital circuit, a delay circuit is necessary as one of basic circuits like an analog circuit. The digital delay circuit is a circuit that delays data and a clock to the digital circuit, and is used for various purposes.
[0003]
An example of a conventional digital delay circuit is disclosed in, for example, Japanese Patent Laid-Open No. 3-261217. This digital delay circuit has a configuration as shown in FIG. That is, data is input to one input terminal 103 of a 2-port RAM (random access memory) 108. On the other hand, a counter (counting) circuit 104 is connected to the clock (CLK) terminal 101 and the reset (RST) terminal 102 and input to the RA terminal of the 2-port RAM 108 via the decoder circuit 105.
[0004]
The clock at the clock terminal 101 is input to the WA terminal of the 2-port RAM 108 via the delay element 106 and the gate 107. The delayed digital data is output from the output terminal 109 of the 2-port RAM 108. According to the digital delay circuit having such a configuration, a sufficiently large and controllable delay time can be obtained by sequentially storing or storing the digital data of the input terminal 103 in the 2-port RAM 108 and sequentially reading out from the 2-port RAM 108 after the additional delay time. The delayed output data can be output from the output terminal 109. This delay time is determined by the clock cycle and the count setting value of the counter circuit 104.
[0005]
[Problems to be solved by the invention]
According to the conventional digital delay circuit described above, when the delay time to be added is increased, there is a problem that the storage capacity (scale) and power consumption of the 2-port RAM for storing data increase accordingly. For example, when the additional delay amount is doubled, the number of words in the 2-port RAM needs to be doubled. The reason is that when the input data of all times is stored sequentially in the 2-port RAM, the address once the data has been written is stored until the data is read out, and is used as a new data write area. This is because it cannot be used.
[0006]
Therefore, an object of the present invention is to provide a digital delay circuit that can suppress an increase in circuit scale and power consumption even when the amount of additional delay (time) increases.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems, the digital delay circuit according to the present invention employs the following characteristic configuration.
[0008]
(1) In a digital delay circuit that stores input data in a 2-port RAM, reads the input data stored in the 2-port RAM after an arbitrary time, and uses it as output data.
A change point detection circuit for obtaining change point information of the input data;
A write control circuit having a counter and a clock generation circuit, and writing the changed input data into the 2-port RAM based on the change point information of the change point detection circuit;
A digital delay circuit comprising a counter and a clock generation circuit, and a read control circuit for reading data stored in the 2-port RAM through a delay circuit for delaying the change point information.
[0009]
(2) The digital delay circuit according to (1), wherein a shift register is used as the delay circuit.
[0010]
(3) The digital delay circuit according to (1) or (2), wherein a DFF and a comparison circuit are used as the change point detection circuit.
[0011]
(4) the write control circuit and read control circuit includes each counter and DFF, the clock generation circuit including an inverter and an OR gate (1), the digital delay circuit (2) or (3).
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the digital delay circuit of the present invention will be described in detail with reference to the accompanying drawings.
[0015]
FIG. 1 is a block diagram of a preferred embodiment of the digital delay circuit of the present invention. FIG. 2 is a detailed circuit diagram of the digital delay circuit of FIG. FIG. 3 is a specific circuit diagram of the comparison circuit used in FIG. FIG. 4 is a configuration example of the clock generation circuit used in FIG. FIG. 5 is a timing chart for explaining the operation of the digital delay circuit of FIG.
[0016]
First, a description will be given with reference to FIG. The digital delay circuit of the present invention uses the 2-port RAM 7 as in the conventional example. Input data is input to the write data input WD of the 2-port RAM 7 and the change point detection circuit 3 via the input terminal 1. The change point detection circuit 3 generates change point information of input data and inputs it to the write control circuit 5 and the delay circuit 4. The write control circuit 5 generates a write control signal to the 2-port RAM 7 from change point information of input data. On the other hand, the delay circuit 4 adds an arbitrary delay to the change point information of the input data and outputs it. The read control circuit 6 generates a read control signal for the 2-port RAM 7 from the change point information of the input data to which an arbitrary delay is added by the delay circuit 4. Data read from the 2-port RAM 7 is output as output data via the output terminal 2.
[0017]
Next, the operation of the digital delay circuit of FIG. 1 will be described. Since the write control circuit 5 stores new data in the 2-port RAM 7 only when there is a change in the input data based on the input data change point information given by the change point detection circuit 3, the write address and write A signal required for processing (for example, a write clock when the 2-port RAM 7 is synchronous) is generated.
[0018]
On the other hand, the read control circuit 6 converts the data stored in the 2-port RAM 7 by the write control circuit 5 based on the input data change point information to which an arbitrary delay is added by the delay circuit 4, after an arbitrary delay time has elapsed. A read address to be read later and a signal necessary for the read process (a read clock when the two-port RAM 7 is synchronous, for example) are generated. Thus, only the change point information of the input data can be stored in the 2-port RAM 7 and read from the 2-port RAM 7 after the delay time set by the delay circuit 4 to obtain the output data from the output terminal 2.
[0019]
Next, a specific circuit configuration and operation of the digital delay circuit of the present invention will be described with reference to FIG. FIG. 2 shows a synchronous 2-port RAM of 5 words × 8 bits when the number of input data is 8, the delay time to be added is 10 clock cycles, and the number of changes of input data within the additional delay time is 5 times or less. A specific circuit example of the digital delay circuit of the present invention configured using the above will be shown.
[0020]
Input data input via the input terminal 1 is input to the data input terminals of DFFs (D-type flip-flops) 8-1 to 8-8 and the change point detection circuit 3. The input data S4 retimed by the DFFs 8-1 to 8-8 is input to the write data input WD of the 2-port RAM 7. The change check circuit 3 compares the current input data value with the input data value input one cycle before the clock by the DFFs 301-1 to 301-8 and the comparison circuit 302, and outputs the change information S2. The change point information S2 is input to the write control circuit 5 and the delay circuit 4.
[0021]
The write control circuit 5 includes a counter 501 and a clock generation circuit 502, and outputs a write address S5 and a write clock S6 to the 2-port RAM 7 based on the change point information S2.
[0022]
The delay circuit 4 includes an 8-bit shift register 401, and outputs change point information S3 obtained by delaying input change point information S2 by 8 clock cycles. The read control circuit 6 includes a counter 601 and a clock generation circuit 602, and outputs a read address S7 of the 2-port RAM 7 and a read clock S8 based on the change point information S3.
[0023]
Data output from the read data output 2 of the 2-port RAM 7 is output data. The clock (CLK) input from the input terminal 9 is input to the clock inputs of the DFFs 8-1 to 8-8, the change point detection circuit 3, the delay circuit 4, the write control circuit 5, and the read control circuit 6. An initialization reset signal (RST) input from the input terminal 10 is input to the change point detection circuit 3, the delay circuit 4, the write control circuit 5, and the read control circuit 6.
[0024]
Next, a specific configuration example of the comparison circuit 302 used in the change point detection circuit 3 of FIG. 2 will be described with reference to FIG. The comparison circuit 302 includes EXORs 302-1 to 302-8 and an 8-input OR 302-9. If the data values of the inputs A and B to the EXOR gate do not match, “Hi” is output from the output terminal Y, and if they match, “Lo” is output from the output terminal Y. Therefore, in the change point information S2 in FIG. 2, “Hi” is output when the input data input via the input terminal 1 changes, and “Lo” is output when there is no change. The
[0025]
FIG. 4 shows a circuit example of the clock generation circuits 502 and 602 used in the write control circuit 5 and the read control circuit 6 of FIG. In FIG. 4, the clock generation circuit includes a DFF 11, an inverter 12, and an OR 13. When the input EN is “Hi”, the clock input to the input CLKIN is output to the output terminal CLKOUT of the OR gate 13, and when the input EN is “Lo”, “Hi” is output. . Accordingly, the write clock S6 and the read clock S8 of the 2-port RAM 7 in FIG. 2 are given clocks input via the input terminal 9 only when the change point information S2 and S3 are “Hi”.
[0026]
The operation of the digital delay circuit in FIG. 2 will be described with reference to the timing chart in FIG. When the reset signal (RST) “Lo” is input to the RST input terminal 10 at time 0, the counter 501 of the write control circuit 5 and the counter 601 of the read control circuit 6 are initialized, and the write address S5 of the 2-port RAM 7 The initial address 0 is given to the read address S7. When data D1 to D10 are input to the input terminal (DIN) 1 at the time interval shown in FIG. 5 at time 2, the change point detection circuit 3 detects the input data value and the input data value one cycle before the clock at each time. In the case of a mismatch, “Hi” is output, so the change point information S2 becomes “Hi” between time 2 and time 12 to 16. Since the delay circuit 4 adds a delay of 8 clock cycle times to the change point information S2, the change point information S3 becomes “Hi” between the times 10 and 14 and between the times 20 and 24.
[0027]
The counter 501 of the write control circuit 5 increments the count value using a clock when the change point information S2 is “Hi”, and writes the write data (WA) for storing the input data D1 to D10 in the 2-port RAM 7. S5 is generated. The clock control circuit 502 of the write control circuit 5 generates a write clock (WCLK) S6 for storing the input data D1 to D10 at the write address S5 when the change point information S2 is “Hi”. Accordingly, the writing process of the input data D1-5 between the times 3 and 7 and the writing process of the input data D6-10 between the times 13 and 17 are performed on the 2-port RAM 7.
[0028]
When the change point information S3 is “Hi”, the counter 601 of the read control circuit 6 uses a clock to increment the count value and read the data D1 to 10 stored in the 2-port RAM 7 (RA) S7 is generated. When the change point information S3 is “Hi”, the clock generation circuit 602 of the read control circuit 6 generates a read clock (RCLK) S8 for reading the data D1 to D10 from the read address S7. Accordingly, the data D1-5 are read from the time 11 to 15 for the 2-port RAM 7, and the data D6-10 are read from the time 21 to 25, and the clock 10 Data to which a cycle time delay is added can be obtained.
[0029]
The configuration and operation of the preferred embodiment of the digital delay circuit of the present invention have been described in detail above. However, this embodiment is merely an example, and it will be understood that various modifications and changes can be made according to a specific application. Of course, these modifications are also included in the present invention.
[0030]
【The invention's effect】
As understood from the above description, according to the digital delay circuit of the present invention, the circuit scale can be suppressed even if the additional delay amount is increased. The reason for this is that the change inspection output circuit detects only when there is a change in the input data and stores the new data in the 2-port RAM. This is because the number of words in the 2-port RAM can be reduced as the number of changes in input data decreases (because it does not depend directly on the delay time), depending on the number of changes in input data in between.
[0031]
Further, according to the present invention, power consumption can be suppressed even if the additional delay amount is increased. The reason is that, as described above, the number of words in the 2-port RAM can be reduced, and the writing and reading processing for the 2-port RAM is limited to the case where the input data and the output data change, respectively.
[Brief description of the drawings]
FIG. 1 is a block diagram of an exemplary embodiment of a digital delay circuit of the present invention.
FIG. 2 is a specific circuit diagram of the digital delay circuit shown in FIG.
3 is a circuit diagram showing a configuration example of a comparison circuit used in the digital delay circuit shown in FIG. 2;
4 is a specific circuit diagram of a clock generation circuit used in the digital delay circuit shown in FIG. 2. FIG.
FIG. 5 is a timing chart for explaining the operation of each part of the digital delay circuit shown in FIG. 2;
FIG. 6 is a configuration diagram of a conventional digital delay circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Data input terminal 2 Data output terminal 3 Change point detection circuit 4 Delay circuit 5 Write control circuit 6 Read control circuit 7 2 port RAM
302 Comparison circuit 401 Shift register 501, 601 Counter 502, 602 Clock generation circuit

Claims (4)

In a digital delay circuit for storing input data in a 2-port RAM and reading out the input data stored in the 2-port RAM after an arbitrary time and using it as output data,
A change point detection circuit for obtaining change point information of the input data;
A write control circuit having a counter and a clock generation circuit, and writing the changed input data into the 2-port RAM based on the change point information of the change point detection circuit;
A digital delay circuit comprising: a counter and a clock generation circuit; and a read control circuit for reading data stored in the two-port RAM through a delay circuit for delaying the change point information.   The digital delay circuit according to claim 1, wherein a shift register is used as the delay circuit.   3. The digital delay circuit according to claim 1, wherein a DFF and a comparison circuit are used as the change point detection circuit. 4. The digital delay circuit according to claim 1 , wherein each of the write control circuit and the read control circuit includes a clock generation circuit including a counter, a DFF, an inverter, and an OR gate .

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