JP3667907B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a trench type power semiconductor device.
[0002]
[Prior art]
Hereinafter, a method of manufacturing a semiconductor device according to a conventional example will be described with reference to FIGS. 7 to 12 are cross-sectional views for explaining a conventional method of manufacturing a power MOSFET having a so-called trench structure.
First, as shown in FIG. 7, an n @-type drain layer 1B is formed on the surface layer of a semiconductor substrate 1A made of n @ + type silicon, and a p @ + type channel layer 1C is formed on the surface layer. Further, an oxide film 3 is formed on the channel layer 1C, and an n + type impurity is selectively implanted and diffused to form the source region 2. Thereafter, the oxide film 3 near the source region 2 and the semiconductor substrate 1 are selectively etched to form a trench 4.
[0003]
Next, as shown in FIG. 8, the entire surface is thermally oxidized to form an oxide film 5 on the inner wall of the trench 4.
Next, as shown in FIG. 9, a polysilicon layer 6 is formed on the entire surface and filled into the trench 4, and then the entire surface is etched back to remove the polysilicon layer 6 on the substrate surface. As shown, the gate electrode 7 filled in the trench 4 and the extraction electrode pad 8 are formed simultaneously.
[0004]
Next, as shown in FIG. 11, an interlayer insulating film 9 made of an oxide film or the like is formed on the entire surface by CVD to cover the gate electrode 7 and the extraction electrode pad 8, and then in a part of the source region 2. The interlayer insulating film 9 is removed, and a metal wiring layer 10 that makes contact with the source region 2 is formed as shown in FIG.
[0005]
[Problems to be solved by the invention]
According to the above manufacturing method, in order to eliminate the depression of the polysilicon layer 6 on the trench 4, it is necessary to stack the polysilicon layer 6 by about 1.5 μm under normal conditions. Since the step d shown is also as large as 1.5 μm, the step coverage is deteriorated by this step, and the breakdown voltage at the step portion is lowered, or the metal wiring layer 10 formed thereon is disconnected. It becomes a cause.
[0006]
Furthermore, it is necessary to deposit an interlayer insulating film by a CVD method, and the number of processes has increased.
[0007]
[Means for Solving the Problems]
The present invention has been made in view of the above-described conventional drawbacks. As shown in FIG. 1, a step of forming a groove in a semiconductor substrate, and a conductor layer filling the groove and covering the entire surface of the semiconductor substrate are provided. Forming a mask, selectively forming a mask in a region where a pad is to be formed, etching back the conductor layer to a thickness approximately half the thickness of the conductor layer, and thermally oxidizing the conductor layer. And a step of forming an interlayer insulating film that electrically separates the conductor layer filled in the trench from the conductor layer remaining in the pad region. The above-mentioned problems are solved.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a power MOSFET having a trench structure according to an embodiment of the present invention will be described with reference to the drawings. 1 to 6 are cross-sectional views illustrating a method for manufacturing a power MOSFET according to this embodiment.
First, as shown in FIG. 1, an n @-type drain layer 11B is formed by epitaxial growth on the surface layer of a semiconductor substrate 11A made of n @ + type silicon, and a p @ + type channel layer 11C is formed on the surface layer. Further, a silicon oxide film 13 is formed on the channel layer 11C, and arsenic (As +), which is an N + type impurity, is selectively implanted and diffused into the surface layer of the channel layer under the condition of a dose amount of 6 × 10 13 cm −1. The source region 12 is formed. Thereafter, the silicon oxide film 13 and the semiconductor substrate 11 in the vicinity of the source region 12 are selectively dry etched to form a trench 14 having a width of 1 μm and a depth of 1.5 to 3 μm, preferably about 2 μm.
[0009]
Next, as shown in FIG. 2, the entire surface is thermally oxidized to form a silicon oxide film 15 having a thickness of about 500 mm on the inner wall of the trench 14. This silicon oxide film becomes a gate insulating film in the power MOSFET of this embodiment.
Next, as shown in FIG. 3, a polysilicon layer 16 having a thickness of about 1.5 μm is formed on the entire surface so as to fill the trench 14 and cover the entire surface of the semiconductor substrate 11.
[0010]
Next, a photoresist PR is selectively formed in a region (hereinafter referred to as a pad region) where an extraction electrode pad is to be formed later. As shown in FIG. 4, the polysilicon layer 16 has a thickness of about 0.5 μm or less. The polysilicon layer 16 is etched back to such an extent that Therefore, the level difference d ′ between the polysilicon remaining in the pad region at this time and the surface of the etched back polysilicon layer 16 is about 0.5 μm.
[0011]
Next, after the photoresist PR is peeled off, the polysilicon layer 16 is thermally oxidized under a condition that a thermal oxide film of about 6000 mm is formed, specifically, for example, a steam oxidation condition at about 1100 ° C. for 20 minutes. Then, the surface of the polysilicon layer 16 is oxidized to form a silicon oxide film, but the polysilicon layer inside the trench 14 is not oxidized and maintains the state of polysilicon.
[0012]
In addition, since the formation area of the extraction electrode pad is not etched back, the film thickness is about 1.5 μm. The surface is oxidized, but the inside is not oxidized, and the polysilicon is only about half the thickness from the bottom. The state of is maintained.
Thus, as shown in FIG. 5, polysilicon remains in the trench 14 and in the pad region, and these polysilicons are electrically connected by the interlayer insulating film 17 made of an oxide film formed by oxidation of the polysilicon layer. Will be separated. Among these, the polysilicon remaining in the trench functions as the gate electrode 18 of the power MOSFET of this embodiment, and the polysilicon in the region where the extraction electrode pad is formed functions as the extraction electrode pad 19.
[0013]
Thereafter, the interlayer insulating film 17 in a part of the source region 12 is selectively removed by etching or the like to expose the source region 12, and then a wiring layer 20 made of metal such as aluminum is formed on the entire surface. By patterning, a trench type power MOSFET as shown in FIG. 6 is completed.
As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, when the gate electrode and the extraction electrode pad are formed at the same time, the polysilicon layer is completely removed by etch back and then separated. Without taking the step of forming an interlayer insulating film by the CVD method, the polysilicon layer 16 is etched back to about half the thickness as shown in FIG. 4, and then the entire surface is thermally oxidized as shown in FIG. As a result, the gate electrode 18 and the extraction electrode pad 19 are formed at the same time and the interlayer insulating film 17 is also formed at the same time. Therefore, the step d 'in the pad region can be reduced to about 1/3 as compared with the prior art. It becomes possible to reduce the degradation of step coverage, the breakdown voltage drop, or the disconnection of the metal wiring layer formed thereon, which has been a problem.
[0014]
In addition, since the interlayer insulating film is formed at the same time in the formation process of the gate electrode and the like, the number of processes can be reduced as compared with the conventional method in which the interlayer insulating film is formed separately by the CVD method, etc. The manufacturing cost can be reduced.
In this embodiment, the thickness of the polysilicon layer 16 is 1.5 μm, and the thickness after etching back is 0.5 μm. However, the present invention is not limited to these values, and these values are changed. However, if the film thickness after the etch back is about half the original film thickness, the same effect can be obtained.
[0015]
Further, in the present embodiment, a method for manufacturing a power MOSFET having a trench structure is described. However, the present invention is not limited to this, and an electrode such as polysilicon is embedded in the trench, and at the same time, a substrate surface in the vicinity thereof is formed. As long as it is used to form an electrode pad, the same effect can be obtained in almost any case, and it can be applied to an IGBT (insulated gate bipolar transistor) having a trench structure. Absent.
[0016]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device according to the present invention, after the polysilicon layer is etched back to about half the film thickness, the entire surface is thermally oxidized to simultaneously form the gate electrode and the extraction electrode pad. Since the interlayer insulating film is also formed at the same time, the step in the electrode pad can be reduced as compared with the prior art. It is possible to reduce the disconnection of the metal wiring layer.
[0017]
In addition, by forming the interlayer insulating film at the same time, the number of processes can be reduced as compared with the conventional method in which the interlayer insulating film is separately formed by the CVD method, etc. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 3 is a third cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention.
FIG. 4 is a fourth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 5 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 6 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 7 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.
FIG. 8 is a second cross-sectional view illustrating the manufacturing method of the semiconductor device according to the conventional example.
FIG. 9 is a third cross-sectional view illustrating the manufacturing method of the semiconductor device according to the conventional example.
FIG. 10 is a fourth cross-sectional view illustrating the manufacturing method of the semiconductor device according to the conventional example.
FIG. 11 is a fifth cross-sectional view illustrating the manufacturing method of the semiconductor device according to the conventional example.
FIG. 12 is a sixth cross-sectional view illustrating the manufacturing method of the semiconductor device according to the conventional example.

Claims (4)

Forming a groove in the semiconductor substrate;
Forming a conductor layer that fills the groove and covers the entire surface of the semiconductor substrate;
Selectively forming a mask in a pad region where an electrode pad is to be formed, and etching back the conductive layer to a film thickness approximately half the thickness of the conductive layer;
And a step of thermally oxidizing the conductor layer to form an interlayer insulating film that electrically separates the conductor layer filled in the groove and the conductor layer remaining in the pad region. A method for manufacturing a semiconductor device.   2. The semiconductor device according to claim 1, wherein a polysilicon layer is formed in the step of forming the conductor layer, and an interlayer insulating film made of a silicon oxide film is formed in the step of forming the interlayer insulating film. Production method. Forming a drain region layer of one conductivity type on a surface layer of a semiconductor substrate of one conductivity type, and forming a channel region layer of reverse conductivity type on the surface layer of the drain region layer;
Forming a first insulating film on the surface of the semiconductor substrate and diffusing an impurity of one conductivity type in the channel region layer to form a source region;
Selectively etching the first insulating film and the semiconductor substrate in a region near the source region to form a groove, and forming a second insulating film on the inner wall of the groove;
Forming a conductor layer that fills the groove and covers the entire surface of the semiconductor substrate;
Selectively forming a mask in a pad region, which is a region for forming an extraction electrode pad, and etching back the conductor layer to a thickness of about half of the thickness of the conductor layer;
The conductive layer is thermally oxidized to form an interlayer insulating film that electrically separates the conductive layer filled in the groove and the conductive layer remaining in the pad region, and the conductive filled in the groove Using the body layer as a gate electrode and the conductor layer in the pad region as an extraction electrode pad;
And a step of selectively removing a part of the interlayer insulating film in the source region to expose the source region and forming a wiring layer in contact with the source region. Method. 4. The semiconductor device according to claim 3 , wherein a polysilicon layer is formed in the step of forming the conductor layer, and an interlayer insulating film made of a silicon oxide film is formed in the step of forming the interlayer insulating film. Production method.

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