JP3668122B2 - Thin film transistor substrate and liquid crystal display device including the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor substrate and a liquid crystal display device including the same.
[0002]
[Prior art]
In a thin film transistor array substrate constituting a liquid crystal display device, one using a pixel electrode as one electrode for forming an auxiliary capacitor and a gate wiring as the other electrode is known (for example, Japanese Patent Laid-Open No. 1-169430). See the official gazette). In order to increase the auxiliary capacitance, it is effective to increase the area where the pixel electrode and the gate wiring overlap, but there is a limit from the relationship with the aperture ratio. Therefore, as shown in FIG. 4, an auxiliary capacitor electrode CM is separately provided between the gate insulating layer and the protective layer thereon, and the contact hole CH in which the electrode CM and the pixel electrode ITO are formed in the protective layer is provided. A structure in which the auxiliary capacity is increased by connection is put into practical use.
[0003]
[Problems to be solved by the invention]
In the conventional structure shown in FIG. 4, the contact hole CH is also formed over the entire area where the pixel electrode ITO faces the adjacent pixel electrode via the gate wiring GL, particularly over the gate wiring GL away from the thin film transistor TFT. Since the pixel electrode ITO is formed so as to cover it, the interval between the pixel electrodes ITO is very narrow, and there is a problem that a short circuit accident of the pixel electrode is liable to occur when foreign matter enters the gap portion.
[0004]
Accordingly, an object of the present invention is to prevent the occurrence of a short-circuit accident between pixel electrodes facing each other across a gate wiring. Another object is to increase the auxiliary capacity without sacrificing the aperture ratio. Another object is to provide a liquid crystal display device with high image quality.
[0005]
[Means for Solving the Problems]
According to the thin film transistor substrate of the present invention, the thin film transistor and the pixel electrode connected to the thin film transistor are arranged in a region defined by the plurality of gate wirings and the plurality of source wirings, and the gate wiring is arranged to overlap the gate wiring. In a thin film transistor substrate having a gate insulating layer, an auxiliary capacitor electrode, and a protective layer interposed between the pixel electrodes of the next stage, the interval between the pixel electrode positioned with the gate electrode interposed therebetween and the pixel electrode of the next stage is widened. The contact hole formed in the protective layer to connect the pixel electrode and the auxiliary capacitor electrode so that the area where the pixel electrode of the next stage overlaps the auxiliary capacitor electrode is smaller on the side opposite to the thin film transistor than on the thin film transistor side. The thin film transistor is formed so as to be within a length range projected onto the gate wiring.
[0008]
According to a liquid crystal display device of the present invention, as described in claim 4, in the liquid crystal display device in which a liquid crystal layer is sandwiched between a pair of substrates, one of the above substrates is used as one of the substrates. It is characterized by that.
[0009]
By making the area where the pixel electrode of the next stage overlaps the auxiliary capacitor electrode smaller on the side opposite to the thin film transistor than on the thin film transistor side, the distance between the pixel electrodes is widened to prevent occurrence of a short circuit between the pixel electrodes. can do. Since the contact hole formed in the protective layer for connecting the pixel electrode and the auxiliary capacitor electrode is formed so as to be within the length range of the thin film transistor projected onto the gate wiring, the space between the pixel electrodes is reduced by the intervening thin film transistor. A contact hole and a pixel electrode covering the contact hole can be arranged in a region that can be secured widely. A liquid crystal display device including such a thin film transistor substrate on one substrate can perform display with improved display quality with less occurrence of a short circuit between pixel electrodes. Further, by arranging the auxiliary capacitor electrode so as to overlap the gate wiring, the storage capacity can be increased and the display quality can be improved without sacrificing the aperture ratio.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described by taking as an example a thin film transistor substrate (hereinafter referred to as TFT array) 2 in which inverted staggered thin film transistors (hereinafter referred to as TFT) 1 are arranged in a matrix. FIG. 1 is a schematic plan view of the TFT array 2. FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1, and is a schematic cross-sectional view of the main part (TFT 1). FIG. 3 is a plan view schematically showing a schematic structure of the TFT 1.
[0011]
In the TFT array 2, a plurality of gate wirings 4 extending in the left-right direction and a gate electrode 5 connected to the gate wiring 4 are formed on a substrate 3 such as non-alkali glass. A semiconductor island 7 is formed on the gate electrode 5 via a gate insulating layer 6 such as silicon nitride (SiNx). The semiconductor island 7 is formed of an amorphous silicon layer as a semiconductor layer that is connected to a source electrode 9 and a drain electrode 10 described later to form a channel region. After the formation of the semiconductor island 7, a plurality of source wirings 8 in a direction orthogonal to the gate wiring 4 (extending in the vertical direction), a source electrode 9 connected to the source wirings 8, and the source electrode 9 are arranged facing each other with a certain distance. A drain electrode 10, a contact electrode 11 with a pixel electrode connected to the base end of the drain electrode 10, and an auxiliary capacitance electrode 12 are formed. These wirings 8 to 12 are simultaneously formed by patterning the same metal layer, but can also be formed separately.
[0012]
The upper surface of the TFT array 2 including the semiconductor island 7, the source electrode 9, the drain electrode 10 and the like is covered with a protective layer (SiNx or the like) 13. A contact hole 14 reaching the contact electrode 11 and a contact hole 15 reaching the storage capacitor electrode 12 are formed in the protective layer 13. Transparent pixel electrodes 16 such as ITO and IZO are individually formed in regions partitioned by the gate wiring 4 and the source wiring 8. The pixel electrode 16 formed on the protective layer 13 is connected to the drain electrode 10 of the TFT 1 through the contact hole 14 and is connected to the storage capacitor electrode 12 through the contact hole 15.
[0013]
Most of the gate insulating layer 6 and the protective layer 13 located under the pixel electrode are removed except for the portion that insulates the pixel electrode 16 from the electrode and wiring located thereunder. Most of the pixel electrodes 16 are in direct contact with each other. In this way, the amount of transmitted light can be increased by removing the insulating layer and the protective layer located under the pixel electrode 16. Further, since the pixel electrode 16 has a notch corresponding to the TFT 1 at the corner in order to avoid the planar overlap with the light-shielding gate electrode 5, the pixel electrode 16 and the next adjacent to the pixel electrode 16 are provided. A gap corresponding to the TFT 1 is interposed between the pixel electrode 16 in the stage.
[0014]
The pixel electrode 16 is disposed adjacent to the TFT 1. However, when an interlayer insulating layer covering the TFT 1 is formed, the pixel electrode 16 may be disposed so as to overlap most of the TFT 1 in plan view. The TFT 1 and the pixel electrode 16 connected to the TFT 1 are both arranged in a matrix. The pixel electrode 16 can also be formed of a reflective metal film or the like when the display device is of a reflective type.
[0015]
The source electrode 9 has a horizontally long shape in a direction orthogonal to the source wiring 8 and is formed at a position overlapping the gate electrode 5 and the semiconductor island 7 in a plane. On the side of the source electrode 9 facing the drain electrode 10, a semicircular recess 9 a that receives the tip 10 a of the drain electrode 10 is formed. The drain electrode 10 disposed so as to overlap the gate electrode 5 and the semiconductor island 7 in plan view has a vertically long shape extending in the same direction as the extension direction of the source wiring 8, and the extension of the source wiring 8 with reference to the source electrode 9. It is arranged in the same direction as the direction. By fitting the arcuate tip 10a of the drain electrode 10 into the recess 9a of the source electrode 9, the periphery of the tip of the drain electrode 10 and the source electrode 9 are maintained at a constant interval (channel width).
[0016]
A portion where the source electrode 9 and the drain electrode 10 overlap with the gate electrode 5 in plan view with the gate insulating layer 6 and the semiconductor island 7 interposed therebetween mainly constitutes the parasitic capacitance of the TFT 1. It is a parasitic capacitance formed by the overlap between the drain electrode 10 and the gate electrode 5. The structure shown in FIG. 3 is a structure that suppresses variations in the parasitic capacitance between the gate and the drain.
[0017]
First, since the source electrode 9 and the drain electrode 10 simultaneously formed of the same metal are arranged in the vertical direction, the parasitic capacitance between the gate and the drain does not change even if the electrode arrangement is slightly shifted in the horizontal direction. In addition, when the vertical displacement occurs, the overlapping area of the drain electrode 10 and the gate electrode 5 changes in size. However, since the drain electrode 10 is vertically long, when a horizontally long portion is overlapped on the gate electrode 5 like the contact electrode 11. In comparison, the fluctuating area can be made very small. Here, since the drain electrode 10 is vertically long, the channel width may be shortened. However, the recess 9a is provided in the source electrode 9, and the source electrode 9 surrounds the periphery of the distal end portion 10a of the drain electrode 10 with a certain interval. Because of the shape, the channel width can be secured relatively wide.
[0018]
As described above, since the distal end portion 10a of the drain electrode 10 is disposed in the recess 9a of the source electrode 9, fluctuations in parasitic capacitance of the TFT 1 can be suppressed.
[0019]
Therefore, when providing the liquid crystal display device by incorporating the TFT array 2 on one of the substrates opposed to each other with the liquid crystal layer interposed therebetween, it is possible to perform display while suppressing display unevenness due to variations in the parasitic capacitance of the TFT 1. Further, when the auxiliary capacitor for suppressing the influence due to the fluctuation of the parasitic capacitance is provided in the TFT 1, the capacitance can be set small, and the light shielding area by the auxiliary capacitor can be reduced to increase the aperture ratio of the liquid crystal display device. Can do.
[0020]
The shape of the tip portion 10a of the drain electrode 10 is formed using a pattern set in advance so as to round the corner. In this rounding of the corners, it is desirable to set the radius to a value larger than the resolution of the exposure apparatus, so that the difference between the design shape and the actual shape can be reduced. In this embodiment, the tip end portion 10a of the drain electrode 10 is convex toward the source electrode 9 side and has an arc shape when viewed in plan. This tip shape is the same as the original design pattern. Accordingly, it is possible to solve the problem of the fluctuation of the area of the drain 10 electrode due to rounding of the corner and the fluctuation of the parasitic capacitance due to the rounding as in the case of the square or the problem of the fluctuation of the distance between the source electrode 9 and the drain electrode 10.
[0021]
The source electrode 9 also has a concave portion 9a in an arc shape. That is. In order to make the distance between the source and drain electrodes constant, a concave arcuate recess 9a is provided on the side of the source electrode 9 facing the drain electrode 10 when viewed in plan. The arc shape of the recess 9a is formed to be concentric with the arc shape of the distal end portion 10a of the drain electrode 10. Thus, since the concave portion 9a is also formed in an arc shape concentric with the drain electrode tip 10a, the source-drain distance, that is, the channel length of the TFT 1 can be kept constant, and the transistor characteristics can be improved. The side 9b opposite to the side opposite to the drain electrode 10 of the source electrode 9 may have an arbitrary shape, but in this example, it is formed concentrically with the arc of the drain electrode tip 10a, like the recess 9a. Thus, in the embodiment shown in the figure, the tip 10a of the drain electrode 10 facing the source electrode 9, the side 9a of the source electrode 9 facing the drain electrode 10, and the side 9b of the source electrode 9 opposite to the drain electrode 10 are provided. Are formed concentrically in a plan view so that their radii are successively increased. Here, the concentric arc shape can include an elliptical shape in addition to a circle.
[0022]
The above-described rounding process in which rounding is performed in advance with a radius larger than the exposure resolution has the highest degree of influence on the parasitic capacitance and channel state of the TFT 1, particularly the tip on the side facing the source electrode 9. Although it is preferable to apply to the part 10a and the recessed part 9a of the source electrode 9 facing this tip part, it can also be applied to other parts, for example, the contact electrode 11, the connection between the contact electrode 11 and the drain electrode 10. It can also be applied to the connection portion between the source electrode 9 and the source wiring 8, the gate electrode 5, the connection portion between the gate electrode 5 and the gate wiring 4, the pixel electrode 16, and the like.
[0023]
The auxiliary capacitance electrode 12 is laminated on the gate insulating layer 6 in a state where there is almost no protrusion from the gate wiring 4 when viewed in plan. The length of the auxiliary capacitor electrode 12 is set to be substantially the same as the length of the pixel electrode 16 in the short side direction (the length in the same direction as the gate wiring 4).
[0024]
More preferably, the contact hole 15 formed in the protective layer 13 is within a projection length range of half or less when the pixel electrode 16 is projected onto the gate wiring 4, and more preferably, the TFT 1 is connected to the gate wiring as in this example. 4 so as to be within the projection length range when projected onto 4, or within the projection length range when the gate electrode 5 is projected onto the gate wiring 4, or the source electrode 9 to the gate wiring 4. It is preferable that the contact length is within the projected length range when projected, or within the projected length range when the contact electrode 11 is projected onto the gate wiring 4. Thus, in the structure in which the gate insulating layer 6, the auxiliary capacitor electrode 12, and the protective layer 13 are arranged between the gate electrode 5 and the pixel electrode 16, the contact hole is located at a position biased toward the TFT 1 side on the auxiliary capacitor electrode 12. 15 is formed, the degree of design freedom of the pixel electrode 16 on the side opposite to the contact hole 15 is increased, the pixel electrode interval can be set wide, and a structure useful for preventing a short circuit between the electrodes 16 is provided. Can do.
[0025]
The adjacent (next stage) pixel electrode 16 on the gate wiring 4 covers the contact hole 15, while the auxiliary capacitance electrode is provided on the side opposite to the side on which the contact hole 15 is formed on the auxiliary capacitance electrode 12. 12 has a cutout portion 16a that is exposed from the edge of the pixel electrode 16 when viewed in plan. The notch 16a serves to widen the interval between the portions where the pixel electrode 16 is opposed to the next-stage pixel electrode 16 with the gate wiring 4 interposed therebetween, in particular, the interval where the TFT is not interposed between the pixel electrodes 16. Therefore, it is possible to prevent the occurrence of a short circuit between adjacent pixel electrodes and the accompanying deterioration in display quality.
[0026]
Due to the presence of the notch 16a, the area where the adjacent pixel electrode 16 adjacent to the auxiliary capacitor electrode 12 overlaps on the side opposite to the TFT 1 is smaller than the TFT 1 side, and the overlapping area of the pixel electrode 16 as a whole is reduced. Although the amount of auxiliary capacitance is reduced, the majority of the auxiliary capacitance is defined by the area of the auxiliary capacitance electrode 12, so that the influence of the notch 16a on the auxiliary capacitance is very small.
[0027]
The TFT array 2 is used for a display device using a transistor for driving a display pixel, for example, a liquid crystal display device in which liquid crystal is sandwiched between two substrates or an organic or inorganic type EL display device. be able to. Further, although the above embodiment has been described by taking an example of an inverted staggered TFT using amorphous silicon, a part of the structure of the present invention can be applied to other transistors. The present invention can also be applied to a transistor using crystalline silicon as a semiconductor island and a transistor using the transistor.
[0028]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent the occurrence of a short circuit accident between pixel electrodes facing each other with a gate wiring interposed therebetween. Further, since the auxiliary capacitance electrode is provided, the auxiliary capacitance can be set large without sacrificing the aperture ratio. As a result, a liquid crystal display device with high image quality can be provided.
[Brief description of the drawings]
FIG. 1 is a plan view showing a schematic structure of a TFT array for explaining an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view along AA in FIG.
FIG. 3 is a plan view schematically showing a schematic structure of a TFT according to an embodiment of the present invention.
FIG. 4 is a plan view schematically showing a schematic structure of a conventional TFT.
[Explanation of symbols]
1 TFT
2 TFT array 5 Gate electrode 7 Semiconductor island 9 Source electrode 10 Drain electrode 12 Auxiliary capacitance electrode 13 Protective layer 14 Contact hole 15 Contact hole 16 Pixel electrode 16a Notch

Claims (2)

A thin film transistor and a pixel electrode connected to the thin film transistor are arranged in a region partitioned by a plurality of gate wirings and a plurality of source wirings, and a gate insulating layer and an auxiliary capacitor are arranged between the gate wiring and the next pixel electrode arranged so as to overlap with the gate wiring. In the thin film transistor substrate with the electrode and the protective layer interposed therebetween , the next-stage pixel electrode serves as the auxiliary capacitor electrode so as to widen the distance between the pixel electrode located between the gate electrode and the next-stage pixel electrode. The overlapping area is smaller on the side opposite to the thin film transistor than on the thin film transistor side, a contact hole formed in the protective layer for connecting the pixel electrode and the auxiliary capacitance electrode, and the thin film transistor is connected to the gate wiring. A thin film transistor substrate, wherein the thin film transistor substrate is formed so as to be within a length range projected onto the substrate. 2. A liquid crystal display device having a liquid crystal layer sandwiched between a pair of substrates, wherein the substrate according to claim 1 is used as one of the substrates.

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