JP3670543B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device suitable for a solid-state imaging device that reads a document in close contact.
[0002]
[Prior art]
Solid-state imaging devices include a type that implements a color image using a plurality of blinking light sources in addition to a type that reads a color image using a color filter. In addition, when reading an image from a document, there are a type that reads a reduced image using a lens, and a type that reads a document at a full size by closely contacting the document.
[0003]
FIG. 3A shows the configuration of a contact type conventional solid-state imaging device using flashing light sources of R, G, and B colors, and FIG. 3B shows the waveform of the transfer clock applied to the transfer electrode. FIG. 4 shows a time chart regarding the lighting timing of the blinking light source and the waveform of the drive pulse.
[0004]
Pixels PE1, PE2,... Are arranged in the left-right direction (horizontal direction) in the drawing. As shown in FIG. 4, the three-color blinking light sources LED (B), LED (G), and LED (R) are sequentially supplied with power in the form of pulses to emit light. In each of the pixels PE1, PE2,..., When the flashing light sources LED (B), LED (G), and LED (R) are turned on, signal charges corresponding to the three colors R, G, and B are generated and temporarily held. Is done.
[0005]
A shift gate SH is provided between the pixels PE1, PE2,... And the horizontal transfer register HTR. The transfer pulse SH is supplied to the shift gate SH as shown in FIG. This transfer pulse SH is given after each of the blinking light sources LED (B), LED (G), and LED (R) is turned on. As a result, signal charges generated in the pixels PE1, PE2,... Are accumulated in the impurity layers below the transfer electrodes HTR12, HTR22,. Then, signal charges are transferred in the direction of arrow A in accordance with the timing of the two-phase transfer clocks Φ1 and Φ2. Then, it is converted into a voltage signal OS corresponding to each signal charge amount and read out at an output section (not shown).
[0006]
[Problems to be solved by the invention]
However, the conventional solid-state imaging device has the following problems. In a document-contact type solid-state imaging device, since a document is read at almost the full size, the pixel pitch is longer than that of a type in which the document is reduced and read using a lens. In such an apparatus, the transfer length of each pixel PE1, PE2,. Therefore, when the horizontal transfer register HTR is driven with a two-phase pulse, the transfer time becomes long because the charge transfer distance per stage is long.
[0007]
Therefore, as shown in FIG. 3B, for each transfer electrode HTR11, HTR12,..., By changing the number of impurity implantations in the impurity region below it, three or more multi-stage barrier steps are formed. doing. Thereby, the execution length of transfer per stage is shortened, and as a result, the transfer speed is improved.
[0008]
However, when a multi-stage barrier step is formed in the register due to the recent decrease in power supply voltage and pulse voltage, the transfer step P between the transfer electrodes HTR11 and HTR12, HTR12 and FTR21,... Shown in FIG. It becomes difficult to ensure. Therefore, there are cases where high-speed transfer due to multi-level barrier steps cannot be realized.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of simultaneously realizing a reduction in power supply voltage and pulse voltage and high-speed transfer of signal charges.
[0010]
[Means for Solving the Problems]
The solid-state imaging device of the present invention is
a flashing light source of n (n is an integer of 2 or more),
A plurality of pixels arranged in a first direction and irradiated with light from the flashing light source to perform photoelectric conversion and generate signal charges;
An accumulation gate for receiving and accumulating the signal charge generated in the pixel, the n accumulation gates being arranged in a second direction for each pixel;
A transfer register that receives the signal charge stored in the storage gate and sequentially transfers the signal charge in the first direction;
A shift gate disposed between the storage gate and the transfer register and transferring each of the signal charges stored in the storage gate to the transfer register;
With
The transfer register has n * m transfer electrodes per pixel when a transfer clock of m (m is an integer of 2 or more) phase is given.
The signal charge generated in the pixel is transferred in the second direction by the storage gate, supplied to the transfer register through the shift gate, and then transferred in the first direction.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0014]
FIG. 1A shows the configuration of the solid-state imaging device according to this embodiment, and FIG. 1B shows the waveforms of the two-phase transfer pulses Φ1 and Φ2 applied to the transfer electrodes in this device.
[0015]
A plurality of pixels PE1, PE2,... Are arranged in the left-right direction (horizontal direction) in the drawing. Between the pixels PE1, PE2,... And the horizontal transfer register HTR, a plurality of storage gates SG11 to SG13 and a shift gate SH11, storage gates SG21 to SG23 and a shift gate SH21,. They are arranged in the (vertical direction). Here, the number of storage gates SG11 to SG13, SG21 to SG23 provided for each of the pixels PE1, PE2,... Is the same as the number of colors of the blinking light source.
[0016]
In the horizontal transfer register HTR, six pixel electrodes HTR11 to HTR16 and HTR21 to HTR26 are arranged for each pixel PE1, PE2,.
[0017]
Regarding the operation of the solid-state imaging device according to the present embodiment having such a configuration, the lighting timing of the blinking light source, the gate pulse of the storage gates SG21 to SG23, the gate pulse of the shift gate SH, and the time chart of the transfer clock Φ1 are shown. This will be described with reference to FIG.
[0018]
As shown in FIG. 2, among the three-color blinking light source LEDs (B), LED (G), and LED (R), the blinking light source LED (B) is turned on in a pulsed manner from the time t1 to the time t2. Supplied to emit light. In the pixels PE1, PE2,..., The blinking light source LED (B) is lit, whereby a signal charge corresponding to the B color is generated and temporarily held.
[0019]
The gate pulses SG (R) are applied to the R color storage gates SG11, SG21,... From time t2 to t3, and the signal charges (B) generated by the light emission of the LEDs (B) are converted into the pixels PE1, PE2, Are transferred to the storage gates SG11, SG21,.
[0020]
A gate pulse SG (G) is applied to the G color storage gates SG12, SG22,... From time t3 to t4, and the signal charge (B) generated by the light emission of the LED (B) is stored in the storage gate pixels SG11, Transfer from SG21,... To storage gates SG12, SG22,.
[0021]
A gate pulse SG (B) is applied to the B color storage gates SG13, SG23,... From time t4 to t5, and the signal charge (B) generated by the light emission of the LED (B) is stored in the storage gate pixels SG12, Transfer from SG22,... To storage gates SG13, SG23,.
[0022]
Next, the blinking light source LED (G) is supplied with power in a pulsed manner from time t5 to t6 to emit light. In the pixels PE1, PE2,..., A signal charge (G) corresponding to G color is generated and temporarily held.
[0023]
A gate pulse SG (R) is applied to the R color accumulation gates SG11, SG21,... From time t6 to t7, and the signal charges (G) are accumulated from the pixels PE1, PE2,. Forwarded to….
[0024]
The gate pulses SG (G) are applied to the G color accumulation gates SG12, SG22,... From time t7 to t8, and the signal charges (G) are accumulated from the accumulation gates SG11, SG21,. , ... transferred to.
[0025]
Further, the blinking light source LED (R) is supplied with power in pulses and emits light during the period from time t8 to t9. In the pixels PE1, PE2,..., Signal charges (R) corresponding to the R color are generated and temporarily held.
[0026]
The gate pulses SG (R) are applied to the R color accumulation gates SG11, SG21,... From time t9 to t10, and the signal charges (R) are accumulated from the pixels PE1, PE2,. Forwarded to….
[0027]
Next, during time t10 to t11, the gate pulse SH is given to the shift gates SH11, SH21,..., And the signal charge (B) accumulated in the accumulation gates SG13, SG23,. Transfer electrodes HTR16, HTR26,... Of the register HTR are transferred to the lower impurity layer. Two-phase transfer clocks Φ1 and Φ2 are applied to the transfer electrodes of the horizontal transfer register HTR, and are transferred in the direction of arrow A.
[0028]
From time t11 to t12, the gate pulse SG (B) is applied to the storage gates SG13, SG23,..., And the signal charges (G) stored in the storage gates SG12, SG22,. Forwarded to Further, during time t12 to t13, the gate pulse SG (G) is applied to the storage gates SG12, SG22,..., And the signal charges (R) stored in the storage gates SG11, SG21,. , ... transferred to.
[0029]
From time t13 to t14, the gate pulse SH is given to the shift gates SH11, SH21,..., And the signal charge (G) accumulated in the accumulation gates SG13, SG23,. Transfer electrodes HTR16, HTR26,... Are transferred to the lower impurity layer and transferred in the direction of arrow A.
[0030]
From time t15 to t16, the gate pulse SG (B) is applied to the storage gates SG13, SG23,..., And the signal charge (4) stored in the storage gates SG12, SG22,. Forwarded to
[0031]
From time t17 to t18, the gate pulse SH is given to the shift gates SH11, SH21,..., And the signal charge (R) accumulated in the accumulation gates SG13, SG23,. Transfer electrodes HTR16, HTR26,... Are transferred to the lower impurity layer and transferred in the direction of arrow A.
[0032]
In this way, the signal charge (B) generated in each pixel PE1, PE2,... Is temporarily accumulated in the accumulation gates SG11, SG21,..., And the signal charge (G) is accumulated in the accumulation gates SG12, SG22,. , Signal charges (R) are accumulated in the accumulation gates SG13, SG23,. The signal charge (B) is applied to the horizontal transfer register HTR via the shift gates SH11, SH21,..., The signal charge (G) is applied to the storage gates SG13, SG23,. The storage gates SG12, SG22,. The signal charge (G) is applied to the horizontal transfer register HTR via the shift gates SH11, SH21,..., And the signal charge (R) is applied to the storage gates SG13, SG23,. Then, the signal charge (R) is applied to the horizontal transfer register HTR via the shift gates SH11, SH21,. The signal charges given to the horizontal transfer register HTR are sequentially transferred at the timing of the transfer clocks Φ1 and Φ2, and are converted into voltage signals and output at an output unit (not shown).
[0033]
According to this embodiment, the number of transfer electrodes per pixel is six, and the transfer length of signal charges under one transfer electrode is shortened. As a result, the signal charge transfer rate can be increased. Further, in the conventional device, when a multi-stage barrier step is formed under one transfer electrode as shown in FIG. 3B, a transfer step P between registers is secured by lowering the power supply voltage and the pulse voltage. There was a problem that it was difficult to do. On the other hand, in this embodiment, the transfer length under each transfer electrode is shortened without providing a multi-level barrier step, so that the transfer rate can be increased even when the voltage is lowered.
[0034]
The above-described embodiment is an example and does not limit the present invention. For example, in the above-described embodiment, blinking light sources of R, G, and B colors are used, but the present invention can also be applied to an apparatus that includes blinking light sources of two colors or four colors or more. In this case, the storage gates are arranged in the same number as the number of colors of the blinking light source. In the above embodiment, a two-phase clock is supplied to the transfer register, but the present invention can also be applied to a device to which a transfer clock of three or more phases is supplied. In this case, the number of transfer electrodes obtained by multiplying the number of phases of the transfer clock by the number of colors of the blinking light source is arranged per pixel.
[0035]
【The invention's effect】
As described above, according to the present invention, when a signal charge generated in a pixel is transferred to a transfer register, it is configured to pass through a plurality of storage gates arranged between them, so that transfer per pixel is performed. By increasing the number of electrodes, the transfer length can be shortened, and as a result, the transfer speed can be increased.
[Brief description of the drawings]
FIG. 1 is a plan view and a time chart showing a configuration of a solid-state imaging device and a waveform of a transfer clock according to an embodiment of the present invention.
FIG. 2 is a time chart showing a waveform of a drive signal used in the solid-state imaging device.
FIG. 3 is a plan view and time chart showing a configuration of a conventional solid-state imaging device and a waveform of a transfer clock.
FIG. 4 is a time chart showing a waveform of a drive signal used in the solid-state imaging device.
[Explanation of symbols]
PE1, PE2 Pixels SG11, SG12, SG13, SG21, SG22, SG23 Storage gate SH11, SH21 Shift gate HTR Horizontal transfer registers HTR11-HTR16, HTR21-HTR26 Horizontal electrodes Φ1, Φ2 Transfer clock

Claims (1)

a flashing light source of n (n is an integer of 2 or more),
A plurality of pixels arranged in a first direction and irradiated with light from the flashing light source to perform photoelectric conversion and generate signal charges;
An accumulation gate for receiving and accumulating the signal charge generated in the pixel, the n accumulation gates being arranged in a second direction for each pixel;
A transfer register that receives the signal charge stored in the storage gate and sequentially transfers the signal charge in the first direction;
A shift gate disposed between the storage gate and the transfer register and transferring each of the signal charges stored in the storage gate to the transfer register;
With
The transfer register has n * m transfer electrodes per pixel when a transfer clock of m (m is an integer of 2 or more) phase is given.
A signal charge generated in the pixel is transferred in the second direction by the storage gate, applied to the transfer register through the shift gate, and then transferred in the first direction. Imaging device.

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