JP3672292B2 - Driving method of plasma display panel - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).
[0002]
[Prior art]
An AC (alternating discharge) type PDP is known as one of such matrix display type PDPs.
The AC-type PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs that are arranged orthogonally to the column electrodes and form one scan line as a pair. Each of these row electrode pairs and column electrodes is covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .
[0003]
At this time, since the PDP uses a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, the subfield method is used to realize halftone luminance display using such PDP. In the subfield method, a display period of one field is divided into N subfields, and a light emission period having a period length corresponding to the weighting of each bit digit of pixel data (N bits) is assigned to each subfield. The light emission is driven.
[0004]
FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus that performs halftone luminance display using such a subfield method.
In FIG. 1, a driving apparatus 100 converts an input video signal into digital pixel data corresponding to each pixel, and a pixel data pulse corresponding to this pixel data is converted to a column electrode D of the PDP 10.₁~ D_mApply to. The PDP 10 includes the column electrode D₁~ D_mA row electrode X that crosses each other and forms one row by a pair of X electrode and Y electrode₁~ X_nAnd Y₁~ Y_nIt has. Each of these column electrode and row electrode pairs is formed with a dielectric not shown in between, and one pixel cell is formed at a portion where one column electrode and row electrode pair intersect.
[0005]
FIG. 2 is a diagram showing a driving format in the one-field display period by the driving device 100. As shown in FIG.
As shown in FIG. 2, the display period of one field is divided into four subfields SF1 to SF4. In each subfield, the simultaneous reset process Rc, the pixel data writing process Wc, and the sustain light emission are performed. The process Ic and the erase process E are executed.
[0006]
FIG. 3 is a diagram showing application timings of various drive pulses applied by the driving device 100 to the column electrode and row electrode pair of the PDP 10 in each subfield so as to perform these various processes.
First, in the simultaneous reset process Rc, the driving device 100 performs the reset pulse RP as shown in FIG._xAnd RP_YRow electrode X₁~ X_nAnd Y₁~ Y_nApply to each simultaneously. These reset pulses RP_xAnd RP_YIn response to the application, all the discharge cells in the PDP 10 are reset and discharged, and a predetermined amount of wall charges are uniformly formed in each discharge cell. Thereby, all the discharge cells are temporarily set as light emitting cells.
[0007]
Next, in the pixel data writing process Wc, as shown in FIG. 3, the driving device 100 sequentially applies the pixel data pulse group DP for each row to the column electrode D.₁~ D_mApply to. For example, in the subfield SF1, only the first bit is extracted from each of the input pixel data corresponding to all the discharge cells of the PDP 10, and the pixel data pulse group DP corresponding to the logic level of the first bit is set to one row. Sequential column electrode D every minute₁~ D_mApply to. In the subfield SF2, only the second bit is extracted from each input pixel data corresponding to each of all the discharge cells of the PDP 10, and the pixel data pulse group DP corresponding to the logic level of the second bit is set to one row. Sequential column electrode D every minute₁~ D_mIt is applied to. At this time, the driving device 100 generates a high-voltage pixel data pulse and applies it to the column electrode D only when the logical level of the input pixel data is, for example, “1”. Further, the driving device 100 generates a scan pulse SP as shown in FIG. 3 at the same timing as the application timing of the pixel data pulse group DP, and generates the scan pulse SP as shown in FIG.₁~ Y_nApply sequentially to. Here, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining inside are selectively erased. Due to the selective erasing discharge, the discharge cell initialized to the light emitting cell state by the simultaneous reset process Rc is changed to a non-light emitting cell. It should be noted that no discharge occurs in the discharge cells formed in the “column” to which the high-voltage pixel data pulse is not applied, and the state initialized by the simultaneous reset process Rc, that is, the state of the light-emitting cells. Maintained.
[0008]
Further, in the pixel data writing process Wc, the driving device 100 applies a priming pulse PP as shown in FIG. 3 immediately before applying each scanning pulse SP to each row electrode Y.₁~ Y_nApply to. In response to the application of the priming pulse PP, priming discharge is generated for each row. Due to this priming discharge, charged particles that have been obtained by the simultaneous reset operation and have been reduced over time are re-formed in the discharge space of the PDP 10. Accordingly, since the scanning pulse SP is applied immediately after the charged particles are re-formed, the selective erasing discharge is surely generated, and the pixel data writing error is prevented.
[0009]
Next, in the sustain light emission process Ic, the driving apparatus 100 performs the sustain pulse IP as shown in FIG._XAnd IP_YRow electrode X₁~ X_nAnd Y₁~ Y_nAre applied alternately. At this time, these sustain pulses IP are within one subfield._XAnd IP_YThe number of times (period) to apply is set corresponding to the weighting of each subfield.
For example, as shown in FIG.
SF1: 1
SF2: 2
SF3: 4
SF4: 8
Sustain pulse IP at the number of times (period) ratio_XAnd IP_YIs continuously applied.
[0010]
At this time, only the discharge cells in which the wall charges remain due to the pixel data writing process Wc, that is, the light emitting cells, are not subjected to the sustain pulse IP._XAnd IP_YEach time is applied alternately, discharge light is emitted and the light emission state is maintained.
Next, in the erasing step E, the driving device 100 applies an erasing pulse EP as shown in FIG.₁~ X_nBy applying the voltage to, all the discharge cells are erased and discharged all at once, and the wall charges remaining in each discharge cell are erased.
[0011]
For example, when the discharge cell emits light with luminance “8” by driving using the subfield method, light emission is performed only with SF4 of subfields SF1 to SF4, and light emission with luminance “7” is performed. In the case of causing light emission, light emission is performed in the subfields S1 to SF3. As a result, halftone luminance expression in 16 levels is possible.
[0012]
However, in the driving method as shown in FIG. 3, priming discharge is generated immediately before the application of the scan pulse SP in order to stably perform pixel data writing. There was a problem that the contrast of the image was lowered.
[0013]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for driving a plasma display panel that can improve the contrast of an image.
[0014]
[Means for Solving the Problems]
Claim 1The plasma display panel driving method according to the method forms discharge cells corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. A method of driving a plasma display panel, wherein a display period of one field is divided into a plurality of subfields, and at least two subfields continuously arranged among the subfields are used as subfield groups, and the subfields A reset process is performed to generate a reset discharge that initializes all the discharge cells to either the light-emitting cells or the non-light-emitting cells only in the first subfield of the group. In the subfieldEach of the discharge cells is sequentially written by one scan line, and belongs to the scan line that is the write target.Each of the discharge cells according to pixel dataSelectivelyNon-light emitting cellas well asOf the light emitting cellInsideEither oneSelect to set the status ofPerforming a pixel data writing step for causing discharge, and the light emitting cell in each of the subfields in the subfield group;The discharge cell in the state ofA sustain light emission process in which only the number of times of light emission corresponding to the weighting of the subfields is maintained and discharged, and the sustain light emission process includes:In the state of the light emitting cellAll the aboveDischargeA simultaneous sustaining light emission process for discharging the cells all at once,Immediately before or after the selective discharge, by applying a pulse only to the scan line to be written, the light emitting cell in each of the discharge cells belonging only to the scan line to be written The discharge cell in the state ofAnd a scan sustaining light emission process in which sustaining light emission discharge is performed.
[0015]
  or,Claim 11The plasma display panel driving method according to the method forms discharge cells corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. A method for driving a plasma display panel, wherein one field display period is divided into N subfields, and all the discharge cells emit light only in the first subfield in the one field display period. Performing a reset process for generating a reset discharge that is initialized to one of a cell and a non-light-emitting cell, and in any one of the N subfields;Each of the discharge cells is sequentially written by one scan line, and belongs to the scan line that is the write target.Each of the discharge cells according to pixel dataSelectivelyNon-light emitting cellas well asOf the light emitting cellInsideEither oneSelect to set the status ofPerforming a pixel data writing step to cause discharge, and the light emitting cell in each of the subfieldsThe discharge cell in the state ofA sustain light emission process in which only the number of times of light emission corresponding to the weighting of the subfields is maintained and discharged, and the sustain light emission process includes:In the state of the light emitting cellAll the aboveDischargeA simultaneous sustaining light emission process for discharging the cells all at once,Immediately before or after the selective discharge, by applying a pulse only to the scan line to be written, the light emitting cell in each of the discharge cells belonging only to the scan line to be written The discharge cell in the state ofAnd a scan sustaining light emission process in which sustaining light emission discharge is performed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 4 is a diagram showing a schematic configuration of a plasma display device that drives a plasma display panel (hereinafter referred to as PDP) to emit light based on the driving method according to the present invention.
[0017]
In FIG. 4, the A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from the drive control circuit 2, and for example samples 8-bit pixel data (input pixel) for each pixel. Data) D is converted and supplied to the data conversion circuit 30.
The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical synchronization signals in the input video signal. Further, the drive control circuit 2 generates various timing signals for driving and controlling the address driver 6, the first sustain driver 7 and the second sustain driver 8 in synchronization with the horizontal and vertical synchronization signals.
[0018]
The data conversion circuit 30 converts the 8-bit pixel data D into 8-bit converted pixel data (display pixel data) HD and supplies the converted data to the memory 4. The conversion operation of the data conversion circuit 30 will be described later.
The memory 4 sequentially writes the converted pixel data HD in accordance with the write signal supplied from the drive control circuit 2. When writing for one screen (n rows, m columns) is completed by such writing operation, the memory 4 stores the converted pixel data HD for one screen._11-nmAre read for each bit digit and supplied to the address driver 6 sequentially for each row.
[0019]
In response to the timing signal supplied from the drive control circuit 2, the address driver 6 outputs m pieces of pixel data having voltages corresponding to the logical levels of the converted pixel data bits for one row read from the memory 4. Pulses are generated, and these are generated by the column electrode D of the PDP 10₁~ D_mRespectively.
The PDP 10 includes the column electrode D as an address electrode.₁~ D_mAnd row electrodes X arranged orthogonal to these column electrodes₁~ X_nAnd row electrode Y₁~ Y_nIt has. In the PDP 10, a row electrode corresponding to one row is formed by a pair of the row electrode X and the row electrode Y. That is, the first row electrode pair in the PDP 10 is the row electrode X.₁And Y₁The row electrode pair in the nth row is the row electrode X_nAnd Y_nIt is. The row electrode pair and the column electrode are covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of each row electrode pair and the column electrode.
[0020]
Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses as described below in accordance with the timing signal supplied from the drive control circuit 2, and outputs these drive pulses to the row electrode X of the PDP 10.₁~ X_nAnd Y₁~ Y_nApply to.
FIG. 5 is a diagram showing a light emission drive format in one field display period in the plasma display device shown in FIG. The drive mode (A) shown in FIG. 5 is used when light emission drive is performed in an even field, and the drive mode (B) is used when light emission drive is performed in an odd field. It is.
[0021]
FIG. 6 shows that the address driver 6, the first sustain driver 7 and the second sustain driver 8 are connected to the column electrode D of the PDP 10 based on the light emission drive format.₁~ D_m, Row electrode X₁~ X_nAnd Y₁~ Y_nIt is a figure which shows the application timing of the various drive pulses applied to.
In the example shown in FIGS. 5 and 6, the display period of one field is divided into eight subfields SF1 to SF8 to drive the PDP 10. In each of these subfields SF1 to SF8, pixel data writing process Wc (Wc₁~ Wc₈), And the sustain emission process Ic (Ic) in which only the light emitting cell is maintained for the number of times corresponding to the weighting of each subfield.₁~ Ic₈). Also, the reset process Rc for initializing all the discharge cells of the PDP 10 is executed only in the first subfield SF1, and the wall charges remaining in all the discharge cells are erased simultaneously only in the last subfield SF8. Then, an erasing step E is performed to bring all the discharge cells into a non-light emitting cell state.
[0022]
In FIG. 6, in the simultaneous reset process Rc, the first sustain driver 7 and the second sustain driver 8 cause the reset pulse RP as shown in FIG._xAnd RP_YPDP10 row electrode X₁~ X_nAnd Y₁~ Y_nApply to each simultaneously. These reset pulses RP_xAnd RP_YIn response to the application, all the discharge cells in the PDP 10 are reset and a predetermined amount of wall charges are uniformly formed in each discharge cell. Thereby, all the discharge cells are set to the light emitting cells.
[0023]
Also, the pixel data writing process Wc in each of the subfields SF1 to SF8.₁~ Wc₈Then, the address driver 6 performs pixel data pulse group DP1 for each row.₁~ DP1_n, DP2₁~ DP2_n, DP3₁~ DP3_n... DP8₁~ DP8_nAs shown in FIG.₁~ D_mApply to. For example, the pixel data writing process Wc of the subfield SF1₁Then, the converted pixel data HD_11-nmPixel data pulse group DP1 corresponding to each of the first to nth rows generated based on each first bit₁~ DP1_nColumn electrode D sequentially for each row₁~ D_mIt is applied to. Also, the pixel data writing process Wc of the subfield SF2₂Then, the converted pixel data HD_11-nmPixel data pulse group DP2 generated based on each second bit₁~ DP2_nColumn electrode D sequentially for each row₁~ D_mIt is applied to. At this time, the address driver 6 generates a high-voltage pixel data pulse and applies it to the column electrode D only when the bit logic of the converted pixel data is, for example, the logic level “1”. At the same timing as the application timing of each pixel data pulse group DP, the second sustain driver 8 generates a scan pulse SP as shown in FIG.₁~ Y_nApply sequentially to. Here, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining inside are selectively erased. Due to the selective erasing discharge, the discharge cell initialized to the light emitting cell state in the simultaneous reset process Rc changes to a non-light emitting cell. It should be noted that no discharge occurs in the discharge cells formed in the “column” where the high voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, the state of the light emitting cell. To maintain.
[0024]
According to such an operation, a light emitting cell that maintains a light emitting state in a sustain light emitting process, which will be described later, and a non-light emitting cell that remains in an extinguished state are alternatively set according to pixel data, and so-called pixel data writing is performed. It is done.
The pixel data writing process Wc of the subfield SF1₁In FIG. 6, immediately before the scan pulse SP is applied to each row electrode Y, the second sustain driver 8 applies a priming pulse PP to the row electrode Y as shown in FIG. A priming discharge is generated in response to the application of the priming pulse PP, whereby charged particles are re-formed in the discharge space of the PDP 10. Accordingly, since the scanning pulse SP is applied immediately after the charged particles are re-formed, the selective erasing discharge is surely generated, and the pixel data writing error is prevented.
[0025]
Next, the sustain emission process Ic in each subfield₁~ Ic₈In each, the first sustain driver 7 and the second sustain driver 8 are connected to the row electrode X.₁~ X_nAnd Y₁~ Y_nIn contrast, as shown in FIG._XAnd IP_YApply. Such sustain pulse IP_XAnd IP_YEach time is applied alternately, the discharge cell in which the wall charges remain (that is, the discharge cell set as the light emitting cell in the pixel data writing process Wc performed immediately before) emits light. The sustain discharge is repeated. At this time, sustain light emission process Ic₁~ Ic₈The number of times of light emission by the sustain discharge in each is set corresponding to the weighting of each subfield.
[0026]
For example, at the time of light emission driving in the driving mode (A) shown in FIG.
SF1 (Ic₁: 6
SF2 (Ic₂: 22
SF3 (Ic_Three): 40
SF4 (Ic_Four: 60
SF5 (Ic_Five): 80
SF6 (Ic₆): 102
SF7 (Ic₇): 126
SF8 (Ic₈: 74
And
During light emission drive in drive mode (B),
SF1 (Ic₁): 2
SF2 (Ic₂): 12
SF3 (Ic_Three): 32
SF4 (Ic_Four): 48
SF5 (Ic_Five: 70
SF6 (Ic₆): 92
SF7 (Ic₇): 114
SF8 (Ic₈): 140
It becomes.
[0027]
The light emission period ratio in each of the subfields SF1 to SF8 is nonlinear (that is, the inverse gamma ratio, Y = X^2.2Thus, the nonlinear characteristic (gamma characteristic) of the input pixel data D is corrected.
As shown in FIG. 5, the sustain light emission process Ic in the other subfields except the last subfield SF8.₁~ Ic₇Each is a simultaneous maintenance light emission process I₁And scanning sustaining light emission process I₂It consists of and.
[0028]
Simultaneous maintenance light emission process I₁Then, as shown in FIG. 6, the first sustain driver 7 and the second sustain driver 8 are less than the number of times of discharge light emission for each subfield SF, as shown in FIG._XAnd IP_YRow electrode X alternately and simultaneously₁~ X_nAnd Y₁~ Y_nRespectively.
On the other hand, scanning sustaining light emission process I₂Then, as shown in FIGS. 5 and 6, the second sustain driver 8 prompts one sustain discharge immediately before application of each scan pulse SP in the pixel data writing process Wc of the next subfield. IP_YFApply. That is, sustain pulse IP_YFIs a sustain pulse IP applied for the total number of times of light emission as shown in FIG._YIs the last sustain pulse, and this is the same as the scan pulse SP, and the row electrode Y₁~ Y_nAre sequentially scanned and applied to cause the last one sustain discharge in the sustain light emission process Ic.
[0029]
Sustain pulse IP_YFIs applied to the row electrode Y, charged particles are formed in the discharge space of the PDP 10, so that the selective erasure discharge is surely generated when the scan pulse SP is applied immediately thereafter, and writing of pixel data is performed. Mistakes are prevented. That is, the sustain pulse IP that causes the last discharge light emission in each sustain light emission process Ic._YFAlso plays the role of the priming pulse PP as described above.
[0030]
Here, sustain light emission process Ic in subfield SF8₈Then, the first sustain driver 7 and the second sustain driver 8 have the sustain pulse IP as shown in FIG. 6 corresponding to the number of times of discharge light emission for each subfield SF as described above._XAnd IP_YRow electrode X alternately and simultaneously₁~ X_nAnd Y₁~ Y_nRespectively.
FIG. 7 shows the simultaneous sustaining light emission process I in each of the subfields SF1 to SF8.₁And scan maintaining light emission process I₂FIG. 6 is a diagram showing the number of times of light emission in, the total number of times of light emission in the sustain light emission process Ic, and the emission luminance ratio. 7A shows the drive mode (A), that is, the number of times of light emission in the case of performing the light emission drive in the even field, and FIG. 7B shows the number of times of light emission in the case of performing the light emission drive in the odd field. Is shown.
[0031]
Further, as shown in FIGS. 5 and 6, the erasing process E is executed only in the last subfield SF8 during one field display period. In the erasing process E, the address driver 6 generates an erasing pulse AP as shown in FIG._1-mTo each of the above. Further, at the same time as the application timing of the erase pulse AP, the second sustain driver 8 generates an erase pulse EP, which is generated by the row electrode Y.₁~ Y_nApply to each. By simultaneously applying these erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished.
[0032]
That is, by executing the erase process E, all the discharge cells in the PDP 10 become non-light emitting cells.
FIG. 8 is a diagram showing all patterns of light emission driving performed by the driving shown in FIGS. 5 and 6.
As shown in FIG. 8, selective erasure discharge is performed on each discharge cell only in the pixel data writing process Wc in one of the subfields SF1 to SF8 (indicated by black circles). . That is, wall charges formed in all the discharge cells of the PDP 10 by performing the simultaneous reset process Rc remain until the selective erasing discharge is performed, and the sustain light emission process in each subfield SF existing in the meantime. Discharge light emission is performed at Ic (indicated by white circles). Accordingly, each discharge cell becomes a light emitting cell until the selective erasing discharge is performed in the subfield indicated by the black circle in FIG. 8, and in the sustain light emission process Ic in each subfield existing in the meantime, FIG. As shown in FIG. 4, light is emitted as many times as the number of times of discharge light emission, and the light emission state is maintained.
[0033]
As described above, in the light emission drive pattern shown in FIG. 8, the number of times each discharge cell transitions from the light emitting cell to the non-light emitting cell is always less than or equal to one in one field period. That is, a light emission driving pattern that once returns a discharge cell set as a non-light emitting cell to a light emitting cell again within one field period is prohibited. Therefore, the above-described simultaneous reset operation with strong light emission is not necessary for the image display, and it is only necessary to perform the reset operation once in one field period as shown in FIGS. The decrease can be suppressed. Further, since the selective erasing discharge performed within one field period is at most once as shown by the black circle in FIG. 8, the power consumption can be suppressed. Further, as shown in FIG. 5, there is no light emission pattern in which the period in which the discharge cells are in the light emitting state (indicated by white circles) and the period in which the discharge cells are in the non-light emitting state are reversed in one field period. False contours can be prevented.
[0034]
Furthermore, in the present invention, as shown in FIGS. 5 and 6, a sustain pulse (IP that causes the last one sustain discharge in the sustain light emission process Ic) is generated._YF) Is scanned in the same manner as the scanning pulse SP, and the row electrode Y₁~ Y_nAre sequentially applied to cause a sustain discharge to occur immediately before each scanning pulse SP. At this time, the sustain discharge is accompanied by light emission according to the pixel data, and forms charged particles in each discharge cell. Therefore, the sustain discharge plays the same role as the priming discharge as described above. Therefore, even if priming discharge with light emission not related to pixel data is not required, pixel data can be written reliably. Therefore, when displaying an image as compared with the case where priming discharge is performed independently. This can improve the contrast.
[0035]
Here, according to the light emission drive pattern shown in FIG.
In the display period of the even field, as shown in the light emission luminance (A) in the figure,
{0: 3: 14: 34: 64: 104: 155: 218: 255}
The light emission drive capable of expressing the luminance of 9 gradations composed of the following light emission luminance ratio is made,
In the display period of the odd field, as shown in the light emission luminance (B) in the figure,
{0: 1: 7: 23: 47: 82: 128: 185: 255}
The light emission driving capable of expressing the luminance of 9 gradations having the light emission luminance ratio is performed.
[0036]
In this way, by performing two types of nine gradation driving with different light emission periods to be carried out in each subfield alternately for each field (frame), the number of display gradations on the visual level can be reduced. More than that.
Further, the number of display gradations on the eye increases from 9 gradations when integrated in the time direction. Accordingly, the dither and error diffusion patterns due to the multi-gradation processing described later are less noticeable and the S / N feeling is improved.
[0037]
FIG. 9 is a diagram showing an internal configuration of the data conversion circuit 30 shown in FIG.
As shown in FIG. 9, the data conversion circuit 30 includes an ABL circuit 31, a first data conversion circuit 32, a multi-gradation processing circuit 33, and a second data conversion circuit 34.
In FIG. 9, an ABL (automatic brightness control) circuit 31 is sequentially supplied from the A / D converter 1 so that the average brightness of an image displayed on the screen of the PDP 10 is within a predetermined brightness range. The brightness level is adjusted for the pixel data D for each pixel, and the brightness adjustment pixel data D obtained at this time is adjusted._BLIs supplied to the first data conversion circuit 32.
[0038]
The luminance level is adjusted before the inverse gamma correction is performed by setting the ratio of the number of times of light emission in the subfield to be nonlinear as described above. That is, the ABL circuit 31 automatically adjusts the luminance level of the pixel data D in accordance with the average luminance of the inverse gamma converted pixel data obtained by performing inverse gamma correction on the pixel data D (input pixel data). As a result, display quality deterioration due to brightness adjustment is prevented.
[0039]
FIG. 10 is a diagram showing an internal configuration of the ABL circuit 31. As shown in FIG.
In FIG. 10, the level adjustment circuit 310 adjusts the brightness adjustment pixel data D obtained by adjusting the level of the pixel data D according to the average brightness obtained by the average brightness detection circuit 311 described later._BLIs output. The data conversion circuit 312 receives the brightness adjustment pixel data D_BLAs shown in FIG. 11, the inverse gamma characteristic (Y = X^2.2) Is supplied to the average luminance level detection circuit 311 as inverse gamma conversion pixel data Dr. That is, luminance adjustment pixel data D_BLBy applying inverse gamma correction processing to the pixel data, the pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal for which the gamma correction has been canceled is restored. The average luminance detection circuit 311 obtains the average luminance of the inverse gamma conversion pixel data Dr and supplies it to the level adjustment circuit 310.
[0040]
Further, the average luminance detection circuit 311 selects a luminance mode in which the PDP 10 can be driven to emit light with the average luminance corresponding to the average luminance from the luminance modes 1 to 4 as shown in FIG. 12, for example. The luminance mode signal LC indicating the luminance mode is supplied to the drive control circuit 2. The average luminance detection circuit 311 uses the drive mode (A) in FIG. 12 when driving display for even fields, and the drive mode (B) in FIG. 12 when driving display for odd fields. The luminance mode as described above is selected. Here, the drive control circuit 2 performs the sustain light emission process Ic of each of the subfields SF1 to SF8 shown in FIG. 4 according to the luminance mode signal LC as shown in FIG.₁~ Ic₈The period during which light emission is to be maintained, that is, the number of times the sustain pulse IP is applied is set.
[0041]
At this time, the number of times of light emission in each subfield shown in FIG. 7 indicates the number of times of light emission when the luminance mode 1 is set. If the luminance mode 2 is set,
For even fields,
SF1: 12
SF2: 44
SF3: 80
SF4: 120
SF5: 160
SF6: 204
SF7: 252
SF8: 148
For odd fields,
SF1: 4
SF2: 24
SF3: 64
SF4: 96
SF5: 140
SF6: 184
SF7: 228
SF8: 280
The light emission driving in each subfield is performed at the number of times of light emission.
[0042]
Even in such light emission driving, the ratio of the number of times of light emission in each of the subfields SF1 to SF8 is nonlinear (that is, the inverse gamma ratio, Y = X^2.2Thus, the nonlinear characteristic (gamma characteristic) of the input pixel data D is corrected.
Here, the first data conversion circuit 32 in FIG. 9 is the 8-bit (0-255) 256-gradation luminance adjustment pixel data D supplied from the ABL circuit 31._BL8 bits (0 to 128) of converted pixel data HD_pAnd converted to the multi-gradation processing circuit 33.
[0043]
FIG. 13 is a diagram showing an internal configuration of the first data conversion circuit 32.
In FIG. 13, the data conversion circuit 321 includes the luminance adjustment pixel data D._BLIs converted into 8-bit (0-128) conversion pixel data A based on the conversion characteristics as shown in FIG. The data conversion circuit 323 receives the luminance adjustment pixel data D_BL15 is converted into 8-bit (0 to 128) converted pixel data B based on the conversion characteristics as shown in FIG. 15 and supplied to the selector 322. Specifically, each of the data conversion circuits 321 and 323 has the brightness adjustment pixel data D according to the conversion table as shown in FIGS. 16 and 17 based on the conversion characteristics shown in FIGS._BLAre converted into converted pixel data A and B. The selector 322 alternatively selects one of the conversion pixel data A and B in accordance with the logical level of the conversion characteristic selection signal, and selects this conversion pixel data HD._pOutput as. Such a conversion characteristic selection signal is supplied from the drive control circuit 2 shown in FIG. 4 and has a logic level “1” to “0” or “0” from “0” depending on the vertical synchronization timing of the input pixel data D. The signal transitions to 1 ". Here, the conversion characteristics in FIG. 14 and the drive mode (B) in FIG. 5 are paired with the conversion characteristics in FIG. 15 and the drive mode (A) in FIG. That is, the selector 322 selects the conversion pixel data B in the field (even field) in which the drive mode (A) in FIG. 5 is set, and the field (odd field) in which the drive mode (B) in FIG. 5 is set. Then, conversion pixel data A is selected and converted pixel data HD is selected._PIs output as The conversion characteristics are set according to the number of bits of input pixel data, the number of compression bits by multi-gradation described later, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the preceding stage of the multi-gradation processing circuit 33 to be described later, and the conversion is performed according to the display gradation number and the compression bit number by the multi-gradation, thereby adjusting the luminance. Pixel data D_BLThe upper bit group (corresponding to multi-gradation pixel data) and the lower bit group (data to be discarded: error data) are separated at bit boundaries, and multi-gradation processing is performed based on this signal. This prevents generation of luminance saturation due to multi-gradation processing and generation of a flat portion of display characteristics that occurs when the display gradation is not at the bit boundary (that is, generation of gradation distortion).
[0044]
With the configuration shown in FIG. 13, the first data conversion circuit 32 has 8-bit (0 to 255) luminance adjustment pixel data D supplied from the ABL circuit 31._BL8 bits (0 to 128) of converted pixel data HD while switching the conversion characteristics (FIGS. 14 and 15) for each field (frame)._pAnd converted to the multi-gradation processing circuit 33.
[0045]
FIG. 18 is a diagram showing an internal configuration of the multi-gradation processing circuit 33. As shown in FIG.
As shown in FIG. 18, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.
First, the data separation circuit 331 in the error diffusion processing circuit 330 receives the 8-bit converted pixel data HD supplied from the first data conversion circuit 32._PThe lower 2 bits are separated as error data, and the upper 6 bits are separated as display data. The adder 332 converts the converted pixel data HD as the error data._PAn addition value obtained by adding the lower two bits in the middle, the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335 is supplied to the delay circuit 336. The delay circuit 336 delays the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data, and delays the addition value AD.₁Are supplied to the coefficient multiplier 335 and the delay circuit 337, respectively. The coefficient multiplier 335 receives the delay addition signal AD.₁The predetermined coefficient value K₁A multiplication result obtained by multiplying (for example, “7/16”) is supplied to the adder 332. The delay circuit 337 receives the delay addition signal AD.₁Is further delayed by a time of (1 horizontal scanning period−the delay time D × 4).₂To the delay circuit 338. The delay circuit 338 receives the delayed addition signal AD.₂Is further delayed by the delay time D to obtain a delayed addition signal AD_ThreeAs a coefficient multiplier 339. In addition, the delay circuit 338 receives the delayed addition signal AD.₂Is further delayed by the delay time D × 2 to obtain a delayed addition signal AD_FourIs supplied to the coefficient multiplier 340. Further, the delay circuit 338 receives the delayed addition signal AD.₂Is obtained by delaying the delay time D × 3 by the delay time signal D × 3._FiveIs supplied to the coefficient multiplier 341. The coefficient multiplier 339 outputs the delayed addition signal AD_ThreeThe predetermined coefficient value K₂The multiplication result obtained by multiplying (for example, “3/16”) is supplied to the adder 342. The coefficient multiplier 340 receives the delayed addition signal AD._FourThe predetermined coefficient value K_ThreeThe multiplication result obtained by multiplying (for example, “5/16”) is supplied to the adder 342. The coefficient multiplier 341 receives the delayed addition signal AD._FiveThe predetermined coefficient value K_FourThe multiplication result obtained by multiplying (for example, “1/16”) is supplied to the adder 342. The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340, and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the time corresponding to the delay time D and supplies the delayed signal to the adder 332. The adder 332 outputs the error data (converted pixel data HD)._P(The lower 2 bits in the middle), the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335 are added. At this time, if there is no carry, there is a logical level “0” and carry. In this case, a carry-out signal C with a logic level "1"_OIs generated and supplied to the adder 333. The adder 333 receives the display data (converted pixel data HD)._PIn the upper 6 bits), the above carry-out signal C_OIs added as 6-bit error diffusion processed pixel data ED.
[0046]
The operation of the error diffusion processing circuit 330 having such a configuration will be described below.
For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 19, first, the pixel G (j, k) on the left side of the pixel G (j, k) is first obtained. k-1), upper left pixel G (j-1, k-1), upper right pixel G (j-1, k), and upper right pixel G (j-1, k + 1) Each error data corresponding to each, that is,
Error data corresponding to pixel G (j, k-1): delayed addition signal AD₁
Error data corresponding to pixel G (j-1, k + 1): delayed addition signal AD_Three
Error data corresponding to pixel G (j-1, k): delayed addition signal AD_Four
Error data corresponding to pixel G (j-1, k-1): delayed addition signal AD_Five
Each is represented by a predetermined coefficient value K as described above.₁~ K_FourIs weighted and added. Next, the conversion pixel data HD is added to the addition result._PThe error data corresponding to the lower 2 bits of the pixel, that is, the pixel G (j, k) is added, and the carrier-out signal C for 1 bit obtained at this time is added._OConvert pixel data HD_PThe upper 6 bits, that is, the display data corresponding to the pixel G (j, k) is added to the display data corresponding to the pixel G (j, k) as error diffusion processing pixel data ED.
[0047]
With this configuration, the error diffusion processing circuit 330 converts the converted pixel data HD._PThe upper 6 bits are displayed as display data, and the remaining lower 2 bits are regarded as error data. The peripheral pixels {G (j, k-1), G (j-1, k + 1), G (j-1 , k) and G (j−1, k−1)} are weighted and added to the display data. By this operation, the luminance of the lower 2 bits in the original pixel {G (j, k)} is expressed in a pseudo manner by the peripheral pixels, and therefore the number of bits is smaller than 8 bits, that is, the display data is 6 bits. Thus, luminance gradation equivalent to the 8-bit pixel data can be expressed.
[0048]
If this error diffusion coefficient value is added to each pixel at a constant rate, noise due to the error diffusion pattern may be visually confirmed, and the image quality is impaired. Therefore, the error diffusion coefficient K to be assigned to each of the four pixels as in the case of the dither coefficient described later.₁~ K_FourMay be changed for each field.
The dither processing circuit 350 performs a dither process on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby maintaining a luminance gradation level equivalent to the 6-bit error diffusion processing pixel data ED. Multi-gradation processing pixel data D with the number of bits further reduced to 4 bits_SIs generated. In this dither process, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when performing gradation display corresponding to 8 bits using upper 6 bits of pixel data of 8 bits of pixel data, a set of four pixels adjacent to each other on the left, right, and top is taken as one set. Four dither coefficients a to d having different coefficient values are assigned to each pixel data corresponding to the pixel and added. According to such dither processing, four different combinations of intermediate display levels are generated with four pixels. Therefore, even if the number of bits of pixel data is 6 bits, the luminance gradation level that can be expressed is 4 times, that is, halftone display equivalent to 8 bits is possible.
[0049]
However, if a dither pattern consisting of dither coefficients a to d is added to each pixel, noise due to the dither pattern may be visually confirmed and image quality is impaired.
Therefore, in the dither processing circuit 350, the dither coefficients a to d to be assigned to each of the four pixels are changed for each field.
[0050]
FIG. 20 is a diagram showing an internal configuration of the dither processing circuit 350. As shown in FIG.
In FIG. 20, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four adjacent pixels, and sequentially supplies these to the adder 351.
For example, as shown in FIG. 21, the pixel G (j, k) and pixel G (j, k + 1) corresponding to the jth row, and the pixel G (j + 1) corresponding to the (j + 1) th row. , k) and four dither coefficients a, b, c, d corresponding to the four pixels G (j + 1, k + 1), respectively. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.
[0051]
That is, in the first first field,
Pixel G (j, k): Dither coefficient a
Pixel G (j, k + 1): Dither coefficient b
Pixel G (j + 1, k): Dither coefficient c
Pixel G (j + 1, k + 1): Dither coefficient d
In the next second field,
Pixel G (j, k): Dither coefficient b
Pixel G (j, k + 1): Dither coefficient a
Pixel G (j + 1, k): Dither coefficient d
Pixel G (j + 1, k + 1): Dither coefficient c
In the next third field,
Pixel G (j, k): Dither coefficient d
Pixel G (j, k + 1): Dither coefficient c
Pixel G (j + 1, k): Dither coefficient b
Pixel G (j + 1, k + 1): Dither coefficient a
And in the fourth field,
Pixel G (j, k): Dither coefficient c
Pixel G (j, k + 1): Dither coefficient d
Pixel G (j + 1, k): Dither coefficient a
Pixel G (j + 1, k + 1): Dither coefficient b
The dither coefficients a to d are repeatedly generated by the assignment as described above and supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first field to the fourth field as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated. The adder 351 supplies the pixel G (j, k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j) supplied from the error diffusion processing circuit 330. + 1, k + 1) is added to each of the error diffusion processing pixel data ED corresponding to each of the dither coefficients a to d assigned to each field as described above, and the dither addition pixel data obtained at this time is added. This is supplied to the upper bit extraction circuit 353.
[0052]
For example, in the first field shown in FIG.
Error diffusion processing pixel data ED corresponding to the pixel G (j, k) + dither coefficient a,
Error diffusion pixel data ED corresponding to pixel G (j, k + 1) + dither coefficient b,
Error diffusion pixel data ED corresponding to the pixel G (j + 1, k) + dither coefficient c,
Error diffusion pixel data ED corresponding to pixel G (j + 1, k + 1) + dither coefficient d
Are sequentially supplied to the upper bit extraction circuit 353 as dither addition pixel data. The upper bit extraction circuit 353 extracts up to the upper 4 bits of the dither addition pixel data, and converts this to the multi-gradation pixel data D_SOutput as.
[0053]
As described above, the dither processing circuit 350 shown in FIG. 20 changes the dither coefficients a to d to be assigned corresponding to each of the four pixels for each field, thereby reducing visual noise due to the dither pattern. 4-bit (0 to 7) multi-gradation pixel data D which is visually reduced and multi-gradation while being reduced_SIs supplied to the second data conversion circuit 34.
[0054]
The second data conversion circuit 34 provides the multi-gradation pixel data D_SIs converted into converted pixel data (display pixel data) HD composed of first to eighth bits corresponding to each of the subfields SF1 to SF8 in accordance with a conversion table as shown in FIG. In FIG. 22, the bit of logical level “1” among the first to eighth bits in the converted pixel data HD is subjected to selective erasure discharge in the pixel data writing process Wc in the subfield SF corresponding to the bit. It indicates that it will be carried out (indicated by a black circle).
[0055]
The converted pixel data HD is supplied to the address driver 6 via the memory 4 as shown in FIG. At this time, the form of the converted pixel data HD is any one of nine patterns as shown in FIG. The address driver 6 assigns each of the first to eighth bits in the converted pixel data HD to each of the subfields SF1 to SF8, and only when the bit logic is the logic level “1”, In the pixel data writing process Wc, a high-voltage pixel data pulse is generated and applied to the column electrode D of the PDP 10. As a result, the selective erasing discharge is generated. Therefore, each discharge cell becomes a light emitting cell until the selective erasing discharge is performed in the subfield indicated by the black circle in FIG. 22, and in the sustain light emission process Ic in each of the continuous subfields existing therebetween, As shown in FIG. 7, light is emitted for the number of times of discharge light emission.
[0056]
Thus, during the even field (frame) display period, as shown in the light emission luminance (A) of FIG.
{0: 3: 14: 34: 64: 104: 155: 218: 255}
9-level light emission drive is made,
During the odd field (frame) display period, as shown in the light emission luminance (B) of FIG.
{0: 1: 7: 23: 47: 82: 128: 185: 255}
Thus, the light emission drive of 9 gradations is performed.
[0057]
FIG. 23 shows the relationship between the above-described two types of nine-level light emission luminance (display luminance level) and the input pixel data D. In the figure,-■-indicates the relationship between the input pixel data D and the display luminance level in the drive mode (A), and-◆-indicates the drive mode (B). From this figure, the gradation level expressed in one drive mode by changing the drive pattern for each field (frame), that is, the number of times of light emission (number of sustain pulses) in the sustain light emission process Ic of each subfield. It can be seen that the gradation level expressed in the other drive mode is set to be between. Therefore, due to the integration effect in the time direction, the number of visually displayed gradations is increased from 9 gradations, and the gradation expression is improved.
[0058]
Further, a value between adjacent gradation levels, for example, a value between the light emission luminance “3” and the light emission luminance “14” in the drive mode (A) (a level corresponding to the lower 4 bits of the input pixel data D). Is expressed by multi-gradation processing such as error diffusion and dither as described above.
Note that, when multi-gradation processing such as error diffusion and dithering is performed, if the number of original display gradations is small, the multi-gradation processing pattern is noticeable and the S / N feeling deteriorates. In addition, by changing the light emission drive pattern for each field (frame), the number of display gradations in the visual field increases, so that the pattern of multi-gradation processing becomes less conspicuous and the S / N feeling is improved. Further, it can be seen from FIG. 23 that the input pixel data D is reverse-gamma corrected by setting the light emission frequency ratio in the sustain light emission process Ic of each subfield to the reverse gamma ratio.
[0059]
As described above, although the number of gradations in the drive mode (A) and the drive mode (B) is 9 gradations as described above, there are many methods for changing the light emission drive pattern for each field (frame) described above. By combining with the gradation processing, the visual multi-gradation expression is equivalent to 256 gradations.
In the above embodiment, as a pixel data writing method, wall charges are formed in advance in each discharge cell at the beginning of one field, all discharge cells are set as light emitting cells, and selection is made according to pixel data. In particular, the case where the so-called selective erasure address method in which pixel data is written by erasing the wall charges has been described.
[0060]
However, the present invention can be similarly applied to a case where a so-called selective write addressing method in which wall charges are selectively formed according to pixel data as a pixel data writing method.
FIG. 24 is a diagram showing a light emission drive format when this selective write address method is adopted.
[0061]
FIG. 25 shows the column electrode D of the PDP 10 based on the light emission drive format shown in FIG.₁~ D_m, Row electrode X₁~ X_nAnd Y₁~ Y_nIt is a figure which shows the application timing of the various drive pulses applied to.
Furthermore, FIG. 26 is a diagram showing a conversion table used in the second data conversion circuit 34 when this selective write address method is adopted, and all the patterns of light emission driving performed within one field period.
[0062]
As shown in FIG. 25, when the selective write address method is adopted, first, in the simultaneous reset process Rc in the first subfield SF8, the first sustain driver 7 and the second sustain driver 8 Reset pulse RP to the row electrodes X and Y respectively_xAnd RP_YAre simultaneously applied. As a result, all discharge cells in the PDP 10 are reset and discharged, and wall charges are forcibly formed in each discharge cell (R₁). Immediately thereafter, the first sustain driver 7 sends the erase pulse EP to the row electrode X of the PDP 10.₁~ X_nAre simultaneously applied to cause an erasing discharge for erasing the wall charges formed in all the discharge cells (R).₂). That is, according to the execution of the simultaneous reset process Rc shown in FIG. 25, all the discharge cells in the PDP 10 are initialized to the non-light emitting cell state.
[0063]
In each pixel data writing process Wc in FIG. 25, only the discharge cells at the intersections of the “rows” to which the scanning pulse SP is applied and the “columns” to which the high-voltage pixel data pulses are applied are discharged (selection note). In the discharge cells, and wall charges are selectively formed in the discharge cells. Due to the selective write discharge, the discharge cell initialized to the non-light emitting cell state in the simultaneous reset process Rc is changed to the light emitting cell. It should be noted that no discharge is generated in the discharge cells formed in the “column” to which the high-voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, the non-light emitting cell. Maintain state.
[0064]
That is, by executing the pixel data writing process Wc, a light emitting cell whose light emission state is maintained in a sustain light emission process, which will be described later, and a non-light emitting cell that remains in an extinguished state are alternatively set according to the pixel data. In other words, pixel data is written to each discharge cell.
Each sustain light emission process Ic in FIG.₀And simultaneous maintenance light emission process I₁It consists of and.
[0065]
Scanning light emission process I₀Then, immediately after the second sustain driver 8 applies each of the scan pulses SP, the sustain pulse IP prompts one sustain discharge._YSApply. That is, sustain pulse IP_YSAs shown in FIG. 27, the sustain pulse IP is applied by the total number of times of light emission for each subfield._YIs the first sustain pulse, and this is the same as the row electrode Y as with the scan pulse SP.₁~ Y_nAre sequentially scanned and applied to cause the first sustain discharge in the sustain light emission process Ic.
[0066]
Simultaneous maintenance light emission process I₁Then, as shown in FIG. 25, the first sustain driver 7 and the second sustain driver 8 maintain the sustain pulse IP as shown in FIG. 25 by one less than the total number of times of light emission for each subfield._XAnd IP_YRow electrode X alternately and simultaneously₁~ X_nAnd Y₁~ Y_nRespectively.
Here, when the light emission driving by the selective writing address method is performed, as shown in FIG. 26, the selective writing is performed only in the subfield SF corresponding to the bit of the logical level “1” in the converted pixel data HD. Carry out discharge (indicated by black circles). At this time, the non-light emitting state is maintained in the subfield SF existing between the first subfield SF8 and the execution of the selective write discharge, and the subfield SF (in black circles) in which the selective write discharge is executed is maintained. And the light emission state is maintained in the subfield SF (indicated by white circles) existing thereafter.
[0067]
FIG. 28 is a diagram showing another example of the light emission drive format when the selective write address method is adopted.
In the driving shown in FIG. 28, each sustain light emission stroke Ic is changed to the scan sustain light emission stroke I.₀, Simultaneous maintenance light emission process I₁, And scanning sustaining light emission process I₂It consists of the following three strokes.
[0068]
First, the scan maintaining light emission process I₀Then, immediately after the application of each of the scan pulses SP, the second sustain driver 8 prompts the sustain pulse IP for one time._YSApply. That is, sustain pulse IP_YSAs shown in FIG. 29, the sustain pulse IP is applied by the total number of times of light emission for each subfield._YIs the first sustain pulse, and this is the same as the row electrode Y as with the scan pulse SP.₁~ Y_nAre sequentially scanned and applied to cause the first sustain discharge in the sustain light emission process Ic.
[0069]
Next, simultaneous maintenance light emission process I₁Then, as shown in FIG. 29, the first sustain driver 7 and the second sustain driver 8 cause the sustain pulse IP to be twice as many times as the total number of times of light emission for each subfield._XAnd IP_YRow electrode X alternately and simultaneously₁~ X_nAnd Y₁~ Y_nRespectively.
Last scan sustaining light emission stroke I₂Then, the second sustain driver 8 causes the sustain pulse IP that prompts one sustain discharge immediately before the application of each scan pulse SP._YFApply. That is, sustain pulse IP_YFIs a sustain pulse IP applied for the total number of times of light emission as shown in FIG._YIs the last sustain pulse, and this is the same as the scan pulse SP, and the row electrode Y₁~ Y_nAre sequentially scanned and applied to cause the last one sustain discharge in the sustain light emission process Ic.
[0070]
That is, in the drive shown in FIG. 28, sustain pulse IP to be applied for the total number of times of light emission (for each subfield) shown in FIG._YOf the first sustain pulse (IP_YS) Is applied immediately after each scanning pulse SP as shown in FIG. 25, and the last sustain pulse (IP_YF) Is applied by scanning immediately before each scanning pulse SP as shown in FIG. At this time, in the drive of FIG. 28 as well, the light emission drive based on the drive mode (A) as shown in FIG. 28A and the drive mode as shown in FIG. By executing the light emission drive based on (B) while switching alternately for each field (frame), the number of luminance gradations on the eye is increased.
[0071]
5, FIG. 6, FIG. 24, FIG. 25 and FIG. 28, the operation in the case where the simultaneous reset process Rc for simultaneously initializing all the discharge cells of the PDP 10 is executed only once in one field period. Although described, the present invention can be similarly applied to the case where the simultaneous reset process Rc is executed twice.
FIG. 30 is a diagram showing a light emission drive format made in view of this point.
[0072]
In the light emission drive format shown in FIG. 30, one field period is divided into six subfields, which are subfields SF1 to SF6, of which SF1 to SF3 are the first subfield group, and SF4 to SF6. A second subfield group is formed. At this time, the simultaneous reset process Rc as described above is performed in the first subfield of each of the first and second subfield groups, that is, the subfields SF1 and SF4, and the last of each of the first and second subfield groups is performed. The erasing process E is executed in the tail subfield, that is, the subfields SF3 and SF6. In each subfield, pixel data writing process Wc in which pixel data is written to set a light emitting cell and a non-light emitting cell, and the number indicated by the total number of times of light emission in FIG. 31 only for the light emitting cell. The sustain light emission process Ic is performed to generate the sustain discharge and maintain the light emission state. At this time, the sustain light emission process Ic in each of the subfields SF1 and SF2 in the first subfield group and the subfields SF4 and SF5 in the second subfield group is the simultaneous sustain light emission process I.₁And scanning sustaining light emission process I₂It consists of two strokes.
[0073]
Simultaneous maintenance light emission process I₁Then, as shown in FIG. 31, the first sustain driver 7 and the second sustain driver 8 maintain the sustain pulse IP by the number of times less than the total number of times of light emission for each subfield._XAnd IP_YRow electrode X alternately and simultaneously₁~ X_nAnd Y₁~ Y_nRespectively. On the other hand, scanning sustaining light emission process I₂Then, as shown in FIG. 30, immediately before the application of each scan pulse SP in the pixel data writing process Wc of the next subfield, the sustain pulse IP that prompts one sustain discharge is performed._YFApply.
[0074]
FIG. 32 is a diagram showing all patterns of light emission driving executed based on the light emission driving format shown in FIG.
As shown in FIG. 32, 4-bit multi-gradation pixel data D output from the multi-gradation processing circuit 33 is provided._SAccordingly, 16 kinds (16 gradations) of light emission are driven. In the figure, black circles indicate that selective erasure discharge occurs in the pixel data writing process Wc of the subfield, and white circles indicate that sustain discharge light emission is performed in the sustain light emission process Ic of the subfield. Indicates.
[0075]
As described above, according to the present invention, the last one of the plurality of sustain pulses that cause the sustain discharge in each sustain light emission process Ic is applied immediately before each scan pulse SP in the next subfield. Yes. Due to the sustain discharge, charged particles are re-formed in each discharge cell, so that a selective erasure discharge for writing pixel data is surely generated and pixel data writing is performed correctly. At this time, since the sustain discharge originally emits light related to the pixel data, the contrast of the image can be improved as compared with the case where the priming discharge is performed independently.
[0076]
As a method for ensuring the writing of the pixel data, there is a method of executing the same pixel data writing again within one field instead of causing the sustain discharge to occur immediately before the scanning pulse SP as described above.
FIG. 33 and FIG. 34 are diagrams showing a light emission drive pattern made in view of this point. FIG. 33 shows multi-gradation processing pixel data D obtained when the selective erasure address method is adopted._SFIG. 34 shows a correspondence relationship between all the patterns and the light emission drive pattern. FIG. 34 shows multi-gradation processing pixel data D obtained when the selective writing address method is adopted._SThe correspondence relationship between all the patterns and the light emission drive pattern is shown.
[0077]
Further, “*” shown in FIG. 33 and FIG. 34 indicates that either the logical level “1” or “0” may be used, and the triangle mark indicates that “*” is the logical level “1”. Only in this case, selective erasure (writing) discharge is performed in the pixel data writing process Wc of the subfield.
In short, since there is a possibility that writing of pixel data may fail in the first selective erasing (writing) discharge, selective erasing (writing) discharge is performed again in at least one of the subfields existing thereafter. This is done to ensure the writing of pixel data.
In the above-described embodiment, an example in which the scan sustain light emission discharge also serves as the priming discharge has been described. However, the scan sustain light emission discharge may also serve as a scan selective erasure (write) discharge. At this time, when the selective erasure address method is adopted, the selective erasure discharge itself carries out light emission for one time out of the number of times of sustain light emission to be performed in the sustain light emission process Ic of the immediately preceding subfield. . When the selective write address method is employed, the selective write discharge itself carries out light emission for one of the number of sustain light emissions to be performed in the sustain light emission process Ic of the subfield. Therefore, when driving based on the selective erasure address method, a subfield in which selective erasure discharge is performed (that is, a subfield to which a high-voltage pixel data pulse is applied simultaneously with the scanning pulse SP in the pixel data writing step Wc). The total number of times of sustain light emission (total number of light emission times shown in FIG. 7) executed in the sustain light emission process Ic in the subfield immediately before) can be reduced by one time. On the other hand, when driving based on the selective writing address method, the total number of times of sustain light emission executed in the sustain light emission process Ic in the subfield where selective write discharge is performed (the total number of light emission times shown in FIG. 7). Can be reduced by one dose.
[0078]
【The invention's effect】
As described above in detail, according to the plasma display driving method of the present invention, it is possible to improve the contrast.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a plasma display device.
FIG. 2 is a diagram showing a conventional light emission drive format for carrying out halftone display of 16 gradations.
FIG. 3 is a diagram illustrating an example of application timing of a conventional driving pulse applied to a PDP 10;
FIG. 4 is a diagram showing a schematic configuration of a plasma display apparatus for driving a plasma display panel according to a driving method according to the present invention.
FIG. 5 is a diagram showing a light emission drive format based on the drive method of the present invention.
6 is a diagram showing application timings of drive pulses applied to the PDP 10 based on the light emission drive format shown in FIG.
FIG. 7 is a diagram showing the number of times of sustain discharge light emission for each subfield.
FIG. 8 is a diagram illustrating an example of a light emission drive pattern.
9 is a diagram showing an internal configuration of a data conversion circuit 30. FIG.
10 is a diagram showing an internal configuration of an ABL circuit 31. FIG.
FIG. 11 is a diagram showing conversion characteristics in the data conversion circuit 312;
FIG. 12 is a diagram illustrating a correspondence relationship between a luminance mode and the number of times of sustain light emission for each subfield.
13 is a diagram showing an internal configuration of a first data conversion circuit 32. FIG.
14 is a diagram showing a first conversion characteristic in the first data conversion circuit 32. FIG.
15 is a diagram showing a second conversion characteristic in the first data conversion circuit 32. FIG.
16 is a diagram showing a conversion table based on the conversion characteristics shown in FIGS. 14 and 15. FIG.
17 is a diagram showing a conversion table based on the conversion characteristics shown in FIGS. 14 and 15. FIG.
18 is a diagram showing an internal configuration of a multi-gradation processing circuit 33. FIG.
FIG. 19 is a diagram for explaining the operation of the error diffusion processing circuit 330;
20 is a diagram showing an internal configuration of a dither processing circuit 350. FIG.
FIG. 21 is a diagram for explaining the operation of the dither processing circuit 350;
FIG. 22 is a diagram showing an example of all patterns of light emission driving performed based on the light emission driving format shown in FIG. 5 and an example of a conversion table used in the second data conversion circuit 34 when the light emission driving is performed. is there.
FIG. 23 is a diagram illustrating a relationship between two types of 9-level light emission luminance (display luminance level) and input pixel data D;
FIG. 24 is a diagram showing a light emission drive format when the selective write address method is employed.
FIG. 25 is a diagram showing application timings of various drive pulses applied to the PDP 10 when the selective write address method is employed.
FIG. 26 is a diagram showing an example of all the patterns of light emission driving when the selective writing address method is adopted, and an example of a conversion table used in the second data conversion circuit 34 when the light emission driving is performed.
FIG. 27 is a diagram showing the number of times of sustain discharge emission for each subfield when the selective write address method is employed.
FIG. 28 is a diagram showing another example of the light emission drive format when the selective write address method is employed.
29 is a diagram showing the number of times of sustain discharge light emission for each subfield when the light emission drive format shown in FIG. 28 is adopted.
FIG. 30 is a diagram showing a light emission drive format when the simultaneous reset process Rc is executed twice in one field period.
31 is a diagram showing the number of times of sustain discharge light emission for each subfield when the light emission drive format shown in FIG. 30 is adopted.
32 is a diagram showing an example of a light emission drive pattern based on the light emission drive format shown in FIG.
FIG. 33 is a diagram showing another example of the light emission drive pattern when the selective erase address method is employed.
FIG. 34 is a diagram showing another example of the light emission drive pattern when the selective write address method is employed.
[Explanation of main part codes]
2 Drive control circuit
6 Address driver
7 First Sustain Driver
8 Second Sustain Driver
10 PDP
30 Data conversion circuit
31 ABL circuit
32 First data conversion circuit
33 Multi-gradation processing circuit
34 Second data conversion circuit
330 Error diffusion processing circuit
350 dither processing circuit

Claims (25)

A method for driving a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
A display period of one field is divided into a plurality of subfields, and at least two subfields continuously arranged in the subfields are defined as subfield groups. Performing a reset process that causes a reset discharge to initialize the discharge cell to either the light emitting cell or the non-light emitting cell;
In each of the subfield groups, each of the discharge cells is sequentially set as a write target for each scan line, and each of the discharge cells belonging to the scan line as the write target is set according to pixel data. selectively the running non-light emitting cell and the pixel data writing process which allowed to rise to selective discharge for setting either one of the states of said light emitting cells Te,
Performing a sustain light emission process in which only the discharge cells in the light emitting cell state in each subfield in the subfield group are subjected to a sustain light emission discharge for the number of times of light emission corresponding to the weight of the subfield;
The sustain light emission process is a simultaneous sustain light emission process in which all the discharge cells in the state of the light emitting cells are simultaneously subjected to a sustain light emission discharge,
Immediately before or after the selective discharge, by applying a pulse only to the scan line to be written, the light emitting cell in each of the discharge cells belonging only to the scan line to be written And a scan sustaining light emitting step of causing the discharge cells in the state of FIG . 2. The plasma display panel according to claim 1, further comprising an erasing process for generating a discharge that causes all of the discharge cells to be in the non-light emitting cell state only in the last subfield of the subfield group. Driving method. In the reset process, all the discharge cells are initialized to the state of the light emitting cells by forming wall charges in all the discharge cells by the reset discharge, and in the pixel data writing process, the pixel data 2. The driving method of the plasma display panel according to claim 1, wherein the discharge cell is set to the non-light emitting cell by selectively selectively erasing and discharging the discharge cell in response to erasing the wall charge. . 4. The driving method of the plasma display panel according to claim 3, wherein the sustain light emission discharge in the scan sustain light emission process is caused immediately before the selective erasing discharge in the pixel data writing process. 5. The method of driving a plasma display panel according to claim 4, wherein the sustain light emission discharge in the scan sustain light emission process also serves as a priming discharge for the selective erasing discharge. In the reset process, all the discharge cells are initialized to the non-light emitting cell state by erasing wall charges remaining in all the discharge cells in the reset discharge, and in the pixel data writing process, 2. The plasma display panel according to claim 1, wherein the discharge cell is set as the light emitting cell by selectively discharging the selective discharge according to the pixel data to form the wall charge. Driving method. 7. The method of driving a plasma display panel according to claim 6, wherein the sustain light emission discharge in the scan sustain light emission process is caused immediately after the selective write discharge in the pixel data writing process. 7. The method of driving a plasma display panel according to claim 6, wherein the scan sustaining light emission process is executed immediately before the simultaneous sustaining light emission process. 7. The method of driving a plasma display panel according to claim 6, wherein the scan sustaining light emission process is executed immediately after the simultaneous sustaining light emission process. 7. The method of driving a plasma display panel according to claim 6, wherein the scan sustaining light emission process is executed immediately before and immediately after the simultaneous sustaining light emission process. A method for driving a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
The display period of one field is divided into N subfields, and all the discharge cells are initially set to either a light emitting cell or a non-light emitting cell only in the first subfield in the display period of the one field. Execute the reset process that causes the reset discharge to become
In each of the N subfields, each of the discharge cells is sequentially written for one scan line, and each of the discharge cells belonging to the scan line that is the write target is a pixel. selectively the running non-light emitting cell and the pixel data writing process which allowed to rise to selective discharge for setting either one of the states of said light emitting cell in accordance with the data,
Performing a sustain light emission process in which only the discharge cells in the light emitting cell state in each of the subfields are subjected to a sustain light emission discharge for the number of times of light emission corresponding to the weight of the subfield;
The sustain light emission process is a simultaneous sustain light emission process in which all the discharge cells in the state of the light emitting cells are simultaneously subjected to a sustain light emission discharge,
Immediately before or after the selective discharge, by applying a pulse only to the scan line to be written, the light emitting cell in each of the discharge cells belonging only to the scan line to be written And a scan sustaining light emitting step of causing the discharge cells in the state of FIG . 12. The plasma according to claim 11, further comprising an erasing process for generating a discharge that causes all of the discharge cells to be in the non-light emitting cell state only in the last subfield in the display period of the one field. Display panel drive method. In the reset process, all the discharge cells are initialized to the state of the light emitting cells by forming wall charges in all the discharge cells by the reset discharge, and in the pixel data writing process, the pixel data 12. The driving method of the plasma display panel according to claim 11, wherein the discharge cell is set to the non-light emitting cell by selectively selectively erasing and discharging the discharge cell to erase the wall charge. . 14. The driving method of the plasma display panel according to claim 13 , wherein the sustain light emission discharge in the scan sustain light emission process is caused immediately before the selective erasing discharge in the pixel data writing process. 15. The driving method of the plasma display panel according to claim 14 , wherein the sustain light emission discharge in the scan sustain light emission process also serves as a priming discharge for the selective erasing discharge. N + 1 gradation driving is performed by causing the sustain light emission to occur only in the sustain light emission process in each of the n subfields (n is 0 to N) continuous from the head of the display period of the one field. The method of driving a plasma display panel according to claim 11 . N + 1 gradation driving is performed by causing the sustain light emission discharge to occur only in the sustain light emission process in each of the n subfields (n is 0 to N) continuous from the end of the display period of the one field. The method of driving a plasma display panel according to claim 11 . 12. The driving method of the plasma display panel according to claim 11, wherein the non-linear display characteristic of the input pixel data is corrected by setting a non-linear ratio of the number of times of light emission in the sustain light emission process of each of the subfields. . 19. The method of driving a plasma display panel according to claim 18 , wherein the nonlinear display characteristic is a gamma characteristic. 19. The method of driving a plasma display panel according to claim 18 , wherein a multi-gradation process is performed on the input pixel data before the nonlinear display characteristic is corrected. 21. The method of driving a plasma display panel according to claim 20, wherein the multi-gradation processing is error diffusion processing and / or dither processing. 21. The plasma according to claim 20 , wherein the pixel data is converted before the multi-gradation processing to separate upper bit groups and lower bit groups necessary for the multi-gradation processing at bit boundaries. Display panel drive method. 12. The driving method of the plasma display panel according to claim 11 , wherein the number of times of light emission in the sustain light emission process of each of the subfields is changed for each field or frame. In the reset process, the reset discharge initializes all the discharge cells to the non-light emitting cell state by erasing wall charges from all the discharge cells,
In the pixel data writing process, the discharge cells are selectively selectively written and discharged according to the pixel data to form the wall charges in the discharge cells, thereby setting the discharge cells as the light emitting cells. The method of driving a plasma display panel according to claim 11 . 25. The driving method of a plasma display panel according to claim 24 , wherein the sustain light emission due to the scan sustain light emission process is caused immediately after the selective write discharge according to the pixel data writing process.

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