JP3672695B2 - Semiconductor memory device, microcomputer, and data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a parity check technique for a semiconductor memory device, and more particularly to a technique for enabling simultaneous detection of a plurality of bits in a parity check. For example, the present invention is applied to a semiconductor memory device incorporated as a cache memory in a single-chip microcomputer. It relates to effective technology.
[0002]
[Prior art]
In order to improve the processing performance of a data processing apparatus such as a microcomputer, a technique incorporating a cache memory has been conventionally applied. In the field where the operating system manages the memory without the user being aware of the real memory, the data processing device needs to support the address translation mechanism. The address translation mechanism is a mechanism for converting a virtual address into a physical address in order to realize virtual storage.
[0003]
Furthermore, in order to execute the address translation mechanism at a high speed, a technology that incorporates an address translation buffer (translation lookaside buffer, hereinafter simply referred to as TLB) in the microcomputer to hold a translation pair of a virtual address and a physical address has also been conventionally employed. Has been.
In a cache memory such as a built-in microcomputer, a cache miss hit is determined by comparing tag information read from the tag portion of the cache memory accessed by a virtual address with the upper bits of the physical address. There is a problem with synonyms. That is, a synonym problem arises by trying to access a copy of a block of main memory, which is essentially a real memory, with a virtual address. Therefore, in order to prevent a situation in which a plurality of pieces of data having the same physical address exist in the cache memory, a synonym check unit that stores basically the same information as the tag unit of the cache memory is provided. Whether or not data with the same physical address exists is determined by this synonym check unit, and the operation at the time of writing to the cache memory is controlled based on the determination result. That is, in the write operation at the time of a cache miss, if data with the same physical address already exists, it is already stored in the data portion to prevent a situation in which a plurality of data with the same physical address exists in the cache memory. Of the data, the data for the physical address is invalidated, and the cache memory is updated with new data read from the main memory instead.
[0004]
The synonym check unit is provided with a comparison circuit for comparing multi-bit data read from the memory cell array based on a physical address with comparison data. The comparison data is the upper bits of the physical address. The comparison between the multi-bit data read from the memory cell array and the comparison data is simultaneously performed in bit units, and the OR logic of the multi-bit comparison result is taken by the OR circuit in the subsequent stage, so that all bits match. Is detected. In the comparison between the multi-bit data read from the memory cell array and the comparison data, if all the bits match, it means that there are a plurality of data of the same physical address in the cache memory, so the data has already been stored. Among the data stored in the storage unit, the data for the physical address is invalidated, and new data read from the main memory is taken in instead.
[0005]
An example of a document describing the cache memory is “Computer Architecture and Configuration (pages 273 to 308)” issued by Asakura Shoten on November 5, 1995.
[0006]
[Problems to be solved by the invention]
By the way, the memory cell array has a plurality of memory cells arranged in the row direction and the column direction, and the word configuration of the memory cell array is a multiplication form of the number of memory cells arranged in the row direction and the number of memory cells arranged in the column direction. Indicated. For example, if 32 words are composed of 1 × 32, this means that the number of memory cell arrays in the row direction is 1 and the number of memory cell arrays in the column direction is 32.
[0007]
In a semiconductor memory device applied to a synonym or the like, a parity check is performed in order to improve data reliability against α (alpha) rays and noise. In a semiconductor memory device capable of simultaneous multi-bit reading, parity check is performed by fetching all bits of data required for simultaneous reading into a single parity operation circuit and performing an exclusive OR operation on them for alpha rays, noise, etc. Whether or not an error has occurred is determined.
[0008]
However, if a data error occurs simultaneously between two adjacent bits in the memory cell array (this is called “adjacent 2-bit simultaneous error”), the existing parity check method cannot determine it as an error. The read data is treated as correct. For example, the data of bit 0 and bit 1 adjacent to it in the memory cell array are the logical value “1” and the logical value “0”, respectively, and this causes an adjacent 2-bit simultaneous error due to the influence of α rays and noise. Even though two adjacent bits are logically inverted at the same time, such as logical value “0” and logical value “1”, respectively, it does not affect the existing parity check result. Such an error cannot be detected.
[0009]
To make it possible to detect the adjacent 2-bit simultaneous error as described above, for example, it is conceivable that the 32 word configuration is 2 × 16. When the word configuration is 2 × 16, one of the adjacent 2 bits is selected by the column system selection, and the adjacent 2 bits are not read at the same time. Errors can be detected.
[0010]
However, if the 32 word configuration is 2 × 16, the chip layout of the memory cell array becomes undesirably horizontally long, for example, the word line becomes undesirably long, and the delay time cannot be ignored. The time from the word line drive to the actual output of data becomes long. Therefore, it is not a good idea to set the 32-word configuration to 2 × 16 and enable detection of adjacent 2-bit simultaneous errors because the access speed of the semiconductor memory device is sacrificed.
[0011]
An object of the present invention is to provide a technique for detecting a simultaneous error between adjacent bits without sacrificing the access speed of a semiconductor memory device.
[0012]
Another object of the present invention is to provide a semiconductor memory device capable of detecting simultaneous errors between adjacent bits without sacrificing access speed.
[0013]
Another object of the present invention is to provide a microcomputer incorporating such a semiconductor memory device.
[0014]
Still another object of the present invention is to provide a data processing apparatus having such a microcomputer.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0017]
That is, a logical operation for parity check is performed for each data group of a plurality of bits that are not adjacent to each other in the memory cell array (42) in which bit allocation is performed for each column. By performing a logical operation for parity check for each data group of a plurality of bits that are not adjacent to each other, it is possible to detect an adjacent bit simultaneous error. At this time, since bit allocation is performed for each column, the memory cell array can be prevented from being laid out horizontally, and the word line can be prevented from becoming undesirably long. Achieving higher access speed of storage devices.
[0018]
Also, the access speed is sacrificed by configuring the semiconductor memory device including a parity operation circuit that takes in data from the memory cell array in every bit or every plurality of bits in the bit allocation direction and performs a logical operation for parity check. Thus, a semiconductor memory device capable of detecting a simultaneous error between adjacent bits can be configured.
[0019]
Parity check of read data from the memory cell array can be performed by logical operation of the memory cell array in which bit allocation is performed for each column, and the read data for a plurality of bits in the memory cell array and the corresponding parity bit data. In addition to the parity check unit (46), a first data group having a multi-bit configuration read from the memory cell array and a second data group to be compared with the first data group in bit units. When a comparison unit (44) for comparison is provided, the parity check unit takes in data from the memory cell array in every bit or every plurality of bits in the bit allocation direction and performs a logical operation for parity check. It includes a parity operation circuit (461, 462). A plurality of bit comparison circuits 66- are arranged corresponding to the bit configurations of the first data group and the second data group, and each compare the first data group and the second data group in bit units. 1 to 66-n and any one of the comparison results from the plurality of bit comparison circuits are activated based on the logical state of one bit, and in the activated state, the plurality of bit comparison circuits An OR circuit (45) for obtaining a logical sum of all the bits except the one arbitrary bit can be configured. In such a configuration, the active state of the OR circuit can be switched between active and inactive using the logic state of any one bit among the comparison results from the plurality of bit comparison circuits. A clock signal for timing control is unnecessary, and the timing margin of the clock signal is also unnecessary. In addition, the number of circuit stages can be reduced as compared with the case where the multi-bit comparison circuit is formed by a static circuit. This achieves speeding up of the operation of the multi-bit comparison circuit, and further speeding up of the operation of the cache memory when such a multi-bit comparison circuit is applied to the synonym check unit of the cache memory. And, as mentioned above, simultaneous errors between adjacent bits can be detected without sacrificing access speed, so the operation speed when applied to cache memory is improved and the reliability of cache data is improved. To do. Therefore, when the semiconductor memory device having the above-described configuration is made on-chip as the cache memory (10) in the microcomputer (31) that is made into one chip, the microcomputer is further improved by increasing the operation speed of the cache memory. The reliability of arithmetic processing results is achieved by shortening the arithmetic processing time in a data processing apparatus including the above and improving the reliability of cache data.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 shows a computer system which is an example of a data processing apparatus according to the present invention.
[0021]
This computer system includes a microcomputer 31, SDRAM (Synchronous Dynamic Random Access Memory) 32, SRAM 33 (Static Random Access Memory), ROM (Read Only Memory) via a system bus BUS. 34, the peripheral device control unit 35, the display control unit 36, and the like are coupled so that signals can be exchanged with each other, and perform predetermined data processing according to a predetermined program. The microcomputer 31 is the logical core of the system, and mainly handles addressing, information reading and writing, data operations, instruction sequences, interrupt acceptance, and information exchange between the storage device and the input / output device. It has functions such as activation, and is composed of an arithmetic control unit, a bus control unit, a memory access control unit and the like. The SDRAM 32, SRAM 33, and ROM 34 are positioned as internal storage devices. The SDRAM 32 is used as a work area for calculation and control in the microcomputer 31. The SRAM 33 functions as a main memory into which a program executed by the microcomputer 31 is loaded. The ROM 34 stores a read-only program. The peripheral device control unit 35 performs operation control of the external storage device 38 such as a hard disk and information input control from the keyboard 39 or the like. The display control unit 36 controls information display on the CRT display 40. The display control unit 36 includes a semiconductor chip and an image memory for drawing processing.
[0022]
FIG. 3 shows a configuration example of the microcomputer 31. The microcomputer 31 includes a cache memory 10, an address translation buffer (hereinafter also simply referred to as “TLB”) 11, a control unit 12, and a peripheral module 13, which are not particularly limited, and are coupled to internal buses 14 and 15. And formed on a single semiconductor substrate.
[0023]
The control unit 12 is a circuit block that collectively refers to the functions of the central processing unit, bus controller, control circuit of the cache memory 10 and TLB 11, external interface circuit, and the like. In FIG. An internal controller 121 and an external bus controller 122 are shown as circuit blocks. The internal memory 14 is connected to the cache memory 10, the TLB 11, and the internal controller 121, and the internal bus 15 is connected to the TLB 11, the peripheral module 13, and the external bus controller 122. The peripheral module 13 includes appropriate peripheral circuits such as a timer, a serial communication interface, a RAM (random access memory), a ROM (read only memory), and a DMAC (direct memory access controller) not shown. In the figure, 16 is a control signal line group for the cache memory 10, 17 is a control signal line group for the TLB 11, 18 is a control signal line group between the TLB 11 and the peripheral circuit module 13, and 19 is a control signal line group for the peripheral module 13. , 20 is a control signal line group between the cache memory 10 and the TLB 11. The microcomputer 31 of this configuration example is not particularly limited, but is connected to the SRAM 33 via the system bus BUS. In this configuration example, the address translation mechanism for realizing the virtual memory is composed of the TLB 11 and a circuit in the control unit 12 for controlling the TLB 11.
[0024]
FIG. 4 shows a configuration example of the cache memory 10.
[0025]
As shown in FIG. 4, the cache memory 10 includes a tag unit 72, a data unit 73, a comparison unit 74, and a synonym check unit 75.
[0026]
A virtual address is input to the tag unit 72 and the data unit 73, and a physical address corresponding to the virtual address is input to the comparison unit 74 and the synonym check unit 75. Tag information is read from the tag unit 72 based on the virtual address and transmitted to the comparison unit 74. The comparison unit 74 compares the tag information output from the tag unit 72 with the physical address. In this comparison, if the tag information output from the tag unit 72 matches the physical address, a cache hit is detected, and if the tag information does not match, a cache miss is determined. In the case of a cache hit, data corresponding to the virtual address is read from the data unit 73, but in the case of a cache miss, data reading from the data unit 73 is not performed. In that case, new data is fetched from the SRAM 33, and the contents of the cache memory are updated with the data.
[0027]
In addition, in order to prevent a situation in which a plurality of pieces of data having the same physical address exist in the cache memory, when a physical address is input, information read from the memory cell array in the synonym check unit 75 based on the physical address The comparison data generated from the physical address is compared in bit units. The comparison data is the upper bits of the physical address, and the lower reciprocal bits are used for memory access in the synonym chuck circuit 75. In a write operation at the time of a cache miss, if data with the same physical address already exists, in order to prevent a situation in which a plurality of data with the same physical address exists in the cache memory, Of these, the data for the physical address is invalidated and new data is taken in instead.
[0028]
FIG. 5 shows a configuration example of the synonym check unit 75.
[0029]
As shown in FIG. 5, the synonym check unit 75 amplifies a memory cell array 42 in which a plurality of static memory cells are arranged, a decoder 41 for decoding an address Adr, and a signal read from the memory cell array 42. Sense amplifier 43, a comparison unit 44 for comparing the output signal of the sense amplifier 43 and the comparison data CD0 to CDn in bit units, and an OR for obtaining a logical sum of the comparison results of a plurality of bits from the comparison unit 44. A circuit 45 and a parity check unit 46 for determining whether or not the data read from the memory cell array 42 is logically inverted by α-rays, noise, or the like by a parity check. When the parity check unit 46 determines that the read data from the memory cell array 42 is normal, the output OUT of the OR circuit 45 is validated as a synonym check result. However, when the parity check unit 46 detects a data error In this case, the output OUT of the OR circuit 45 is invalidated. The address input to the decoder 41 is the lower multiple bits of the physical address, and the comparison data CD0 to CDn input to the comparison unit 44 are the upper multiple bits of the physical address.
[0030]
In practice, a plurality of sets of the constituent circuits shown in FIG. 5 are provided. For example, when the virtual address is 3 bits, there are 2 to the 3rd power, that is, 8 virtual spaces, and in the case of the 4-way set associative format, there are 32 (= 8 × 4) virtual spaces. Therefore, for the synonym check, 32 circuit configurations shown in FIG. 5 are provided corresponding to the virtual space, and the above synonym check operation is performed each time the virtual address is converted into the physical address. Done.
[0031]
FIG. 1 shows the relationship between the memory cell array 42 and the parity check unit 46.
[0032]
The memory cell array 42 is not particularly limited, but the memory cell array includes a plurality of memory cells arranged in the row direction and the column direction. For example, the memory cell array 42 is composed of 32 words of 1 × 32, the number of memory cell arrays in the row direction is 1, and the number of memory cell arrays in the column direction is 32. Although not particularly limited, the parity check unit 46 includes a first parity calculation circuit 461 and a second parity calculation circuit 462. Of bits BIT0 to BIT17, bits 0 to BIT15 are assigned to data, and bits BIT16 and BIT17 are used as parity bits.
[0033]
The data of bits 0, 2, 4 to 16, which are even-numbered bits, is transmitted to the first parity operation circuit 461 via the sense amplifier 43, and the data of bits 1, 3, 5 to 17 which are odd-numbered bits. Is transmitted to the second parity check unit 462 via the sense amplifier 43. That is, the first parity operation circuit 461 and the second parity operation circuit 462 perform the logical operation for the parity check for each data group of a plurality of bits that are not adjacent to each other in the memory cell array. In other words, each of the first parity calculation circuit 461 and the second parity calculation circuit 462 performs a logical operation for every other data group. Accordingly, when an error occurs for the even-numbered bits, it is detected by the first parity operation circuit 461. When an error occurs for the odd-numbered bits, it is detected by the second parity operation circuit 462. Detected. As described above, in the first parity operation circuit 461 and the second parity operation circuit 462, since logical operations are performed on data groups every other bit, errors occur simultaneously between adjacent bits. But it can be detected accurately. For example, the data of bit 0 and bit 1 adjacent to it in the memory cell array are the logical value “1” and the logical value “0”, respectively, and this causes an adjacent 2-bit simultaneous error due to the influence of α rays and noise. When the adjacent two bits are logically inverted at the same time as in the logic value “0” and the logic value “1”, respectively, the data of bit 0 is transmitted to the first parity operation circuit 461 and the bit 1 Since the data is transmitted to the first parity calculation circuit 461, the error detection is performed in the first parity calculation circuit 461 and the second parity calculation circuit 462, respectively.
[0034]
Further, even when an adjacent 3-bit simultaneous error occurs, it can be detected. For example, when simultaneous errors occur in bits 0, 1, and 2, error detection cannot be performed by the first parity calculation circuit 461, but error detection is performed by the second parity calculation circuit 462. Therefore, by using the output signal P1 of the first parity operation circuit 461 and the output signal P2 of the second parity operation circuit 462 as the parity check result of the read data from the memory cell array 42, an adjacent 3-bit simultaneous error can be obtained. It can be detected and reflected in the processing of read data from the memory cell 42 as a parity calculation result.
[0035]
FIG. 6 representatively shows a configuration example of the first parity operation circuit 461.
[0036]
As shown in FIG. 6, the first parity operation circuit 461 is configured by exclusive OR circuits (abbreviated as “EOR”) 111 to 118 for obtaining exclusive OR. The exclusive OR of the bits BIT0 and BIT2 is obtained by the EOR111, the exclusive OR of the bits BIT4 and BIT6 is obtained by the EOR112, the exclusive OR of the bits BIT8 and BIT10 is obtained by the EOR113, and the bit BIT12 , Bit BIT14 is exclusive-ORed by EOR14. An exclusive OR of the output signal of EOR 111 and the output signal of EOR 112 is obtained by EOR 115, and an exclusive OR of the output signal of EOR 113 and the output signal of EOR 114 is obtained by EOR 116, and the output signal of EOR 115 and EOR 116 are obtained. Is obtained by the EOR 117, and the exclusive OR of the output signal of the EOR 117 and the bit BIT16 which is the parity bit is obtained by the EOR 118, so that the first parity operation circuit 461 An output signal P1 is obtained.
[0037]
FIG. 6 shows a configuration example of the first parity calculation circuit 461, but the second parity calculation circuit 462 has the same configuration.
[0038]
FIG. 7 shows a configuration example of the comparison unit 44 in FIG. 5 and a relationship between the comparison unit 44 and the OR circuit 45.
[0039]
As shown in FIG. 7, the comparison unit 44 includes a plurality of bit comparison circuits 61-1 to 61-n corresponding to the number of bits simultaneously read from the memory cell array 42. Corresponding comparison data CD0 to CDn are input to the plurality of bit comparison circuits 61-1 to 61-n, read simultaneously from the memory cell array 42, amplified by the sense amplifier 43, and comparison data. A logical comparison is performed in units of bits with CD0 to CDn. The number of bit comparison circuits 61-1 to 61-n corresponds to the multi-bit output from the memory cell array 42. Only the comparison result of an arbitrary bit comparison circuit, for example, the nth bit comparison circuit 61-n is inverted by the inverter 63 and then input to the OR circuit 45 as the activation signal φ1 of the OR circuit 45. It has become. Further, the comparison results of the bit comparison circuits excluding the nth bit comparison circuit 61-n, that is, the 1st to (n-1) th bit comparison circuits 61-1 to 61-n-1, obtain the logical sum of them. Therefore, it is input to the OR circuit 45.
[0040]
FIG. 8 representatively shows a configuration example of the bit comparison circuit 61-1 among the plurality of bit comparison circuits 61-1 to 61-n.
[0041]
As shown in FIG. 8, the bit comparison circuit 61-1 includes an n-channel MOS transistor Q31 and a p-channel MOS transistor Q32 connected in parallel, and an n-channel MOS transistor Q33 and a p-channel MOS transistor Q34. The inverters 50 and 51 are connected in parallel and coupled to control the operation of the MOS transistors Q31 to Q34 by the nth comparison data CDn. The nth comparison data CDn is inverted by the inverter 50 and then transmitted to the gate electrode of the n-channel MOS transistor Q31 and the gate electrode of the p-channel MOS transistor Q34. The output signal of the inverter 50 is inverted by the inverter 51 in the subsequent stage and then transmitted to the gate electrode of the p-channel MOS transistor Q32 and the gate electrode of the n-channel MOS transistor Q33. When the output signal from the sense amplifier 43 is transmitted through complementary level data lines D and D * (* means signal inversion or low active), the data line D is coupled to the MOS transistors Q31 and Q32. Data line D * is coupled to MOS transistors Q33 and Q34. When the output signal from the sense amplifier 43 matches the nth comparison data, the output signal of the bit comparison circuit 61-1 is set to the low level, and conversely, the output signal from the sense amplifier 43 is When the nth comparison data does not match, the output signal of the bit comparison circuit 61-1 is set to the high level.
[0042]
When the n-th comparison data CDn is at a low level, the n-channel MOS transistor Q31 and the p-channel MOS transistor Q32 are turned on. At this time, the n-channel MOS transistor Q33 and the p-channel MOS transistor Q34 are turned off. In that case, the logic of the data line D is transmitted to the OR circuit 45 via the MOS transistors Q31 and Q32. When the data line D is at high level, it does not match the low level of the nth comparison data CDn, and a high level output is made to the OR circuit 45. On the other hand, when the data line D is at the low level, it coincides with the low level of the nth comparison data CDn, and a low level output is made to the OR circuit 45.
[0043]
When the nth comparison data CDn is at a high level, the n-channel MOS transistor Q33 and the p-channel MOS transistor Q34 are turned on. At this time, the n-channel MOS transistor Q31 and the p-channel MOS transistor Q32 are turned off. In that case, the logic of the data line D * is transmitted to the OR circuit 45 via the MOS transistors Q33 and Q34. When the data line D * is at the high level, it means that the data line D is at the low level, which means data mismatch. When the data line D * is at a high level, this means that the data line D is at a low level. Therefore, a high level output is made to the OR circuit 45 due to a data mismatch.
[0044]
The other bit comparison circuits 61-2 to 61-n are configured in the same manner as described above.
[0045]
FIG. 9 shows a configuration example of the OR circuit 45 shown in FIG.
[0046]
P-channel MOS transistors Q21 and Q22 are connected in parallel, and p-channel MOS transistors Q23 and Q24 are connected in parallel. The drain electrodes of the p-channel MOS transistors Q21, Q22, Q23, Q24 are coupled to the high potential side power supply Vdd. The source electrodes of the p-channel MOS transistors Q21 and Q22 are the drain electrodes of the n-channel MOS transistors Q27 to Q29, the base electrode of the n-channel MOS transistor Q25, and the gate electrode of the p-channel MOS transistor Q23 via the node NA. Connected to. This connection location is referred to as a node NA. The source electrodes of p-channel MOS transistors Q23 and Q24 are coupled to the gate electrode of p-channel MOS transistor Q22 and the drain electrode of n-channel MOS transistor Q25 via node NB. The source electrodes of n channel type MOS transistors Q25, Q27, Q28, Q29 are coupled to low potential side power supply Vss through n channel type MOS transistor Q26. The gate electrodes of n-channel MOS transistors Q27, Q28, Q29 are coupled to the output terminals of bit comparison circuits 61-1, 61-2, 61-3 via terminals T1, T2, T3, respectively. The gate electrode of the n-channel MOS transistor Q26 is coupled to the output terminal of the bit comparison circuit 61-n through the terminal Tn.
[0047]
When the activation signal φ1 taken in through the terminal Tn is at a high level, the n-channel MOS transistor Q26 is turned on, and the source electrodes of the n-channel MOS transistors Q25 and Q27 to Q29 are conducted to the low potential side power supply Vss. As a result, the OR circuit 45 is activated. When the activation signal φ1 is at a low level, the n-channel MOS transistor Q26 is turned off, and the source electrodes of the n-channel MOS transistors Q25 and Q27 to Q29 are not conducted to the low potential side power supply Vss. The OR circuit 45 is deactivated.
[0048]
Here, consider a case where the output signal of the sense amplifier 43 and the corresponding comparison data CD0 to CDn completely match. In this case, all the output signals of the bit comparison circuits 61-1 to 61-n are set to the low level. When the output signal of the bit comparison circuit 61-n is set to the low level, the activation signal φ1 obtained by logically inverting it by the inverter 63 is set to the high level, so that the n-channel MOS transistor Q26 When turned on and the source electrodes of the n-channel MOS transistors Q25 and Q27 to Q29 are conducted to the low potential side power source Vss via the n-channel MOS transistor Q26, the OR circuit 45 is activated. At this time, since the output signals of the bit comparison circuits 61-1 to 61-3 are all at the low level, the n-channel MOS transistors Q27, Q28, and Q29 are turned off, and the node NA is set to the high level. Thus, the n-channel MOS transistor Q25 is turned on, whereby the node NB is set to the low level. When the node NB is at a low level, the output signal OUT of the OR circuit 45 is also at a low level. The low level output of the output signal OUT of the OR circuit 45 indicates that the output signal of the sense amplifier 43 and the corresponding comparison data CD0 to CDn completely match.
[0049]
On the other hand, when only the bit comparison circuit 61-n is set to the high level among the bit comparison circuits 61-1 to 61-n, the activation signal φ1 is set to the low level, and the n-channel MOS transistor Q26. Is turned off, the OR circuit 45 is deactivated. When the activation signal φ1 is set to the low level, the p-channel MOS transistor Q24 is turned on, so that the node NB is set to the high level, so that the output signal OUT is also set to the high level. Further, when at least one of the bit comparison circuits 61-1 to 61-n-1 other than the bit comparison circuit 61-n is set to the high level output, the node NA is set to the low level. Since the type MOS transistor Q25 is turned off and the node NA is set to the high level, the output signal OUT of the OR circuit 45 is also set to the high level. The high level of the output signal OUT of the OR circuit 45 indicates that the output signal of the sense amplifier 43 and the corresponding comparison data CD0 to CDn do not completely match.
[0050]
In this way, a discrimination result (output signal OUT) between the case where the output signal of the sense amplifier 43 and the corresponding comparison data CD0 to CDn completely coincide with each other is not obtained.
[0051]
According to the above example, the following effects can be obtained.
[0052]
(1) An adjacent bit simultaneous error can be detected by performing a logical operation for parity check for each data group of a plurality of bits that are not adjacent to each other. At this time, since bit allocation is performed for each column, it is possible to avoid the memory cell array from being laid out horizontally as in the case where 32 words are configured by 2K × 16, for example. Since an undesirably long length can be prevented, the access speed of the memory cell array 42 can be increased.
[0053]
(2) The OR circuit 45 for obtaining the logical sum of all bits except for one arbitrary bit among the plurality of bit comparison circuits 61-1 to 61-n is switched between active and inactive by the arbitrary one bit. Therefore, it is not necessary to specially form a clock signal for timing control, and the timing margin of the clock signal is not necessary. In addition, the number of circuit stages can be reduced as compared with the case where the multi-bit comparison circuit is formed by a static circuit. As a result, the comparison operation can be speeded up. Further, when the OR circuit 45 is inactivated by the one arbitrary bit, the current consumption in the OR circuit 45 is almost zero, so that the current consumption of the circuit can be reduced.
[0054]
(3) n-channel MOS transistors Q27 to Q29 arranged corresponding to the plurality of bit comparison circuits and connected in parallel to each other, and a base electrode coupled to the drain electrode of the n-channel MOS transistor An n-channel MOS transistor Q25 and a current source MOS transistor Q26 commonly connected to the source electrodes thereof are provided, and an arbitrary one of the comparison results from the plurality of bit comparison circuits is provided at the gate electrode of the current source MOS transistor. Therefore, the above OR circuit can be easily formed.
[0055]
(4) A cache memory 10 capable of operating at high speed by speeding up other bit simultaneous comparison, an address translation buffer 11 for storing a translation pair for converting a virtual address into a physical address, and the cache memory and the address translation buffer. By configuring the microcomputer 31 including the control unit 12 to be controlled, it is possible to shorten the time for instruction fetching and the like, and to speed up the arithmetic processing of the microcomputer.
[0056]
(5) By configuring the data processing apparatus to include the microcomputer 31 in which the calculation processing is speeded up and the SRAM 33 accessed by the microcomputer 31 via the bus BUS9, the data processing is performed. Can be speeded up.
[0057]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0058]
For example, in the above example, every other bit of data in the bit allocation direction is taken into the first parity calculation circuit 461 and the second parity calculation circuit 462 to perform a logical operation for parity check. Alternatively, every two bits or more of data may be taken in and a logical operation for parity check may be performed.
[0059]
In the above description, the case where the invention made mainly by the present inventor is applied to the microcomputer built-in cache memory, which is the field of use behind it, has been described. However, the present invention is applied to various semiconductor memory devices arranged inside or outside the microcomputer. Can be widely applied.
[0060]
The present invention can be applied on condition that at least a parity check is performed.
[0061]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0062]
That is, it is possible to detect an adjacent bit simultaneous error by performing a logical operation for parity check for each data group of a plurality of bits not adjacent to each other in a memory cell array in which bit allocation is performed for each column. . At this time, since bit allocation is performed for each column, the memory cell array can be prevented from being laid out horizontally, and the word line can be prevented from becoming undesirably long. The access speed of the storage device can be increased.
[0063]
Also, the access speed is sacrificed by configuring the semiconductor memory device including a parity operation circuit that takes in data from the memory cell array in every bit or every plurality of bits in the bit allocation direction and performs a logical operation for parity check. Thus, a semiconductor memory device capable of detecting a simultaneous error between adjacent bits can be configured.
[0064]
A plurality of bit comparison circuits for comparing the first data group and the second data group in bit units, respectively, and based on a logical state of any one bit among the comparison results from the plurality of bit comparison circuits And an OR circuit for obtaining a logical sum of all the bits of the plurality of bit comparison circuits except for the arbitrary one bit in the activated state. By being configured, the OR circuit can be switched between active and inactive using the logic state of any one of the comparison results from the plurality of bit comparison circuits, so that the precharge operation The clock signal for controlling the timing is unnecessary, and the timing margin of the clock signal is also unnecessary. In addition, the number of circuit stages can be reduced as compared with the case where the multi-bit comparison circuit is formed by a static circuit. Accordingly, it is possible to increase the operation speed of the multi-bit comparison circuit, and further to increase the operation speed of the cache memory when such a multi-bit comparison circuit is applied to the synonym check unit of the cache memory. Since a simultaneous error between adjacent bits can be detected without sacrificing the access speed as described above, it is possible to increase the operation speed of the cache memory and improve the reliability of the cache data. When the semiconductor memory device having the above configuration is formed on-chip in a microcomputer as a cache memory, the operation time of the microcomputer and the data processing apparatus including the microcomputer can be shortened by increasing the operation speed of the cache memory. By improving the reliability of the data, it is possible to improve the reliability of the operation processing result.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a parity check unit included in a semiconductor memory device according to the present invention;
FIG. 2 is a block diagram illustrating a configuration example of a computer system to which a microcomputer including the semiconductor memory device is applied;
FIG. 3 is a block diagram illustrating a configuration example of the microcomputer.
FIG. 4 is a block diagram illustrating a configuration example of a cache memory included in the microcomputer.
FIG. 5 is a block diagram illustrating a configuration example of a synonym check circuit included in the cache memory.
FIG. 6 is a circuit diagram of a configuration example of a parity operation circuit included in a parity check unit.
FIG. 7 is a block diagram illustrating a configuration example of a main part in the synonym check circuit.
8 is a circuit diagram of a configuration example of a bit comparison circuit included in FIG. 7;
FIG. 9 is a circuit diagram illustrating a configuration example of an OR circuit included in FIG. 7;
[Explanation of symbols]
10 Cache memory
11 Address translation buffer
12 Control circuit
13 Peripheral modules
31 Microcomputer
32 SDRAM
33 SRAM
34 ROM
35 Peripheral device controller
36 Display controller
38 External storage
40 keyboard
41 Decoder
42 Memory cell array
43 sense amplifier
44 comparison part
45 OR circuit
46 Parity check section
61-1 to 61-n bit comparison circuit
63 Inverter
72 Tag part
73 Data section
74 Comparison part
75 Synonym check section
111-118 EOR
461 First parity operation circuit
462 Second parity operation circuit

Claims (3)

Parity check of read data from the memory cell array can be performed by logical operation of the memory cell array in which bit allocation is performed for each column, and the read data for a plurality of bits in the memory cell array and the corresponding parity bit data. A parity check unit and
A semiconductor memory including a first data group having a multi-bit configuration read from the memory cell array and a comparison unit for comparing, in bit units, a second data group to be compared with the first data group. In the device
The parity check unit includes a parity operation circuit that takes in data from the memory cell array in every bit or every plurality of bits in the bit allocation direction and performs a logical operation for parity check,
The comparison unit is arranged corresponding to a bit configuration of the first data group and the second data group, and each of the plurality of comparison units compares the first data group and the second data group in bit units. A bit comparison circuit;
The arbitrary one bit of the plurality of bit comparison circuits is activated based on the logic state of one arbitrary bit among the comparison results from the plurality of bit comparison circuits, and in the activated state. the semiconductor memory device characterized by comprising: a OR circuit for obtaining the logical sum of all the bits except for. A cache memory that uses virtual address information as search information, an address translation buffer that stores a translation pair for translating a virtual address into a physical address, and a control unit that controls the cache memory and the address translation buffer. In a one-chip microcomputer,
As the cache memory, a microcomputer, characterized in that formed by applying the semiconductor memory device according to claim 1, wherein. A microcomputer according to claim 2, the data processing apparatus characterized by comprising: a main memory accessed by the microcomputer via the bus.

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