JP3674059B2 - Liquid crystal display - Google Patents

Description

[0001]
[Industrial application fields]
[0002]
[Prior art]
In recent years, liquid crystal display devices have been widely used in liquid crystal televisions, personal word processors, personal computers, and the like as low-power consumption and lightweight display devices. In order to display more image information in the future, an increase in the number of pixels and the number of gradations is expected. Such an increase in the number of pixels and the number of gradations means an increase in the capacity of display image information. As a result, the scanning period of one line of the liquid crystal display device is gradually shortened, and the gradation is controlled more finely. .
[0003]
As a method for controlling the gradation of such a liquid crystal display device, there are a frame modulation method for controlling gradation between a plurality of frames, and a pulse height modulation for controlling the pulse height and pulse width of a data signal within a selection period. Conventionally, a method and a pulse width modulation method are used.
[0004]
Among these, the pulse width modulation method divides the horizontal selection period into a plurality of periods according to the number of gradations, and changes the period during which the ON component is added to the data line in the horizontal selection period, that is, the write pulse width, This is a method for performing gradation display. FIG. 15 shows changes in the voltage waveform output to the data line when 3-bit digital data is used as gradation data and the number of gradations is 8 (all ON, all OFF, and 6 halftones). .
[0005]
When the AC signal FR is High, the OFF voltage is always applied during the selection period (Th) when the digital gradation data (D2.D1.D0.) Is (0.0.). Vx1 is output, and as the value of the gradation data increases, the period of Vx2 that is the ON voltage is output longer. When the digital gradation data (D2.D1.D0.) Is in the all-ON state where (1.1.1.), The ON voltage is always output during the selection period (Th).
[0006]
When the AC signal (FR) is LOW, the ON voltage is Vx1 and the OFF voltage is Vx2. Similarly, the larger the gradation data value, the longer the period for outputting the ON voltage. Th in the drawing is a period during which one scanning line is selected, and corresponds to one horizontal scanning period in a normal liquid crystal display device.
[0007]
FIG. 16 is a diagram showing ideal drive voltage waveforms (scanning signals, data signals, and their difference signals) when the pulse width modulation method is applied to a simple matrix. FR in the figure is the alternating signal shown in FIG. A ternary level (Vy1, Vy2, Vy3) is used for the scanning signal (COM), and a binary voltage level (Vx1, Vx2) is used for the data signal (SEG).
[0008]
Here, when halftone information is given as digital gradation data, a corresponding voltage waveform (SEG) is output to the signal electrode. The SEG rises or falls slightly after the rising / falling timing of the AC signal (FR). In FIG. 16, as SEG, a waveform that gives the same gradation display in all the lines is illustrated, but in general, specific rise and fall timings are given for each line.
[0009]
During the selection period (Ts), when the alternating signal (FR) is HIGH, the voltage level of Vy3 is output as the scanning signal, and when it is LOW, the voltage level of Vy2 is output as the scanning signal. Further, Vy1 is output as a scanning signal during the non-selection period (Tns). In FIG. 16, the mth scan electrode is selected during the Ts period and outputs the voltage waveform of COMm shown in the figure. When the scanning signal and the data signal are given in this way, the difference signal (SEG-COMm) becomes a voltage applied to the liquid crystal element. As a result, the effective voltage applied to the liquid crystal element increases as the time (Ton) during which the ON voltage is applied increases, and the effective voltage applied to the liquid crystal element decreases as Ton decreases. In this case, in a normally white type liquid crystal display device (a type in which the transmittance decreases as the voltage increases, the transmittance of the liquid crystal display device increases as the gradation data value increases). Lower.
[0010]
FIG. 16 shows ideal voltage waveforms when it is assumed that there is no wiring resistance of the scanning lines and data lines and no output impedance of the driving IC. In an actual liquid crystal display device, capacitive coupling occurs through the liquid crystal element due to switching of the data voltage on the data line, and voltage distortion of the scanning signal (hereinafter referred to as crosstalk noise) occurs.
[0011]
FIG. 17 is a diagram showing a state in which crosstalk noise is mixed in the scanning signal (COMm) due to capacitive coupling of the data signal (SEGn) and the data signal (SEGl). Due to the crosstalk noise, the effective value of the voltage waveform (SEGn-COMm) applied to the liquid crystal layer is lower than the ideal waveform shown in FIG. 16, and as a result, the transmittance of the liquid crystal display device fluctuates. Resulting in. This transmittance variation is called crosstalk. Crosstalk is further increased due to an increase in driving voltage due to an increase in the number of gradations and an increase in the number of display dots per line, which is an obstacle to good image display.
[0012]
A technique for correcting such crosstalk noise and improving the display quality of the liquid crystal display device has been proposed in the past, and its specific configuration is disclosed in Japanese Patent Laid-Open No. 3-260621. FIG. 18 is a diagram for explaining the operation of the conventional method. The effective voltage of the scanning line is lowered due to the switching of the voltage level of the data line (scanning voltage before correction). In the above-described prior art, in order to correct this decrease in effective voltage, the number of gradation data that is not all ON or all OFF is counted, and based on the counted value, the correction voltage ΔV is set to the voltage level of the scan electrode. To improve the crosstalk.
[0013]
[Problems to be solved by the invention]
However, in the above prior art, when a correction voltage caused by crosstalk noise is added to a scanning signal, it is necessary to set the correction voltage value very finely. Therefore, unless a DA converter having a very high resolution is used. There was a problem of not becoming.
[0014]
Furthermore, the above-described conventional technique has a problem that it cannot be applied to a liquid crystal display device using a non-linear element that can display image information of higher definition and higher quality than a simple matrix liquid crystal display device. It was.
[0015]
Below, the problems of the prior art will be described in detail.
[0016]
Non-linear elements used in liquid crystal display devices include three-terminal elements typified by amorphous silicon TFT elements and two-terminal elements typified by MIM (conductor-insulator-conductor) elements. In either case, the switching function of the nonlinear element is used to increase the number of drive lines and display a large amount of image information.
[0017]
The two-terminal element includes the MIM element described above, a back-to-back diode element, a diode ring element, a varistor element, etc., but each element has non-linear current-voltage characteristics. .
[0018]
FIG. 19 is a diagram showing current-voltage characteristics of an MIM element that is most widely used as a two-terminal nonlinear element. The horizontal axis indicates the voltage applied to the MIM element, and the vertical axis indicates the current. It can be seen that the current-voltage characteristics are nonlinear.
[0019]
FIG. 20 is a diagram showing an equivalent circuit of one pixel of the liquid crystal display device using the MIM element. The driving voltage is VD, the voltage applied to the liquid crystal layer is VLC, and the voltage applied to the MIM element is VMIM. RLC and CLC indicate the resistance and capacitance value of the liquid crystal layer, respectively, and RMIM and CSIM indicate the resistance value and capacitance value of the MIM element, respectively. In an actual liquid crystal display device, the equivalent circuit shown in FIG. 20 is configured in a matrix.
[0020]
FIG. 21 shows an ideal waveform when a liquid crystal panel using a two-terminal nonlinear element is driven. In the case where pulse width modulation is performed using quaternary voltage levels (VY1 to VY4) on the scanning side and binary voltage levels (VX1, VX2) on the data side to suppress leakage during the non-selection period. It is an ideal waveform. The alternating method is an example in which frame inversion and 1-line inversion are performed.
[0021]
The drive waveform of the data signal is the same as that of the simple matrix type liquid crystal display device shown in FIG. When an intermediate value is given as gradation data to the drive system on the data line side, a voltage waveform indicated by SEG in the figure is output to the data line as in the case of FIG.
[0022]
Here, during the selection period (Ts), when the AC signal (FR) is High, the voltage level of VY4 is output as the scanning signal, and when the AC signal (FR) is LOW, the voltage level of VY2 is output as the scanning signal. In the non-selection period (Tns), VY1 or VY2 is output as a scanning signal. As a result, a voltage waveform indicated by COM shown in FIG. 21 is output.
[0023]
When the voltage is applied to the scanning line and the data line in this way, the difference voltage (SEG-COM) between the scanning voltage and the signal voltage is applied to the driving voltage (SEM-COM) applied between the liquid crystal element and the MIM element shown in FIGS. VD).
[0024]
FIG. 22 shows the drive voltage (VD), the voltage applied to the liquid crystal layer (VLC), and the voltage applied to the MIM element (VMIM) when the gradation data is halftone data. When gradation data is displayed, the period when the voltage applied to the MIM element is high is a part where the data voltage is switched to the ON voltage level. In this part, current flows due to the non-linear characteristics of the MIM element, and the voltage rapidly flows to the liquid crystal element. Charged.
[0025]
Here, even when a non-linear element is used, as in the case of the simple matrix liquid crystal display device shown in FIG. 17, crosstalk noise due to switching on the data line side is caused by MIM from the data line to the scanning line side. It mixes through the element and the capacitive part of the liquid crystal layer. Accordingly, the drive voltage (VD) actually applied to the liquid crystal layer and the MIM element is subject to fluctuations due to crosstalk noise, unlike the case of an ideal waveform. As a result, even when the same gradation data is given to a certain pixel, the transmittance varies depending on the display pattern of other pixels. The change in transmittance due to this display pattern will be described in detail with reference to FIGS.
[0026]
FIG. 23 is a diagram showing data displayed on three types of one line, and the pixel whose transmittance is observed is the Nth point. The pattern (a) is halftone data in which all the data of one line is the same, the pattern (b) is halftone data only for the observation pixel, and the other part is all on data. In the pattern (a), there are many identical halftone data, and all the data signals change at the same timing, so a large amount of crosstalk noise occurs. The pattern (b) is in a state in which almost no crosstalk noise is generated because it is only caused by the observation pixel.
[0027]
FIG. 24 is a diagram showing the relationship between the write pulse width (TON period) and the transmittance when the patterns of (a) and (b) shown in FIG. 23 are displayed using a normally white type liquid crystal display device. It is. The horizontal axis indicates the writing pulse width of the observation pixel. When the writing pulse width is 0, it corresponds to the all-OFF state, and the writing pulse width in one scanning period corresponds to the all-ON state. The vertical axis represents the transmittance at each write pulse width. The gradation characteristic (2401) of the pattern (a) in which the driving voltage decreases due to crosstalk noise has higher transmittance than the gradation characteristic (2402) of the observation point of the pattern (b) written with the same pulse width. Thus, it can be seen that crosstalk that deteriorates the image quality occurs. This means that the voltage actually applied to the liquid crystal varies depending on the display pattern of one line.
[0028]
Further, as shown in the pattern (c) shown in FIG. 23, when a halftone different from the observation point is displayed on the data line other than the observation point N, the crosstalk noise generated by the switching of the data signal other than the observation point N is The higher the voltage applied to the MIM element at the observation point N, the greater the influence. This difference in influence will be described with reference to FIG.
[0029]
In FIG. 25, the voltage applied to the MIM element at the observation point N has a waveform indicated by 2501 like the VMIM in FIG. When the drive voltages of the data lines other than the observation point N are 2502 and 2503, the crosstalk noise generated from the data signal 2502 is generated during the period of TE where the voltage applied to the MIM element is at a high level. Compared with the crosstalk noise generated by the data signal 2503, the liquid crystal applied voltage fluctuates greatly. That is, the crosstalk noise of each gradation has a different influence depending on the gradation data to be displayed.
[0030]
Therefore, the method of correcting the voltage on the scanning electrode side by obtaining the average value of crosstalk noise as in the prior art is effective for a simple matrix type liquid crystal display device, but a liquid crystal display using a non-linear element. It is not effective for the apparatus, and gradations that are too large or small are mixed, and the image quality is further deteriorated.
[0031]
As described above, the conventional liquid crystal display device is applied to the liquid crystal elements on the same scanning line due to the voltage distortion of the scanning electrode due to the resistance of the driving electrode of the liquid crystal optical element, the output resistance of the driver IC and the capacitance of the liquid crystal element. There is a problem that the effective voltage fluctuates, the gradation corresponding to the display data cannot be displayed faithfully, and crosstalk occurs.
[0032]
The conventional technique for improving this problem in the simple matrix type liquid crystal display device also has a problem that a DA converter having a high resolution must be used. Furthermore, such a conventional technique not only cannot suppress the crosstalk of the liquid crystal display device having a nonlinear element, but also has a problem of further deteriorating the display quality.
[0033]
Therefore, the present invention has been made for the purpose of providing a liquid crystal display device that solves such problems.
[0034]
[Means for Solving the Problems]
The liquid crystal display device of the present invention includes a plurality of scanning lines, a plurality of data lines, a plurality of liquid crystal elements selected by the scanning lines and the data lines, and a plurality of liquid crystal elements electrically connected to the plurality of liquid crystal elements, respectively. A liquid crystal panel having a non-linear element, a scanning signal driving circuit for supplying a scanning signal to the plurality of scanning lines, and data for supplying a data signal comprising a pulse width modulation ON voltage or an OFF voltage to the plurality of data lines. For the predetermined gradation data indicated by the data signal to be applied to the signal drive circuit and each data line, the number of one gradation data and the number of other gradation data are weighted differently between gradations. Gradation counting means for counting while giving, correction amount determining means for outputting correction amount data corresponding to the counting result of the gradation counting means, and a count loaded with a value corresponding to the correction amount data In the scanning period, the counter counts a clock from a value corresponding to the correction amount data to a value corresponding to the gradation data of the data signal, and at a timing when the value reaches the value corresponding to the gradation data. Applied voltage correction means for switching ON voltage and OFF voltage of the data signal It is characterized by that.
[0035]
In the liquid crystal display device of the present invention, the liquid crystal element is electrically connected to a nonlinear element, and the nonlinear element and the liquid crystal element are electrically connected in series between the data line and the scanning line. Be placed It is characterized by that.
[0039]
[Action]
The present invention d) gradation counting means for counting the gradation data of the digitized data signal; e) correction amount determining means for determining the correction amount of the voltage applied to the liquid crystal element from the counting result of the gradation counting means; F) applied voltage correction means for correcting the voltage applied to the liquid crystal element in accordance with the correction amount determined by the correction amount determination means, each gradation data included in the data signal The voltage applied to the data line can be increased or decreased for each gradation according to the counting result. As a result, the fluctuation of the effective voltage applied to the liquid crystal element that changes depending on the display pattern can be corrected, and crosstalk can be suppressed.
[0040]
Also, The present invention Each of the liquid crystal elements is electrically connected to the nonlinear element, and the nonlinear element and the liquid crystal element are electrically arranged in series between the data line and the scanning line. Compared with a liquid crystal display device of a type, a large-capacity liquid crystal panel can be displayed. Furthermore, the crosstalk of a liquid crystal display device having a non-linear element is greatly affected by the period during which crosstalk noise occurs. Even in such a case, the fluctuation of the effective voltage applied to the liquid crystal element, which varies depending on the display pattern. Can be corrected more effectively than the conventional one, and as a result, crosstalk can be effectively suppressed.
[0041]
further, The present invention Since the gradation counting unit counts gradation data of a data signal applied to the selected liquid crystal element for each of at least one gradation, the display of all gradations can be corrected. In addition, when a plurality of gradations require the same correction, a circuit for counting the correction amount becomes unnecessary, and the circuit scale can be reduced.
[0042]
further, The present invention Since the correction amount determining means weights the count result of the gradation counting means and determines the correction amount, the liquid crystal display device using a nonlinear element as the switching element displays the gradation display by the pulse width modulation method. Even in the case of performing, it is possible to correct the fluctuation of the effective voltage due to the change of the voltage applied to the data line of the liquid crystal element to which the selection voltage is simultaneously applied by the scanning line.
[0043]
further, The present invention Applied voltage correction means (Gradation display basic clock generation circuit) However, since the correction is performed by changing the pulse width of the data signal according to the correction amount determined by the correction amount determining means, it is not necessary to increase the voltage level for driving the liquid crystal panel. Since the circuit can be realized by a simple logic circuit and can be easily integrated into an IC, no cost is required.
[0044]
further, The present invention Applied voltage correction means (Gradation display basic clock generation circuit) However, since the correction is performed by changing the height of the pulse of the data signal according to the correction amount determined by the correction amount determination means, a circuit for correcting the pulse width of the applied voltage of the data line is provided. It becomes unnecessary and the scale of the logic circuit can be reduced.
[0045]
Furthermore, The present invention Applied voltage correction means (Gradation display basic clock generation circuit) However, according to the correction amount determined by the correction amount determination means, the correction is performed by changing both the pulse width and the height of the data signal, so that fine correction is possible and the number of gradations increases. However, crosstalk can be effectively removed.
[0046]
【Example】
[Example 1]
Hereinafter, the present invention will be described with reference to FIG.
[0047]
FIG. 1 is an overall block diagram of the liquid crystal display device of the present invention. The gradation counting unit 101 counts the gradation data 108 based on the mask signal 107 and the data clock 109, and outputs the counting result 111 to the correction amount determining unit 102. Here, the mask signal 107 is active in a period in which the gradation data 108 is valid, that is, a period in which gradation data to be actually displayed is sent.
[0048]
The correction amount determination unit 102 determines the correction amount data 112 based on the data clock 109, the line clock 110, and the counting result 111, and outputs the result to the applied voltage correction unit 103.
[0049]
The applied voltage correction means 103 generates an applied voltage correction signal 113 based on the data clock 109 and the correction amount data 112 and outputs it to the data signal drive circuit 104.
[0050]
The data signal driving circuit 104 stores the gradation data 108 counted by the gradation counting unit 101 in the shift register. The gradation data 108 held in the shift register is output to the data lines X1 to Xm with reference to the line clock 110.
[0051]
The scanning signal driving circuit 105 sequentially outputs a selection voltage from Y1 to the scanning lines Y1 to Yn, and drives the liquid crystal elements of the liquid crystal panel 106 in a time division manner.
[0052]
An embodiment of the present invention will be described in more detail with reference to FIGS.
[0053]
FIG. 2 shows an example in which the present invention is applied to a 640-dot × 480-dot MIM liquid crystal display device that performs gradation display of 8 gradations by a pulse width modulation method.
[0054]
The gradation counting circuit 201 generates a counting result 212 based on the gradation data 209, the mask signal 208, and the data clock 210. The operation of the gradation counting circuit 201 is described with reference to FIGS. This will be described in more detail.
[0055]
FIG. 3 is a block diagram of the gradation counting circuit, and FIG. 6 is a timing chart thereof. A block 312 for counting the correction amount of gradation 7 in FIG. 3 includes a decoder 301, a weighting circuit 302, a logical sum 303, and a counter 304. The gradation data 305 expresses 8 gradations using 3-bit digital data, and a gradation counting block is provided for each gradation data, so the gradation counting circuit is composed of 8 blocks. Is done. An effective period of gradation data is given by a mask signal 306. In the block 312 in which the gradation data corresponds to 7, the decoder 301 decodes the gradation data 305 to 7 by the decoder 302. Decode signal 308 is weighted to three levels by weighting circuit 302. The weighting circuit 302 weights the decoded signal 308 with gradation data 7 to 3 levels at the timing as shown in FIG. 6 and outputs the result. The weighting signal 309 includes a weighting signal 1, a weighting signal 2, and a weighting signal 3. The weighting signal 1 for the gradation data value of 7 is high for all the periods when the gradation data is 7 and the decoding result is high. The weighting signal 2 is high for one clock if the value of the gradation data is seven for two clocks. That is, the period becomes half of the period in which the gradation data is 7. The weighting signal 3 becomes high for one clock when the value of the gradation data is seven for three clocks. In this way, a three-level weighting signal is generated for each gradation data.
[0056]
The logical sum in each gradation counting block is classified into four levels of influences due to the change of gradation pulses of all gradations, and the weighting circuit of the block corresponding to the gradation having a large influence degree is the most. A weighting signal 1 having a large weight is input. The weighting signal 2 is input from the weighting circuit of the gradation classified into the next influence level, and further, the weighting signal 3 is input from the weighting circuit corresponding to the gradation having the next influence, and has the most influence. The gradation weighting signal classified as having a small influence level is not input. For example, if only the weighting signal 1 of gradation 6 is input to the logical sum 303 of the block 312 corresponding to the gradation data value of 7, the output of the logical sum 303 of the block 312 is the enable of the counter 304. Since it is input as the signal 310, the counter 304 is incremented by one in synchronization with the data clock 307 during a period in which the logical sum output is active (active high). When inactive, the output value is held without adding. If the value of gradation data displayed on all the liquid crystal elements to which the selection voltage is applied to the scanning line is 7, the number of liquid crystal elements per scanning line is 640. The value of the count result 311 of the counter corresponding to the block of 7 is 640. If the gradation information 7 is 320 and the gradation 6 is 320, the value of the counting result 311 of the counter corresponding to the block whose gradation data value is 7 is 480.
[0057]
In this way, the counting result 212 (FIG. 2) counted using the gradation counting circuit 201 is input to the correction amount determining circuit 202. The correction amount determination circuit 202 generates a load signal 213, correction amount data 214, and an enable signal 215 based on the counting result 212, the line clock 211, and the data clock 210. The operation of the correction amount determination circuit 202 in FIG. 2 will be described below with reference to FIGS. 4, 5, and 7.
[0058]
4 is a block diagram of a correction amount determination circuit, FIG. 5 is a block diagram of a gradation display basic clock generation circuit, and FIG. 7 is a timing diagram thereof. In FIG. 4, the controller 401 counts gradations to be provided as addresses of the correction amount table ROM 403 based on a line clock 407 that gives the start of one scanning period and a data clock 410 that gives the latch timing of the gradation data. A selection signal 405 for selecting is generated.
[0059]
Based on the value of the 3-bit selection signal 405 output from the controller 401, the selector 402 outputs the count result of one tone among the count results 404 of each tone to the correction amount table ROM 403 as an address. In the correction amount table ROM 403, correction amount data corresponding to the count result of each gradation is written. In the correction amount data ROM 403, the selected count result 406 is input as a lower address, and the selection signal 405 is input as an upper address. Then, the correction amount data ROM 403 outputs correction amount data 409 corresponding to the count result of each gradation.
[0060]
Next, the operation will be described based on the timing chart of the correction amount determination circuit of FIG.
[0061]
First, the falling edge of the line clock 407 is detected, and the selection signal 405 is set to zero. The selection signal 405 is a 3-bit signal having a value of 0 to 7, and the selector 402 selects and outputs the counting result of gradations 0 to 7 corresponding to the value of the selection signal 405 of 0 to 7. In other words, during the period in which the selection signal 405 is 0, a that is the value of the count result 0 is selected and output to the correction amount data ROM 403. Subsequently, in response to the output of the selection signal 405 counted up in synchronization with the data clock 410, the values a, b, c,. Output. By this input, the correction amount data ROM 403 outputs A, B, C,... H as corresponding correction amount data 409. The controller 401 uses a counter 501 shown in FIG. 5 to be described later and loads 0 to 0 as load signals 411 for latching the correction amount data output from the correction amount data ROM 403 in the gradation display basic clock generation circuit 203 in FIG. load7 is output at the timing shown in FIG.
[0062]
In this way, the load signal of each gradation is output in accordance with the timing at which the correction amount data of each gradation is output from the correction amount data ROM 403, and the correction amount data is loaded into the gradation display basic clock generation circuit of FIG. . Further, the counter 501 in FIG. 5 is supplied with a count enable signal 408 from the controller 401 at the timing shown in FIG. 7 in order to stop the counter 501 during the period when the correction amount data 409 is loaded.
[0063]
Next, the gradation display basic clock generation circuit 203 in FIG. 2 will be described. The gradation display basic clock generation circuit 203 generates a gradation display basic clock 216 based on the load signal 213, the correction amount data 214, and the count enable signal 215. Here, the gradation display basic clock will be described with reference to FIG. As shown in FIG. 26, the gray scale display basic clock applies the voltage applied to the data line to each liquid crystal element to which the selection voltage is applied by the scanning line in accordance with the gray scale displayed on each liquid crystal element. It is a signal which generates the timing for. The data signal driving circuit 204 shown in FIG. 2 is supplied with clocks corresponding to the number of display gradations during the scanning period by the gradation display basic clock, and the applied voltage of the data line is changed from the OFF voltage to the ON voltage at the fall of each clock. To change. For example, when displaying a gradation 5 on a certain liquid crystal element, data is generated from the fall of the third gradation display basic clock during the scanning period in which the scanning line connected to the liquid crystal element is applied with the selection voltage. An ON voltage is applied to the line and is changed to an OFF voltage at the end of the scanning period. For other gradations, as shown in FIG. 26, the start timing of the ON voltage application period for displaying each gradation is obtained from the falling edge of the gradation display basic clock corresponding to each gradation. .
[0064]
The operation of the gradation display basic clock generation circuit 203 will be described with reference to FIG.
[0065]
FIG. 5 is a block diagram of the gradation display basic clock generation circuit.
[0066]
As shown in FIG. 5, the gradation display basic clock generation circuit of FIG. 2 has a block 512 including a counter 501 for each gradation and a decoder 502 that generates the output timing of the gradation display basic clock. The signal for generating the timing of the gray scale display basic clock output from each block is ORed with the logical sum 503, the hazard is removed by the D flip-flop 510, and the above gray scale display basic clock 511 is generated. To do.
[0067]
Next, the operation of the gray scale display basic clock generation circuit will be described with reference to the timing chart of FIG.
[0068]
Assuming that the upper block in FIG. 5 corresponds to gradation 7, gradation 6,..., Gradation 0, the gradation 7 counter 501 outputs the counter enable signal 505 output from the controller 401 in FIG. Counts up when is active (active low). In the counter provided for each gradation, the correction amount data 504 is loaded by the load signals 513 to 515 during the period in which the enable signal 505 is inactive, and counting up starts from the value of the correction amount data 504. become. The counter output 506 corresponding to the gradation 7 is decoded by the decoder 502. The decoder 502 generates a timing corresponding to the gradation 7 of the gradation display basic clock. For example, if the value to be decoded is r (that is, the ON voltage starts to be applied in the period of r clock + 1/2 clock from the start of the scanning period in order to display gradation 7), the counter 501 Therefore, as shown in FIG. 8, the signal 507 for generating the timing of the gradation 7 of the gradation display basic clock in the period of rH clocks after the enable signal 505 becomes active, as shown in FIG. To change. In this way, when there is no correction (that is, when correction is not necessary and 0 is loaded as the correction amount data into the counter 501), the timing at the timing of r clocks from the falling edge of the enable signal. In this example, the signal 507 for generating the gray scale display basic clock is changed to high. In this example, the signal 507 is changed to high by an amount corresponding to the H clock (a correction amount corresponding to the gradation of another liquid crystal element on the same scanning line). The timing is advanced.
[0069]
As a result, the timing for applying the ON voltage to the data line can be advanced by H clocks, and the decrease in the effective voltage applied to the liquid crystal element can be corrected. Similarly, if s is decoded at gradation 6, the counter counts up from G, so that the gradation display basic clock gradation 6 changes to the s-G clock period from the fall of the enable signal. The corresponding timing is generated, and the application period of the ON voltage of the data line is increased for the period of G clock. The same applies to gradations 5 to 0 below.
[0070]
The timing signals corresponding to the gradations of the eight gradation display basic clocks are logically summed with a logical sum 503, latched at the falling edge of the data clock 508 by the D flip-flop 510, and hazards are eliminated by decoding. The key is output to the data signal driving circuit 204 of FIG.
[0071]
Next, operations of the data signal driving circuit 204 and the scanning signal driving circuit 205 will be described with reference to FIGS. The data signal driving circuit 204 takes in the gradation data 209 by the data clock 210 and obtains the timing for applying the ON voltage by the gradation display basic clock 216 in synchronization with the line clock 211. Further, VDD and VEE input from the drive voltage generation circuit 206 are selected by the alternating signal 217, and an ON voltage and an OFF voltage are applied to the data line. The scanning signal driving circuit 205 applies a selection voltage to the scanning lines sequentially for each scanning line in synchronization with the line clock 211. A voltage as shown in FIG. 9 is applied to the MIM element and the liquid crystal element.
[0072]
The portion of the data line Xi painted in gray is the correction voltage. In the scanning period of T1, the writing pulse width correction in the period of ΔT is performed.
[0073]
As described above, an ON voltage corrected in consideration of fluctuations in effective voltage (decrease in this embodiment) due to changes in the voltage applied to the data lines of the liquid crystal elements to which the selection voltage is simultaneously applied by the scanning lines is applied. By doing so, it is possible to apply an effective voltage appropriate for displaying gradations on the liquid crystal element, which eliminates the fluctuation of the effective voltage for each scanning line and effectively prevents crosstalk caused by the display pattern. As a result, it is possible to display a clear image without display unevenness.
[0074]
In this embodiment, correction is performed for each gradation, but since there is little difference between the gradations in the effective voltage variation due to the display pattern between the gradations where the on-voltage application time of the data line is close, this is the case. It is also possible to correct for each of a plurality of gradations. In this case, the circuit scale can be reduced. The counting result weighting method can be handled by changing the number of weighting levels according to the required display quality.
[0075]
Further, not only the MIM element of the present embodiment but also a liquid crystal panel using another nonlinear element having a nonlinear current-voltage characteristic as a switching element can be similarly corrected.
[0076]
Furthermore, since the present invention corrects the voltage applied to the data line in one line, the present invention is not limited to the one-line inversion driving of the present embodiment, and has the same effect in driving such as frame inversion and multiple line inversion.
[0077]
Although this embodiment is a liquid crystal display device for displaying 8 gradations, the present invention is not limited to 8 gradations and can be applied even when the number of display gradations is increased to 16, 32, 64. In such a case, a circuit provided for eight gradations in this embodiment may be provided according to gradations 16, 32, and 64.
[0078]
Here, it is conceivable that if a circuit corresponding to all gradations is provided, the circuit scale increases. However, when the number of gradations increases, the timing at which the ON voltage starts to be applied to the data line between adjacent gradations becomes closer, so the influence on the display due to crosstalk noise hardly changes between neighboring gradations. Come. Therefore, by considering a plurality of gradations as one block and configuring the circuit, an appropriate circuit scale can be maintained even if the number of gradations increases.
[0079]
[Example 2]
Next, Example 2 will be described with reference to FIGS. Similar to the first embodiment, the present invention is applied to an MIM liquid crystal display device of 640 dots × 480 dots and 8-gradation display.
[0080]
10 is a block diagram of the present embodiment, FIG. 11 is a block diagram of a gradation voltage correction circuit, and FIG. 12 is an applied voltage waveform diagram.
[0081]
The gradation counting circuit 1001 and the correction amount determining circuit 1002 operate in the same manner as in the first embodiment. The gradation counting circuit 1001 generates a gradation counting result 1012 from the gradation data 1008, the data clock 1009, and the mask signal 1011. The correction amount determination circuit 1002 generates a load signal 1013 and correction amount data 1014 based on the data clock 1009, the line clock 1010, and the count result 1012. The gradation voltage correction circuit 1003 generates a gradation voltage 1016 (a gradation voltage for eight gradations) based on the data clock 1009, the load signal 1013, and the correction amount data 1014.
[0082]
The operation of the gradation voltage correction circuit 1003 will be described with reference to FIG. The correction amount data 1104 is latched by the data clock 1105 when the load signal 1106 is active in the latch circuit 1101 corresponding to the gradation 0. Subsequently, the correction amount data 1104 corresponding to gradation 1 is latched by the load signal 1107, and finally, the correction amount data 1104 of gradation 7 is latched by the load signal 1108. The latched correction amount data is loaded into the D flip-flop 1113 in the next stage by the line clock 1112, and the gradation voltage 1109 corresponding to the gradation 0 is changed from the D / A converter 1102 to the gradation 1 according to the value. A corresponding gradation voltage 1110 and a gradation voltage 1111 corresponding to gradation 7 are output.
[0083]
The data signal driving circuit 1004 takes in the gradation data 1008 by the mask signal 1011 and the data clock 1009, determines the application timing of the ON voltage of the data line by the line clock 1010 and the gradation display basic clock 1015, and further adds eight lines. The gradation voltage is selected, and the application voltage level and the ON voltage application timing are determined. As shown in the applied voltage waveform diagram of FIG. 12, in the period of T1, the write voltage is applied by increasing the ON voltage applied to the data line by ΔV of the grayed portion and applied to the liquid crystal element. To compensate for fluctuations in the effective voltage. In this manner, the write voltage is corrected by changing the correction voltage according to the change in the effective voltage of each gradation.
[0084]
As described above, the effective voltage can be applied to the liquid crystal element by correcting the decrease in the effective voltage according to the ON voltage level of the data line, thereby eliminating the fluctuation of the effective voltage for each scanning line. Thus, the crosstalk generated by the display pattern can be effectively suppressed, and as a result, a clear image without display unevenness can be displayed.
[0085]
Example 3
Next, Example 3 will be described with reference to FIGS. Similar to the first embodiment, the present invention is applied to an MIM liquid crystal display device of 640 × 480 dots and 8-gradation display. FIG. 13 is a block diagram of this embodiment, and FIG. 14 is an applied voltage waveform diagram.
[0086]
The gradation counter circuit 1301, the correction amount determination circuit 1302, the gradation display basic clock generation circuit 1303, and the gradation voltage correction circuit 1303 operate in the same manner as in the first embodiment, and the gradation voltage correction circuit 1304, the data The signal drive circuit 1305 operates in the same manner as in the second embodiment. The gradation count circuit 1301 generates a gradation count result 1312 based on the gradation data 1308, the data clock 1309, and the mask signal 1311. The correction amount determination circuit 1302 generates a load signal 1313 and correction amount data 1314 based on the data clock 1309, the line clock 1310, and the counting result 1312. The gradation display basic clock generation circuit 1303 generates a gradation display basic clock 1315 based on the data clock 1309, the load signal 1313, and the correction amount data 1314, and the gradation voltage correction circuit 1304 arranged in parallel therewith. Generates gradation voltages 1316 to 1318 (voltages corresponding to eight gradations) based on the data clock 1309, the load signal 1313, and the correction amount data 1314. The data signal driving circuit 1305 takes in the gradation data 1308 with the mask signal 1311 and the data clock 1309, determines the application timing of the ON voltage of the data line based on the line clock 1310 and the gradation display basic clock 1315, and further adds eight lines. The gradation voltage is selected to determine the applied voltage level. As shown in the applied voltage waveform of FIG. 14, in the period of T1, the pulse width is increased by ΔT period and the pulse height is increased by ΔV only in the portion where the ON voltage applied to the data line is grayed out. Then, a write correction voltage is applied to correct the fluctuation of the effective voltage applied to the liquid crystal element.
[0087]
In this manner, the write voltage is corrected by changing the correction voltage according to the change in the effective voltage of each gradation.
[0088]
As described above, by correcting the decrease in effective voltage according to the width and height of the applied voltage on the data line, an appropriate effective voltage can be applied to the liquid crystal element. Voltage fluctuations are eliminated, and crosstalk caused by the display pattern can be effectively suppressed. As a result, a clear image without display unevenness can be displayed.
[0089]
Furthermore, since the configuration of the present embodiment is corrected by changing both the width and height of the ON voltage, finer correction is possible, and as a result, the configuration of the configuration of the first or second embodiment is possible. Crosstalk can be more effectively suppressed than in the case.
[0090]
【The invention's effect】
The liquid crystal display device of the present invention can effectively suppress crosstalk caused by a display pattern, and as a result, has an effect of displaying a clear image without unevenness.
[Brief description of the drawings]
FIG. 1 is a block diagram of the present invention.
FIG. 2 is a block diagram of the first embodiment.
FIG. 3 is a block diagram of a gradation counting circuit according to the first embodiment.
FIG. 4 is a block diagram of a correction amount determination circuit according to the first embodiment.
FIG. 5 is a block diagram of a gradation display basic clock generation circuit according to the first embodiment.
FIG. 6 is a timing chart of the gradation counter circuit according to the first embodiment.
FIG. 7 is a timing chart of the correction amount determination circuit according to the first embodiment.
FIG. 8 is a timing chart of the gradation display basic clock generation circuit according to the first embodiment.
FIG. 9 is a waveform diagram of a liquid crystal driving voltage according to the first embodiment.
10 is a block diagram of Embodiment 2. FIG.
FIG. 11 is a block diagram of a gradation voltage correction circuit according to a second embodiment.
12 is a waveform diagram of a liquid crystal driving voltage in Example 2. FIG.
FIG. 13 is a block diagram of the third embodiment.
14 is a waveform diagram of a liquid crystal driving voltage in Example 3. FIG.
FIG. 15 is an explanatory diagram of gradation display by a pulse width modulation method.
FIG. 16 is an ideal waveform diagram of pulse width modulation in a simple matrix.
FIG. 17 is a waveform diagram showing mixing of crosstalk noise in a simple matrix.
FIG. 18 is a diagram showing current-voltage characteristics of the MIM element.
FIG. 19 is an equivalent circuit diagram of one pixel of a liquid crystal display device using an MIM element.
FIG. 20 is an explanatory diagram of crosstalk of a conventional liquid crystal panel.
FIG. 21 is an applied voltage waveform diagram of a conventional liquid crystal panel.
FIG. 22 is an explanatory diagram of the influence of voltage distortion caused by halftone display.
FIG. 23 is a diagram showing data displayed on three types of one line.
FIG. 24 is a graph showing gradation characteristics indicating the relationship between a write pulse width and transmittance.
FIG. 25 is a diagram for explaining the degree of influence of the voltage applied to the MIM on the crosstalk noise.
FIG. 26 is a diagram showing a relationship between a gray scale display basic clock and a voltage applied to a data line.
[Explanation of symbols]
101. Tone counting means
102. Correction amount determination means
103. Applied voltage correction means
104. Data signal drive circuit
105. Scanning signal drive circuit
106. LCD panel
107. Mask signal
108. Gradation data
109. Data clock
110. Line clock
111. Count result
112. Correction amount data
113. Applied voltage correction signal
201. Tone counting circuit
202. Correction amount determination circuit
203. Gradation display basic clock generation circuit
204. Data signal drive circuit
205. Scanning signal drive circuit
206. Drive voltage generation circuit
207. MIM LCD panel
208. Mask signal
209. Gradation data
210. Data clock
211. Line clock
212. Count result
213. Load signal
214. Correction amount data
215. Enable signal
216. Gradation display basic clock
217. AC signal
301. decoder
302. Weighting circuit
303. Logical sum
304. counter
305. Gradation data
306. Mask signal
307. Data clock
308. Decoding result
309. Weighted signal input to other tone blocks
310. Enable signal for counter 304
311. Count results for each gradation
312. Tone counting block
401. controller
402. selector
403. Correction amount table ROM
404. Count result
405. Selection signal
406. Count result selected by selection signal 405
407. Line clock
408. Gray scale display basic clock counter enable signal
409. Correction amount data
410. Data clock
411. Load signal
501. counter
502. decoder
503. Logical sum
504. Correction amount data
505. Enable signal
506. Counter output
507. Decode signal
508. Data clock
509. OR output
510. D flip-flop
511. Gradation display basic clock
513. Gradation 7 load signal
514. Tone 6 load signal
515. Gradation 0 load signal
1001. Tone counting circuit
1002. Correction amount determination circuit
1003. Gradation voltage correction circuit
1004. Data signal drive circuit
1005. Scanning signal drive circuit
1006. Drive voltage generation circuit
1007. MIM LCD panel
1008. Gradation data
1009. Data clock
1010. Line clock
1011. Mask signal
1012. Count result
1013. Load signal
1014. Correction amount data
1015. Gradation display basic clock
1016. Gradation voltage
1101. Latch circuit
1102. D / A converter
1103. Gradation 0 voltage correction block
1104. Correction amount data
1105. Data clock
1106. Load signal corresponding to gradation 0
1107. Load signal corresponding to gradation 1
1108. Load signal corresponding to gradation 7
1109. Correction voltage for gradation 0
1110. Tone 1 correction voltage
1111. Gradation 7 correction voltage
1112. Line clock
1113. D flip-flop
1301. Tone counting circuit
1302. Correction amount determination circuit
1303. Gradation display basic clock generation circuit
1304. Data signal drive circuit
1305. Scanning signal drive circuit
1306. Drive voltage generation circuit
1307. MIM LCD panel
1308. Gradation data
1309. Data clock
1310. Line clock
1311. Mask signal
1312. Count result
1313. Load signal
1314. Correction amount data
1315. Gradation display basic clock
1316. Gradation voltage

Claims (1)

A liquid crystal panel having a plurality of scanning lines, a plurality of data lines, a plurality of liquid crystal elements selected by the scanning lines and the data lines, and a plurality of non-linear elements respectively electrically connected to the plurality of liquid crystal elements; ,
A scanning signal driving circuit for supplying a scanning signal to the plurality of scanning lines;
A data signal driving circuit for supplying a data signal comprising an ON voltage or an OFF voltage of a pulse width modulation system to the plurality of data lines;
For predetermined gradation data indicated by the data signal to be applied to each data line, the number of one gradation data and the number of other gradation data are counted while assigning different weights between gradations. Gradation counting means;
Correction amount determining means for outputting correction amount data corresponding to the counting result of the gradation counting means;
It has a counter loaded with a value according to the correction amount data, and in the scanning period, the counter counts a clock from a value according to the correction amount data to a value according to the gradation data of the data signal, Applied voltage correction means for switching the ON voltage and the OFF voltage of the data signal at a timing when a value corresponding to the gradation data is reached;
A liquid crystal display device comprising: a.

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