JP3674312B2 - Image display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention includes a plurality of image processing units capable of outputting image signals obtained by performing predetermined processing on input signals such as received television signals and character signals for a display unit such as a large video display device. The present invention relates to an image display device capable of switching output states of a plurality of image processing units.
[0002]
[Prior art]
FIG. 14 shows an image display device having a plurality of conventional image processing units. Here, an example in which one image display apparatus includes one display unit Y capable of displaying an image and two image processing units X1 and X2 is shown. In FIG. 14, X1 is a first image processing unit, X2 is a second image processing unit, Y is a display unit for displaying an image, and Z is a connection between a plurality of image processing units X1, X2 and a display unit Y. The conventional image display device is composed of these four parts.
[0003]
In the image processing units X1 and X2, the input television signal and the character signal for displaying a flow character or the like are subjected to processing such as A / D conversion, and then in a dedicated format suitable for the display unit Y. A differential signal is sent to the switching circuit Z.
[0004]
An image signal output from the two image processing units X1 and X2 and a switching signal generated by a switch or the like are input to the switching circuit Z, and one of the image processing units X1 and X2 is input according to the switching signal. One signal is selected and output to the display unit Y. The display unit Y causes the light emitting element 11 such as a CRT or LED to emit light based on the transmitted signal, and displays the television signal and the character signal.
[0005]
The image processing units X1, X2 are RGB decoding circuits 1a, 1b, R (red), G (green), B (decomposing a television signal into three primary colors R (red), G (green), and B (blue). A / D conversion circuits 2a and 2b that convert analog signals of blue) into digital signals, memories 3a and 3b that store digitally converted image signals, and differential that converts TTL (Transistor Transistor Logic) signals into differential signals Drivers 24a and 24b, communication circuits 5a and 5b that receive character signals, character development circuits 6a and 6b that develop character codes into dot patterns, and memory control circuits 7a and 7b that control writing and reading of memories 3a and 3b It has.
[0006]
The switching circuit Z is a differential receiver 18a, 18b that returns a differential signal to a TTL signal, a selector 19 that selects and outputs one signal from two signals, and a differential that outputs a differential signal to the display unit Y. The driver 20 is configured.
[0007]
The display unit Y includes a differential receiver 8, a memory 9 for storing image signals sent from the switching circuit Z, a control circuit 21 for controlling writing and reading of the memory 9, and light emitting elements 11 arranged in an array. And a driver 10 that directly drives the light emitting element 11.
[0008]
Next, the operation of the image display apparatus will be described. In FIG. 14, the first and second television signals respectively input to the image processing units X1 and X2 are first converted into three primary colors of R (red), G (green), and B (blue) by the RGB decoding circuits 1a and 1b. Disassembled. Next, after digital conversion to a predetermined number of bits by the A / D conversion circuits 2a and 2b, the data is written in the memories 3a and 3b.
[0009]
On the other hand, the first and second character signals for displaying the time and the sink character are received by the communication circuits 5a and 5b and developed into a dot pattern by the character development circuits 6a and 6b, and then the memory control circuit 7a, 7b is written into the memories 3a and 3b and is combined with the first and second television signals, respectively.
[0010]
The image data in which the TV signal and the character signal are combined is read out from the memories 3a and 3b in a predetermined order matching the pixel arrangement of the display unit Y by the memory control circuits 7a and 7b, and the display position of the image data is determined. A designated line address is added, and thereafter, the TTL signal is converted into a differential signal by the differential drivers 24 a and 24 b and is output to the switching circuit Z. Here, the reason why the TTL signal is converted to the differential signal is that the differential signal is more suitable for long-distance transmission than the TTL signal.
[0011]
FIG. 15 shows a transmission format of the image data. In FIG. 15, the line address is data for specifying the vertical position in the display unit Y of the image data 1 to n transmitted subsequently to the line address, and the line address corresponding to the highest line is 0. Yes, it will gradually increase downward. The image data is data obtained by combining a television signal written in the memories 3a and 3b and a character signal.
[0012]
Here, the first image data 1 is displayed at the left end of the display unit, and the image data n is displayed at the right end. A series of data groups from the line address to the image data 1 displayed at the left end of the screen transmitted subsequently to the image data n displayed at the right end of the screen is hereinafter referred to as a data block. Further, the data block completion signal in FIG. 15 is a signal for indicating that the last image data n of this data block has been transmitted.
[0013]
The differential drivers 24a and 24b have two output terminals, a non-inverting output terminal that outputs a signal having the same logic as the input signal and an inverting output terminal that outputs an inverted logic signal.
[0014]
Further, the differential receivers 18a and 18b have two input terminals of a non-inverting input and an inverting input and one output terminal, and the potentials of the non-inverting input and the inverting input are compared. Outputs a level, and outputs a low level if the inverting input is higher.
[0015]
In the switching circuit Z, the differential signals sent from the two image processing units X1 and X2 are received by the differential receivers 18a and 18b and then input to the selector 19. The selector 19 receives a switching signal generated by a manual changeover switch or the like. According to the switching signal, for example, the image signal of the first image processing unit X1 is selected if the level is low, and if the level is high. The image signal of the second image processing unit X2 is selected. The selected image signal is again converted into a differential signal by the differential driver 20 and sent to the display unit Y.
[0016]
In the display unit Y, the image signal is received by the differential receiver 8, and the received image signal is written to the address specified by the line address on the memory 9 by the control circuit 21. The image signal written in the memory 9 is read out by the control circuit 21 a predetermined number of times during the field period of the television signal and sent to the driver 10 of the light emitting element. The sent image signal is converted into a voltage necessary for the light emitting element 11 by the driver 10, so that the light emitting element 11 emits light with a luminance corresponding to the image signal.
[0017]
Through the above operation, the display unit Y displays the image signal stored in the memory 3a or 3b of one of the image processing units X1 and X2 selected by the switching signal. Then, different television signals and character signals can be input to the respective image processing units X1 and X2, and these can be alternately switched and displayed.
[0018]
Here, a display screen when the images from the image processing units X1 and X2 are switched in the conventional image display device will be described. FIG. 16 shows the output image signal of each part at the time of switching, and shows the output image signal of the first image processing unit X1, the second image processing unit X2, and the switching circuit Z from the top. FIG. 17 is a display image at that time, and shows images output from the first image processing unit X1, the second image processing unit X2, and the switching circuit Z in order from the left. Actually, the image displayed on the display unit Y is an image output from the switching circuit Z at the right end.
[0019]
As shown in FIG. 16, when the switching signal changes from low level to high level immediately after the image data 6 in the output image signal of the first image processing unit X1, the image signal input to the switching circuit Z is In the middle of the data block, the output image signal of the first image processing unit X1 is switched to the output image signal of the second image processing unit X2.
[0020]
For this reason, the data after the image data 2 in the output image signal of the second image processing unit X2 is written at a line address different from the original line address, and thus displayed at an incorrect position in the vertical direction.
[0021]
Further, since the data after the image data 2 of the second image processing unit X2 is written after the image data 1 to 7 of the first image processing unit X1, it is displayed at an incorrect position also in the horizontal direction. The
[0022]
As a result, as shown in the display image 8 in FIG. 17, the image data immediately after the switching (here, the uppermost part of the circle) is displayed at a position that is different from the position where it should originally be displayed, both vertically and horizontally. End up. Here, the switching signal in FIG. 17 represents a state of changing from a low level to a high level in the middle of the data block.
[0023]
In addition, since the image signal is switched in the middle of the field regardless of the vertical synchronization signal, the image is interrupted in the middle of scanning as shown in the display image 8 in FIG. There was a problem that the image started from the middle.
[0024]
[Problems to be solved by the invention]
In the conventional example, since the image data is output to the display unit Y through the common switching circuit Z, when the switching circuit Z fails, it becomes impossible to switch images from a plurality of image processing units. The image of could not be displayed.
[0025]
Further, as shown in FIG. 16, since the connection between the display unit Y and the image processing units X1 and X2 is switched in the middle of the data block, the image data immediately after the switching is displayed as shown in the display image 8 in FIG. Is displayed at a position different from the upper and lower sides and the left and right from the position where it should originally be displayed, so that the human eye feels that the image is disturbed for a moment.
[0026]
Also, as shown in FIG. 17, since switching is performed in the middle of the field regardless of the vertical synchronizing signal, the image is interrupted as shown in the display image 8, and a part of the other screen is displayed from the middle, or the display image 9 Because it starts from the middle of the screen like this, it feels as if the image is disturbed for the moment with the naked eye.
[0027]
Further, in the conventional example, since the image processing units X1 and X2 are manually switched, when the power circuit of the image processing unit X1 or X2 outputting the image signal fails, the discoverer manually changes the other. The image could not be displayed until switched to the image processing unit X2 or X1.
[0028]
The present invention has been made to solve the above problems, and can switch image signals from a plurality of image processing units without requiring a common switching circuit, and if the display unit is normal. An object of the present invention is to obtain an image display device capable of continuing display as long as all of the plurality of image processing units do not fail.
[0029]
Another object of the present invention is to obtain an image display device that does not cause disturbance in a display image when switching image signals from a plurality of image processing units.
[0030]
It is another object of the present invention to provide an image display device that can eliminate the need for manual switching to another image processing unit by a fault finder when a power supply circuit of the image processing unit fails.
[0031]
[Means for Solving the Problems]
An image display device according to the present invention includes a plurality of image processing units each having output control means for switching an output of an image signal between an output state and a non-output state based on a switching signal, and an image processing unit in an output state And a display unit for displaying the output image signal.
[0032]
In addition, any one of the plurality of image processing units is in an output state, and the other image processing units are in a non-output state.
[0033]
In addition, when the output state is switched from the image processing unit in the output state to another image processing unit, all outputs of the plurality of image processing units are once at the same level.
[0034]
The output state is switched from the image processing unit in the output state to another image processing unit in accordance with the timing of the data block completion signal of the image processing unit in the output state.
[0035]
Further, the output of the image processing unit in the output state becomes a predetermined level in accordance with the timing of the data block completion signal of the image processing unit in the output state, and then all the outputs of the plurality of image processing units are the predetermined level. The other image processing unit is switched to the output state in accordance with the timing of the data block completion signal of the other image processing unit.
[0036]
Further, the timing of the vertical synchronizing signal is used instead of the timing of the data block completion signal.
[0037]
In addition, a current limiting resistor is provided between the display unit and each of the plurality of image processing units, and when one of the plurality of image processing units fails, the other image processing unit is caused by a short-circuit current. An image signal can be output without failure.
[0038]
Each of the plurality of image processing units detects the power supply voltage of the other image processing unit, and automatically outputs each image signal to the display unit when the power supply voltage of the other image processing unit is cut off. It is characterized by having a circuit to perform.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows a circuit configuration of Embodiment 1 of the present invention.
In FIG. 1, X1 is a first image processing unit, X2 is a second image processing unit, and Y is a display unit. The image display apparatus according to the present embodiment includes these three parts.
[0040]
The image processing units X1 and X2 respectively output first and second television signals, first and second character signals for displaying a sink character, and an image signal to be output to the display unit Y. A switching signal for selecting one of the processing units X1 and X2 is input.
[0041]
Here, the television signal and the character signal are subjected to processing such as A / D conversion in the image processing units X 1 and X 2, and are then transmitted to the display unit Y as a differential signal in a dedicated format suitable for the display unit Y. Sent. Here, the output image signals of the two image processing units X1 and X2 are short-circuited, and either one of the image processing units X1 or X2 is selected according to the switching signal, and the differential of the other image processing unit X2 or X1 is selected. The driver (ie, output control means) 4b or 4a is configured to be in a high impedance state (ie, a non-output state). The display unit Y displays the image signal including the television signal and the character signal by causing the light emitting element 11 including the CRT and the LED to emit light based on the transmitted signal.
[0042]
The image processing units X1, X2 are RGB decoding circuits 1a, 1b, R (red), G (green), B (decomposing a television signal into three primary colors R (red), G (green), and B (blue). A / D conversion circuits 2a and 2b that convert analog signals of blue) into digital signals, memories 3a and 3b that store digitally converted image signals, differential drivers 4a and 4b that convert TTL signals into differential signals, and characters Communication circuits 5a and 5b that receive signals, character expansion circuits 6a and 6b that expand character codes into dot patterns, and memory control circuits 7a and 7b that control memory writing and reading.
[0043]
The display unit Y includes a differential receiver 8, a memory 9 for storing image signals sent from the switching circuit Z, a control circuit 21 for controlling writing and reading of the memory 9, and light emitting elements 11 arranged in an array. And a driver 10 that directly drives the light emitting element 11.
[0044]
The operation of the image display device in the first embodiment will be described below. In FIG. 1, the television signals input to the image processing units X1 and X2 are first separated into three primary colors R (red), G (green), and B (blue) by the RGB decoding circuits 1a and 1b, and then A After the digital conversion to a predetermined number of bits by the / D conversion circuits 2a and 2b, the data is written into the memories 3a and 3b by the memory control circuits 7a and 7b.
[0045]
On the other hand, the character signal for displaying the time and the sink character is received by the communication circuits 5a and 5b, developed from the character code into a dot pattern, and then written to the memories 3a and 3b by the memory control circuits 7a and 7b. Are combined with the television signal.
[0046]
The image data obtained by combining the television signal and the character signal is read from the memories 3a and 3b by the memory control circuits 7a and 7b in a predetermined order corresponding to the pixel arrangement of the display unit Y, and the display position of the image data is determined. After the specified line address is added, it is output to the display unit Y via the differential drivers 4a and 4b.
[0047]
Here, the configuration of the differential drivers 4a and 4b is shown in FIG. It has two input terminals for inputting an input signal and an output control signal, and two output terminals for outputting a non-inverted output signal and an inverted output signal.
[0048]
When the output control signal is set to a high level, a signal having the same logic as the input signal is output as a non-inverted output signal, and a signal having a different logic is output as an inverted output signal. If the output control signal is set to a low level, the two output terminals are in a high impedance state regardless of the input signal. FIG. 3 shows the relationship between the input signals and output signals of the differential drivers 4a and 4b.
[0049]
FIG. 4 shows wiring between the differential drivers 4a and 4b of the image processing units X1 and X2 and the differential receiver 8 of the display unit Y. The outputs of the differential signals of the first image processing X1 and the second image processing X2 are short-circuited and connected to the differential receiver 8 of the display unit Y.
[0050]
Here, the differential receiver 8 has two input terminals for inputting the non-inverted output signal and the inverted output signal, and one output terminal. The differential receiver 8 compares the potentials of the non-inverted output signal and the inverted output signal, and If the inverted output signal is higher, a high level is output, and if the inverted output signal is higher, a low level is output.
[0051]
Since the wiring is performed as described above, the first output control signal φ1 input to the differential driver 4a of the first image processing unit is set to the high level to output the image signal, and the differential of the second image processing unit. The image signal of the first image processing unit X1 can be output to the display unit Y by setting the second output control signal φ2 input to the driver 4b to a low level to be in a high impedance state.
[0052]
If both output control signals φ1 and φ2 are inverted, the image signal of the second image processing unit X2 can be output to the display unit.
[0053]
FIG. 5 shows the timing when switching from the first image processing unit to the second image processing unit.
[0054]
Here, if both output control signals φ1 and φ2 are mistakenly set to low level, the outputs of both differential drivers 4a and 4b are in a high impedance state, so that the signal level input to the differential receiver 8 of the display unit. Becomes indefinite and an incorrect signal is transmitted.
[0055]
Further, when both output control signals φ1 and φ2 are set to high level and the output levels of the short-circuited differential drivers 4a and 4b are different, a short-circuit current flows and the differential drivers 4a and 4b may be damaged. is there. In addition, the voltage level received by the differential receiver 8 of the display unit becomes indefinite, and an incorrect signal is transmitted.
[0056]
Here, the relationship among the output control signal, the input image signal, the non-inverted output, the inverted output, and the output signal of the differential receiver (that is, the signal received by the display unit) is shown in FIG.
[0057]
In the display unit Y, the image signal is received by the differential receiver 8 and written by the control circuit 21 at an address specified by the line address on the memory 9. The signal written in the memory 9 is read out a predetermined number of times during the field period of the television signal by the control circuit 21 and sent to the driver 10 of the light emitting element. The driver 10 converts the input signal into a voltage necessary for the light emitting element 11 and turns on the light emitting element 11, so that the light emitting element 11 emits light with a luminance corresponding to the image signal.
[0058]
Therefore, in the present embodiment, the image signal from the plurality of image processing units X1 and X2 can be switched and displayed with the configuration without the common switching circuit in the prior art, and the display unit Y should be normal. For example, as long as all of the plurality of image processing units X1 and X2 do not break down, display of any one of the images can be continued. It is also possible to input different television images and character information to each of the image processing units X1 and X2 and switch them alternately to be displayed.
[0059]
In the present embodiment, the number of image processing units is two, but the number of image processing units may be three or more. In this case, the number of bits of the switching signal is set to multiple bits. This is possible.
[0060]
Specifically, the switching signal is 2 bits, the first image processing unit X1 in the case of (0, 0), the second image processing unit X2, (1, 0) in the case of (0, 1). In this case, the third image processing unit may be selected, and in the case of (1, 1), the fourth image processing unit may be selected.
[0061]
Similarly, it is possible to select from a larger number of image processing units by increasing the number of bits of the switching signal.
[0062]
Embodiment 2. FIG.
FIG. 7 shows a circuit configuration of the second embodiment of the present invention.
The image display apparatus according to the second embodiment forcibly applies the image data output from the memories 3a and 3b to the image processing units X1 and X2, respectively, in addition to the components of the image display apparatus according to the first embodiment. And gate control circuits 13a and 13b that generate first and second gate signals ψ1 and ψ2 and first and second output control signals φ1 and φ2 based on the switching signals. It is equipped. The display unit Y has the same configuration as that of the first embodiment.
[0063]
FIG. 8 shows a circuit configuration of the gate circuit in the second embodiment of the image display apparatus according to the present invention. As shown in FIG. 8, image data 1 to n output from the memories 3a and 3b and two types of latch clocks (that is, an image data latch clock and a line address latch clock) are input to the gate circuits 12a and 12b. The The gate circuits 12a and 12b are composed of AND circuits. If the first and second gate signals ψ1 and ψ2 are at a low level, the image data 1 to n and the above two types of latch clocks are forcibly set to a low level. Thus, the signal is output to the differential drivers 4a and 4b.
[0064]
FIG. 9 shows a circuit configuration of the switching control circuit in the second embodiment of the image display apparatus according to the present invention. As shown in FIG. 9, in the switching control circuits 13a and 13b, the switching signals are latched by the first and second vertical synchronization signals and the first and second basic clocks, so that the first, Second gate signals ψ1, ψ2 and first and second output control signals φ1, φ2 are generated. The first and second basic clocks are clock signals for operating the circuits in the image processing units X1 and X2 that are output from a clock generation circuit (not shown) included in the image processing units X1 and X2. is there.
[0065]
Next, the operation will be described by taking as an example a case where the switching signal changes from the low level to the high level and changes from the first image processing unit X1 to the second image processing unit X2. A timing chart at this time is shown in FIG.
[0066]
First, at the timing of the first vertical synchronization signal immediately after the change of the switching signal (that is, at the time indicated by A in the figure), the first gate signal ψ1 is set to the low level and output from the gate circuit 12a. The output of the image data 1 to n is fixed at the low level. At this time, the differential driver 4b of the second image processing unit is in a high impedance state. Therefore, the non-inverted output signals of the short-circuited differential drivers 4a and 4b become low level and the inverted output signal becomes high level, that is, the image signal fixed at low level is output to the differential receiver 8. Will be.
[0067]
Here, since the first vertical synchronization signal is synchronized with the first data block completion signal, the image is not interrupted in the middle of the data block. Further, since the gate circuit 12a fixes the image data 1 to n at the low level at the same timing as the first vertical synchronizing signal, the image is displayed as in the case of using the conventional technique shown in the image 8 in FIG. The image at the time when the switching signal is changed without being interrupted can be displayed in the screen unit without being interrupted to the end.
[0068]
Further, at the timing of the next basic clock (that is, at the time indicated by B in the figure), the second output control signal φ2 is set to the high level. At this time, since the second gate signal ψ2 is at the low level, the output of the image data 1 to n output from the gate circuit 12b is at the low level.
[0069]
For this reason, the non-inverted output signals of the short-circuited differential drivers 4a and 4b are at the same low level, and the inverted output signals are at the same high level. Therefore, an image signal that is stable at a low level is input to the differential receiver 8 and an erroneous signal is not sent, and the differential drivers 4a and 4b are not damaged by a short-circuit current.
[0070]
Further, at the timing of the next basic clock (that is, at the time indicated by C in the figure), the first output control signal φ1 is set to the low level, and the differential driver 4a of the first image processing unit is in the high impedance state. To. On the other hand, at this time, the output of the second image processing unit X2 remains fixed at the low level.
[0071]
Next, at the timing of the vertical synchronization signal in the second image processing unit (that is, at the time indicated by D in the figure), the second gate signal ψ2 is set to the high level, and the image of the second image processing unit X2 Output a signal.
[0072]
Here, since the second vertical synchronization signal is synchronized with the second data block completion signal, the image is not interrupted in the middle of the data block. Further, since the image signal is output at the same timing as the second vertical synchronizing signal, the image is not displayed halfway as in the case of using the conventional technique illustrated as the image 9 in FIG.
[0073]
FIG. 11 shows images displayed on the first image processing unit X1, the second image processing unit X2, and the display unit Y in order from the left. As shown in the figure, the image is not interrupted in the middle as in the prior art, and the image is not displayed in the middle.
[0074]
In the present embodiment, by configuring as described above, an image is not interrupted in the middle, an erroneous signal is transmitted, a differential driver is not damaged by a short-circuit current, and an image is further displayed. Is not displayed in the middle.
[0075]
Therefore, the present embodiment has the same effect as that of the first embodiment, and can switch the display image from one image processing unit to another image processing unit without any disturbance.
[0076]
In the present embodiment, the switching control circuits 13a and 13b are not limited to the circuit configuration shown in FIG. 9, and may have other configurations, and the first and second gate signals may be at the above timing. The configuration is not limited as long as it generates ψ1, ψ2 and the first and second output control signals φ1, φ2.
[0077]
In this embodiment, the number of image processing units is two. However, the number of image processing units may be three or more. Even in this case, the outputs of all the image processing units are once the same. After setting the level, an image processing unit that outputs an image signal may be selected using a switching signal. By doing so, there is no transmission of an erroneous signal, and the differential driver is not damaged by a short-circuit current.
[0078]
Even when the number of image processing units is three or more, by generating each gate signal so as to be synchronized with each data block completion signal and vertical synchronization signal, one image processing unit can perform another image processing. The display image can be switched without disturbing the display image at all.
[0079]
Embodiment 3 FIG.
FIG. 12 shows wiring between the differential drivers 4a and 4b of the image processing unit and the differential receiver 8 of the display unit in the third embodiment of the present invention. Except for the point that the resistors 14a to 14d for limiting current are provided at the output portions of the differential drivers 4a and 4b, the other points are the same as those in the first embodiment.
[0080]
In the present embodiment, the effects described in the first embodiment are provided, and the resistors 14a to 14d are provided, so that the differential driver 4a or 4b of any of the image processing units fails, and the difference Even when the output terminal and the power supply Vcc (5 V) or Vdd (0 V) are short-circuited inside the dynamic driver 4 a or 4 b, the image signal is not damaged without damaging one normal differential driver 4 b or 4 a. Can continue to output.
[0081]
On the other hand, when there is no resistor, for example, in the state where the non-inverting output unit of the differential driver 4a of the first image processing unit fails and the output terminal and Vdd (0 V) are short-circuited, When a high level is output from the non-inverted output of the differential driver 4b of the image processing unit, a short-circuit current flows through the differential driver 4b and the differential driver 4b is damaged. Therefore, naturally, a normal image signal cannot be output.
Since the present embodiment includes a current limiting resistor, it has an effect of suppressing the above-described problems.
[0082]
Here, the number of image processing units is not limited to two, and it goes without saying that the same effect can be obtained with three or more image processing units.
[0083]
Embodiment 4 FIG.
FIG. 13 shows a circuit configuration of an image display apparatus according to Embodiment 4 of the present invention. The image display apparatus according to the present embodiment includes circuits 22a and 22b including NOT circuits 16a and 16b and OR circuits 17a and 17b, respectively, in the image processing units X1 and X2, in addition to the circuit components in the first embodiment. To do.
[0084]
In the present embodiment, the voltage 5 V of the local power supply 15a provided in the first image processing unit X1 not explicitly shown in the first embodiment is input to one of the OR circuits 17b via the NOT circuit 16b. Input to the terminal. An inverted signal of the switching signal is input to the other input terminal of the OR circuit 17b, and the output signal of the OR circuit 17b is input to the differential driver 4b of the second image processing unit as the second output control signal φ2. To do.
[0085]
Similarly, the voltage 5V of the local power supply 15b inside the second image processing unit X2 is input to one input terminal of the OR circuit 17a via the NOT circuit 16a. The switching signal is input to the other input terminal of the OR circuit 17a, and the output signal of the OR circuit 17a is input to the differential driver 4a of the first image processing unit as the first output control signal φ1.
[0086]
Next, the operation will be described. When both local power supplies 15a and 15b operate normally and output 5V, the input signals to the NOT circuits 16b and 16a are at a high level, so that the output signals to the OR circuits 17b and 17a are at a low level. Therefore, the output signals of the OR circuits 17b and 17a are at the same level as the switching signal input to the other input terminal, so that the output control signals of the differential drivers 4b and 4a are changed according to the switching signal. Can do. Therefore, when both local power supplies 15a and 15b are operating normally, the same operation as in the first embodiment can be realized.
[0087]
In addition, since the present embodiment is configured as described above, even if the local power supply 15a or 15b of one image processing unit X1 or X2 fails, as described below, other image processing is performed. By automatically switching to the part X2 or X1, there is an effect that the image display can be continued.
[0088]
Specifically, when the local power supply 15b of the second image processing unit fails and 5V becomes 0V, the input signal to the NOT circuit 16a of the first image processing unit becomes a low level. The output signal to the circuit 17a becomes high level. Therefore, since the output signal in the OR circuit becomes high level regardless of the switching signal input to the other input terminal, the first output control signal φ1 of the differential driver 4a becomes high level, and the first image A differential signal is output from the processing unit 4a.
[0089]
On the other hand, at this time, since the local power supply 15b of the second image processing unit is out of order, the differential driver 4b of the second image processing unit is in a high impedance state, so that the first image is displayed on the display unit Y. The image of the processing unit X1 is displayed.
[0090]
On the contrary, when the output of the local power supply 15a of the first image processing unit X1 becomes 0V, the image of the second image processing unit X2 is displayed.
As described above, the present embodiment has the effects described in the first embodiment, and when the power circuit of one image processing unit or the like fails using a circuit having a simple structure, the other There is an effect that it is possible to automatically switch to the image processing unit.
[0091]
In this embodiment, the case where the number of image processing units is two is shown. However, three or more image processing units may be used, and by connecting the output of the local power source of each image processing unit to another image processing unit. Needless to say, when the power supply circuit of one image processing unit breaks down, it is possible to automatically switch to another image processing unit as in the case of two.
[0092]
【The invention's effect】
An image display device according to the present invention includes a plurality of image processing units each having output control means for switching an output of an image signal between an output state and a non-output state based on a switching signal, and an image processing unit in an output state And a display unit for displaying the output image signal, so that the image signal from a plurality of image processing units can be switched without requiring a common switching circuit as in the prior art, and the display unit is normal. For example, the display can be continued as long as all of the plurality of image processing units do not break down.
[0093]
The image display apparatus according to the present invention outputs a plurality of image processing units each having output control means for switching the output of each image signal between an output state and a non-output state, and the image processing unit in the output state. And a display unit that displays an image based on the image signal, wherein any one of the plurality of image processing units is in an output state and the other image processing unit is in a non-output state. The image signal from a plurality of image processing units can be switched without requiring a common switching circuit as in the prior art, and if the display unit is normal, the display is performed unless all of the plurality of image processing units fail. There is an effect that can be continued.
[0094]
In addition, when the output state is switched from the image processing unit in the output state to another image processing unit, all outputs of the plurality of image processing units are once at the same level. Transmitting a signal also has the effect that the image processing unit is not damaged by a short-circuit current.
[0095]
Also, the output state is switched from the image processing unit in the output state to another image processing unit in accordance with the timing of the data block completion signal of the image processing unit in the output state. There is no interruption in the middle of the data block, and the image is not displayed in the middle of the data block. Therefore, it is possible to switch from one image processing unit to another image processing unit without disturbing the display image.
[0096]
In addition, the output of the image processing unit in the output state becomes a predetermined level in accordance with the timing of the data block completion signal of the image processing unit in the output state, and then all the outputs of the plurality of image processing units are Since the other image processing unit switches to the output state in accordance with the timing of the data block completion signal of the other image processing unit after that, the erroneous signal is switched to the output state. The output state can be switched without causing the image processing unit to be damaged by a short-circuit current, and without disturbing the display image from one image processing unit to another image processing unit.
[0097]
Further, since the timing of the vertical synchronizing signal is used instead of the timing of the data block completion signal, the image is not interrupted in units of screens, and the image is not displayed from the middle of the screen. Therefore, it is possible to switch from one image processing unit to another image processing unit without disturbing the display image.
[0098]
In addition, a current limiting resistor is provided between the display unit and each of the plurality of image processing units, and when one of the plurality of image processing units fails, the other image processing unit is caused by a short-circuit current. Since the image signal can be output without failure, the image can be continuously displayed on the display unit based on the image signal from the image processing unit other than the failed image processing unit. effective.
[0099]
Each of the plurality of image processing units detects the power supply voltage of the other image processing unit, and automatically outputs each image signal to the display unit when the power supply voltage of the other image processing unit is cut off. Therefore, there is an effect that an image of another image processing unit can be automatically displayed without requiring a manual switching operation by a person who has found a failure of the image processing unit.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a circuit configuration in Embodiment 1 of an image display apparatus according to the present invention.
FIG. 2 is a circuit configuration diagram showing a circuit configuration of a differential driver in the first embodiment of the image display device according to the present invention.
FIG. 3 is a relationship diagram of input and output signals of a differential driver in the first embodiment of the image display device according to the present invention.
4 is a circuit configuration diagram showing wiring between a differential driver and a differential receiver in Embodiment 1 of the image display device according to the present invention. FIG.
FIG. 5 is a timing chart at the time of switching input and output signals of the differential driver and the differential receiver in Embodiment 1 of the image display device according to the present invention;
FIG. 6 is a relationship diagram of input and output signals of the differential driver and the differential receiver in the first embodiment of the image display device according to the present invention.
FIG. 7 is a circuit configuration diagram showing a circuit configuration in Embodiment 2 of an image display device according to the present invention.
FIG. 8 is a circuit configuration diagram showing a circuit configuration of a gate circuit in Embodiment 2 of the image display device according to the present invention.
FIG. 9 is a circuit configuration diagram showing a circuit configuration of a switching control circuit in Embodiment 2 of the image display device according to the present invention.
FIG. 10 is a timing chart at the time of switching of input and output signals of the differential driver, the gate circuit, and the switching control circuit in Embodiment 2 of the image display device according to the present invention.
FIG. 11 is a diagram showing a display image in the second embodiment of the image display device according to the present invention.
12 is a circuit configuration diagram showing wiring between a differential driver and a differential receiver in Embodiment 3 of the image display apparatus according to the present invention. FIG.
13 is a circuit configuration diagram showing a circuit configuration in Embodiment 4 of an image display device according to the present invention. FIG.
FIG. 14 is a circuit configuration diagram showing a circuit configuration of a conventional image display device.
FIG. 15 is a conceptual diagram showing a transmission format of image data in the first embodiment of the image display device according to the present invention.
FIG. 16 is a timing chart at the time of switching of input and output signals of an image processing unit and a switching circuit of a conventional image display device.
FIG. 17 is a diagram showing a display image of a conventional image display device.
[Explanation of symbols]
1a, 1b RGB decoding circuit, 2a, 2b A / D conversion circuit,
3a, 3b memory, 4a, 4b differential driver (output control means),
5a, 5b communication circuit, 6a, 6b character expansion circuit,
7a, 7b Memory control circuit, 8 Differential receiver,
9 memory, 10 drivers, 11 light emitting elements,
12a, 12b gate circuit, 13a, 13b switching control circuit,
14a, 14b, 14c, 14d Current limiting resistors,
15a, 15b local power supply, 16a, 16b NOT circuit,
17a, 17b OR circuit, 18a, 18b differential receiver,
19 selector, 20 differential driver,
21 control circuit, 22a, 22b a circuit for automatically outputting image signals,
24a, 24b differential driver,
φ1 first output control signal, φ2 second output control signal,
ψ1 first gate signal, ψ2 second gate signal,
X1 first image processing unit, X2 second image processing unit,
Y display, Z switching circuit.

Claims (8)

A plurality of image processing units each having output control means for switching the output of the image signal between an output state and a non-output state based on the switching signal;
In an image display device comprising a display unit for displaying an image signal output from an image processing unit in an output state ,
An image display device, wherein when an output state is switched from an image processing unit in an output state to another image processing unit, all outputs of the plurality of image processing units are once at the same level . A plurality of image processing units each having output control means for switching the output of the image signal between an output state and a non-output state based on the switching signal;
In an image display device comprising a display unit for displaying an image signal output from an image processing unit in an output state,
An image display device , wherein the output state is switched from the image processing unit in the output state to another image processing unit in accordance with the timing of the data block completion signal of the image processing unit in the output state . A plurality of image processing units each having output control means for switching the output of the image signal between an output state and a non-output state based on the switching signal;
In an image display device comprising a display unit for displaying an image signal output from an image processing unit in an output state,
In accordance with the timing of the data block completion signal of the image processing unit in the output state, the output of the image processing unit in the output state becomes a predetermined level, and then all the outputs of the plurality of image processing units become the predetermined level. An image display device , wherein the other image processing unit is switched to an output state at the same level and then in accordance with the timing of the data block completion signal of the other image processing unit . 2. The image according to claim 1 , wherein the output state is switched from the image processing unit in the output state to another image processing unit in accordance with the timing of the data block completion signal of the image processing unit in the output state. Display device. 5. The image display device according to claim 1, wherein any one of the plurality of image processing units is in an output state, and the other image processing unit is in a non-output state . 5. The image display device according to claim 2, wherein the timing is synchronized with the timing of the vertical synchronization signal instead of the timing of the data block completion signal. A current limiting resistor is provided between the display unit and each of the plurality of image processing units,
7. If any one of the plurality of image processing units fails, the other image processing units can output an image signal without failure due to a short-circuit current. The image display device according to item.   Each of the plurality of image processing units detects a power supply voltage of another image processing unit, and when the power supply voltage of the other image processing unit is cut off, a circuit that automatically outputs each image signal to the display unit The image display device according to claim 1, further comprising: an image display device according to claim 1.

Images