JP3675038B2 - Information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus having means for generating a random instruction sequence, and more particularly, information processing including means for continuously generating the same instruction with various conditions in a randomly generated instruction sequence Relates to the device.
[0002]
[Prior art]
FIG. 9 is a diagram for explaining a conventional means for generating a random instruction sequence. In the conventional instruction sequence generation means, an instruction identification code (hereinafter also referred to as an instruction ID) is set from the random data of the pseudo random number generator provided in the information processing apparatus, and according to the set instruction ID, An instruction sequence was generated from the instruction generation data obtained by decoding the instruction generation table 30 and a pseudo random number.
[0003]
In FIG. 9, first, random data is generated from the pseudo random number generator 1 and a random instruction ID is determined from the instruction ID section 20 of the instruction ID setting processing section 2. The instruction generation table 30 is composed of instruction information data (1) and instruction generation data (2).
[0004]
The command information data (1) is the format of the generated command (for example, field configuration for each command ID) or control information (for example, whether to insert a random number in each field described later or fixed data) Control flag or the like) is set and used when an instruction is generated.
[0005]
The command generation data (2) is generated data A (random value setting, for example, when the control flag indicates the random value setting, for generating the target command randomly, and a logical product ( AND) all “1” data) and generation data B (fixed data generated by the above control flag are forcibly added. The generated random numbers and logical sums are used to calculate each of the fields. Data for forcibly setting “1” or “0” in bit units).
[0006]
According to the determined instruction ID, the decoder 31 selects instruction information data (1) and instruction generation data (2) in the instruction generation table 30 corresponding to the instruction ID. Then, a random instruction is generated from the random data (5) from the pseudo random number generator 1 and the instruction generation data (2).
[0007]
The generated instruction is set in the instruction under test sequence 5 by the generation instruction setting processing unit 4. A predetermined number of generated instructions is set in advance in the generated instruction number counter 6. The generated instruction number counter 6 is set to “−1” by the subtraction control unit 60, and the generated instruction number counter = 0, The generation ends, and the generated instruction counter ≠ 0, so that the next instruction is generated, and the process returns to the generation process of the pseudo random number generator 1.
[0008]
[Problems to be solved by the invention]
Therefore, in the conventional random instruction generation means, in order to generate an instruction at random, a sequence of the same instruction,
The same number of consecutive instructions,
A sequence of identical instructions with all register values not duplicated,
A sequence of identical instructions whose operand address values are approximate,
A sequence of identical instructions that specify overlapping register values in preceding and following instructions,
Specifying the same instruction sequence,
This causes a problem that the instruction sequence cannot be intentionally generated.
[0009]
In view of the above-mentioned conventional drawbacks, the present invention generates a control bit (hereinafter also referred to as CB1 and CB2) together with the generation of an instruction ID, a repetitive counter for controlling the generated CB1 and CB2, a CB reset, Information processing provided with instruction sequence generation means capable of improving instruction generation efficiency by register value control data generation means for controlling generation of register numbers in instructions, approximate value data generation means for generating operand addresses, etc. The object is to provide an apparatus.
[0010]
[Means for Solving the Problems]
FIG. 1 is a diagram illustrating the principle of the present invention, and FIGS. 2 to 8 are diagrams illustrating an embodiment of the present invention. The above problem is solved by an information processing apparatus provided with the following instruction sequence generation means.
[0011]
(1) An information processing apparatus comprising means for generating an instruction sequence for testing an information processing apparatus,
Pseudorandom number generation means 1, an instruction identification code (instruction ID) generated using the random number generated by the pseudorandom number generation means 1, a first control bit (CB1) 21, and the first control bit (CB1) Instruction identification code setting processing means 2 comprising a control bit control unit (CB control unit) 22 for controlling 21;
Corresponding to the generated instruction identification code (instruction ID), the pseudo-random number generating means is provided for each field of the generated instruction format and instruction information data (1) consisting of control information and the generated instruction format. It has an instruction generation table 30 consisting of instruction generation data (2) that indicates whether to set a random number from 1 or to set predetermined fixed data, and randomly based on the contents of the instruction generation table 30 Random command generation control means 3 for generating commands,
Generated instruction setting processing means 4 for setting the generated predetermined number of instruction sequences in a predetermined area as an instruction sequence under test 5;
Generated instruction number counter 6 that specifies the number of instructions to be generated, and
With
The first control bit (CB1) 21 is controlled to generate a plurality of instructions identical to the instruction identification code (instruction ID) generated using the random number generated by the pseudo-random number generating means 1 Constitute. {See Figure 1}
(2) The information processing apparatus according to (1) above,
The instruction identification code setting processing means 2 includes means for setting the first control bit (CB1) 21 with the random number generated by the pseudo-random number generating means 1, and the set first control bit (CB1). 21 is configured to include a CB control unit 22 controlled (reset) by a random number (CB reset) 220 generated by the pseudo-random number generating means 1. {See Figure 2}
(3) The information processing apparatus according to (1) above,
The instruction identification code setting processing means 2 sets the first control bit (CB1) 21 set with the random number generated by the pseudo random number generating means 1 with the random number generated by the pseudo random number generating means 1. The CB control unit 22 is configured to be controlled (reset) with a predetermined count value (for example, count over) of the repeated counter 221. {See Figure 3}
(4) The information processing apparatus according to (1) above,
The instruction identification code setting processing means 2 uses the first control bit (CB1) 21 set by the random number generated by the pseudo-random number generating means 1 as the instruction information data (1) in the instruction generation table 30. The CB control unit 22 is configured to be controlled (reset) with a predetermined count value (for example, count over) of the repetition counter 221 set with predetermined data. {See Fig. 4}
(5) The information processing apparatus according to (1) above,
The instruction identification code setting processing means 2 has means for setting the first control bit (CB1) 21 based on predetermined data of the instruction information data (1) in the instruction generation table 30; The first control bit (CB1) 21 is configured to include a CB control unit 22 that controls (resets) the random number generated by the pseudo-random number generating means 1. {See Figure 5}
(6) The information processing apparatus according to (1) above,
In the instruction identification code setting processing means 2, a repetition counter 221 set by the random number generated by the pseudo-random number generation means 1, or a repetition counter 221 set by instruction information data {circle around (1)} of the instruction generation table 30. The register value control data generating means 225 for setting the register numbers that do not overlap is provided so that the register numbers of the plurality of generated instructions do not overlap based on the values of the above. {See Figure 6}
(7) The information processing apparatus according to (2), (3), (4), (5), or (6) above,
The instruction identification code setting processing means 2 includes a second control bit (CB2) 23, a random number generated by the pseudo-random number generation means 1 based on the second control bit (CB2) 23, and the instruction Approximate value data generating means 226 for generating similar addresses as operand addresses of the plurality of generated instructions using the predetermined data (3) of the instruction information data (1) in the generation table 30 is provided. Configure as follows. {See Fig. 7} (8) The information processing apparatus according to (2), (3), (4), (5), or (6) above,
The instruction identification code setting processing means 2 includes a second control bit (CB2) 23, a random number generated by the pseudo-random number generation means 1 based on the second control bit (CB2) 23, and the instruction Register value duplication data generation means 227 for generating a register number in which register numbers of the plurality of generated instructions are duplicated using predetermined data (4) of the instruction information data (1) in the generation table 30 is provided. Configure as follows. {See Fig. 8}
(9) The information processing apparatus according to (7) or (8) above,
The second control bit (CB2) 23 is configured to include means for generating a random number generated by the pseudo-random number generating means 1. {See Fig. 6 and Fig. 7}
(10) The information processing apparatus according to (7) or (8) above,
The second control bit (CB2) 23 is configured to include means for generating predetermined data of the instruction information data (2) of the instruction generation table 30.
[0012]
That is, the above (1) and (2) are means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
The generation is controlled by the instruction ID (identification code) and the first control bit (CB1) 21 generated by the pseudo-random number generator 1;
Instruction sequence generation having control means for generating a plurality of identical instruction IDs until the first control bit (CB1) 21 is set with a random number and reset with a random number for one instruction ID An information processing apparatus including means.
[0013]
The above (3) includes means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
The generation is controlled by an instruction ID (identification code), a first control bit (CB1) 21 generated by the pseudo random number generator 1, and a repeat counter 221 set at random by the pseudo random number generator 1. Means to
Control means for generating a plurality of identical instruction IDs until the first control bit (CB1) 21 is set with a random number and reset by the repeat counter 221 for one instruction ID. By providing the information processing apparatus, the information processing apparatus includes a control unit in which the number of times the plurality of identical instructions are generated is indicated by a random number.
[0014]
The above (4) includes means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
The generation is set by the instruction ID (identification code), the first control bit (CB1) 21 generated by the pseudo random number generator 1, and the predetermined data of the instruction information data (1) of the instruction generation table 30. Means controlled by the repeated counter 221;
Control means for generating a plurality of identical instruction IDs until the first control bit (CB1) 21 is set with a random number and reset by the repeat counter 221 for one instruction ID. By providing the information processing apparatus, the information processing apparatus has a control means in which the number of times the plurality of identical instructions are generated is indicated by the instruction information data (1) in the instruction generation table 30.
[0015]
In the above (5), means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
A first control in which the generation is set with an instruction ID (identification code) and predetermined data of instruction information data (1) in the instruction generation table 30 and is reset with a random number generated by the pseudo-random number generator 1 By means of means controlled by the bit (CB1) 21, the generation of a plurality of identical instruction IDs is instructed by the instruction information data (1) in the instruction information table 30 for one instruction ID. An information processing apparatus having control means.
[0016]
The above (6) includes means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
The generation is set by the instruction ID (identification code), the first control bit (CB1) 21 generated by the pseudo random number generator 1, and the predetermined data of the instruction information data (1) of the instruction generation table 30. Means controlled by the repeated counter 221
Control means for generating a plurality of identical instruction IDs until the first control bit (CB1) 21 is set with a random number and reset by overflow of the repeat counter 221 for one instruction ID. In accordance with the instruction by the predetermined data (3) of the instruction information data (1) of the instruction generation table 30 so that the register numbers of the plurality of generated instructions do not overlap. For example, there is provided means for setting the contents of the repeat counter 221 in the register value control data register 2250 and setting the set register number in the register number field of the generated instruction instead of a random number. It is.
[0017]
The above (7) includes means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
The generation is an instruction ID (identification code), a first control bit (CB1) 21 generated by the pseudo-random number generator 1, a second control bit (CB2) 23, and an instruction of the instruction generation table 30 Means controlled by a repetitive counter 221 set with predetermined data of information data (1);
Control means for generating a plurality of identical instruction IDs until the first control bit (CB1) 21 is set with a random number and reset by overflow of the repeat counter 221 for one instruction ID. In an information processing apparatus comprising:
Based on the instruction of the second control bit (CB2) 23, the means (operating value data generating means) 226 for maintaining the operand addresses of the plurality of generated instructions in the vicinity of a predetermined value, for example, The approximate value data generated by setting the low-order bits with random numbers using the predetermined bits (3) of the instruction information data (1) of the instruction generation table 30 as the high-order bits of the operand address. It is set to.
[0018]
The above (8) includes means for randomly generating the instruction ID of the instruction under test by the pseudo random number generator 1;
The generation is an instruction ID (identification code), a first control bit (CB1) 21 generated by the pseudo-random number generator 1, a second control bit (CB2) 23, and an instruction of the instruction generation table 30 Means controlled by a repetitive counter 221 set with predetermined data of information data (1);
Control means for generating a plurality of identical instruction IDs until the first control bit (CB1) 21 is set with a random number and reset by overflow of the repeat counter 221 for one instruction ID. In an information processing apparatus comprising:
Based on the instruction of the second control bit (CB2) 23, as means (register value duplication data generation means) 227 for making the register values of the plurality of generated instructions overlap, for example, an instruction generation table 30 The predetermined data “00” of the instruction information data {circle over (1)} is logically ANDed with the random number to delete the random number, and the predetermined data “10” of the instruction information data {circle over (1)} A control means for generating an overlapped register value is provided by logically adding (4) and generating fixed data “01”.
[0019]
The above (9) is to generate the second control bit (CB2) 23 by a random number, and the invention of claim 10 provides the second control bit (CB2) 23 to the instruction generation table. It is generated with 30 command information data (1).
[0020]
Therefore, according to the information processing apparatus of the present invention, according to the above (1) to (5), a plurality of identical instructions are based on random numbers or the number specified by the instruction information data (1) in the instruction generation table 30. It can be produced continuously.
[0021]
In addition, because of the above (6), it is possible to continuously generate the same instruction in which all register values do not overlap, and because of the above (7), an approximation that does not change much with respect to the plurality of generated same instructions. It is possible to generate an operand address that takes a value, and according to the above (8), it is possible to continuously generate the same instruction in which register values are overlapped by preceding and following instructions.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the principle of the present invention, FIGS. 2 to 8 are diagrams showing an embodiment of the present invention, and FIG. 2 shows a first control bit set by a random number. FIG. 3 shows the case where the first control bit (CB1) set by the random number is controlled by the repetition counter set by the random number, and FIG. 4 shows the case where the random number is controlled by the random number. FIG. 5 shows the case where the first control bit (CB1) set in step 1 is controlled by the repeat counter intentionally set in the instruction information data (1) in the instruction generation table. FIG. 5 shows the instruction information data in the instruction generation table. The case where the first control bit (CB1) set intentionally in (1) is controlled by a random number is shown. FIG. 6 shows the instruction generation table so that the register values of a plurality of generated same instructions do not overlap. FIG. 7 shows a case where control is performed using the command information data (1). FIG. 8 shows a case where control is performed so that the operand address of one instruction becomes a predetermined approximate value. FIG. 8 shows a register value of a plurality of generated identical instructions as a fixed value by instruction information data (1) in the instruction generation table. The case of controlling is shown in FIG.
[0023]
In the present embodiment, an information processing apparatus having means for generating an instruction sequence for testing the information processing apparatus, the means for generating an instruction code (instruction ID) with a random number, and the first control bit (CB1) 21, the first control bit (CB1) 21 is controlled by a random number or instruction information data (1) in the instruction generation table 30, and the first control bit (CB1) 21 is, for example, , “1”, a means for generating a plurality of instructions having the same instruction code (instruction ID) and a plurality of instructions generated by the instruction by the instruction information data (1) in the instruction generation table 30 A means for preventing register values from overlapping and a second control bit (CB2) 23 are provided, and the second control bit (CB2) 23 is set as a random number or instruction information data (1) in the instruction generation table 30. Control, the second control bit (CB2) 23 is generated while it is “1”, for example. Means for setting operand addresses of a plurality of instructions to a predetermined approximate value, and means for setting register values of a plurality of instructions to be a predetermined value indicated by the instruction information data (1) of the instruction generation table 30 These are necessary means for the present embodiment. In addition, the same code | symbol has shown the same target object through all the figures.
[0024]
Hereinafter, the configuration and operation of an information processing apparatus including an instruction sequence generation unit that generates an instruction sequence for testing the information processing apparatus of the present invention will be described with reference to FIG.
[0025]
First, FIG. 2 is a diagram for explaining an embodiment of the means (1) and (2).
The command ID setting processing unit 2 includes a command ID unit 20 and a CB reset 220.
Random data is generated from the pseudo random number generator 1, and a random instruction ID and a random CB value {value of the first control bit (CB1)} are given to the instruction ID section 20 of the instruction ID setting processing section 2. Set.
If CB1 = 0, the instruction ID is passed to the instruction generation table 30 of the random instruction generation control unit 3.
If CB1 = 1, the instruction ID part 20 is prohibited from updating the instruction ID, and the same instruction ID is continuously passed to the instruction generation table 30 unless CB1 = 0 is set by the CB reset 220 set at random.
[0026]
The instruction generation table 30 is composed of instruction information data (1) and instruction generation data (2). The command information data (1) controls the format of the generated command, for example, the field configuration for each command ID, and control information, for example, whether or not to set a random number in each field of each generated command ID. Control flags, control data, etc. are set and used when generating instructions.
[0027]
The instruction generation data (2) includes the above-mentioned generation data A (logical product data with random numbers for setting random values, for example, all “1” data) for generating a target instruction randomly, and generation data B (logical sum data with a random number for forcibly adding a predetermined value, “0” or “1”).
[0028]
According to the determined instruction ID, the decoder 31 selects instruction information data (1) and instruction generation data (2) in the instruction generation table 30 corresponding to the instruction ID. Further, a random command is generated from the random data from the pseudo random number generator 1 and the control data of the command generation data (2).
[0029]
The generated instruction is set in the instruction under test sequence 5 by the generation instruction setting processing unit 4. A predetermined number of generated instructions is set in advance in the generated instruction number counter 6. The generated instruction number counter 6 is set to “−1” by the subtraction control unit 60, and the generated instruction number counter = 0 is set as above. The generation of the generated instruction ID is finished, and the next instruction is generated with the generated instruction counter ≠ 0.
[0030]
FIG. 3 is a diagram for explaining an embodiment of the means (3).
In this embodiment, the instruction ID setting processing unit 2 includes an instruction ID unit 20, a CB reset 223, a repeat counter 221, and a subtraction control unit 222.
[0031]
Random data is generated from the pseudo random number generator 1, and a random instruction ID and a random CB value {value of the first control bit (CB1)} are given to the instruction ID section 20 of the instruction ID setting processing section 2. Set random counter data in the repeat counter 221.
[0032]
The set CB value {the value of the first control bit (CB1) 21} is
If CB1 = 0, the instruction ID is passed to the instruction generation table 30 of the random instruction generation control unit 3.
If CB1 = 1, update of the instruction ID of the instruction ID portion 20 and update of the repeat counter 221 are prohibited,
The repetition counter 221 continues to pass the same instruction ID to the instruction generation table 30 until the repetition counter = 0 by the subtraction control unit 222.
When the repeat counter = 0, the CB reset 223 is activated and CB1 = 0 is set. The subsequent operation is the same as that of the first and second aspects of the invention described with reference to FIG.
[0033]
Next, FIG. 4 is a diagram for explaining an embodiment of the means (4).
In this embodiment, the instruction ID setting processing unit 2 includes an instruction ID unit 20, a CB reset 223, a repetition counter 221, a subtraction control unit 222, and a setting determination unit 224.
[0034]
Random data is generated from the pseudo random number generator 1, and a random instruction ID and a random CB value {value of the first control bit (CB1)} are given to the instruction ID section 20 of the instruction ID setting processing section 2. Set.
The set CB value {the value of the first control bit (CB1) 21} is
If CB1 = 0, the instruction ID is passed to the instruction generation table 30 of the random instruction generation control unit 3.
If CB1 = 1, update of the instruction ID of the instruction ID portion 20 is prohibited.
[0035]
In accordance with the instruction ID thus determined, the decoder 31 selects instruction information data (1) and instruction generation data (2) in the instruction generation table 30 corresponding to the instruction ID. The designated repeat counter data is set in the repeat counter 221 from the selected instruction information data (1). At this time, in order to prevent resetting during generation in the repetition counter 221, the setting determination unit 224 determines whether or not the setting is already set.
[0036]
The repeat counter 221 continues to pass the same instruction ID to the instruction generation table 30 until the repeat counter = 0 by the subtraction control unit 222. When the repeat counter = 0, the CB reset 223 is activated to set CB1 = 0. Other operations are the same as those of the first and second aspects of the invention described with reference to FIG.
[0037]
Next, FIG. 5 is a diagram for explaining an embodiment of the means (5).
In this embodiment, the CB setting of the instruction ID unit 20 is set from the instruction information data (1) in the instruction generation table 30 of the random instruction generation control unit 3 by using the CB value {value of the first control bit (CB1)}. obtain. Other operations are the same as those of the first and second aspects of the invention described with reference to FIG.
[0038]
Next, FIG. 6 is a diagram for explaining an embodiment of the means (6).
In this embodiment, the instruction ID setting processing unit 2 includes an instruction ID unit 20, a CB reset 223, a repeat counter 221, a subtraction control unit 222, a setting determination unit 224, and a register value control data generation unit 225. It is configured.
[0039]
First, random data is generated from the pseudo-random number generator 1, and a random instruction ID and a random CB value {the value of the first control bit (CB1) are sent to the instruction ID section 20 of the instruction ID setting processing section 2. } Is set.
[0040]
The set CB value {value of the first control bit (CB1)} is
If CB1 = 0, the instruction ID is passed to the instruction generation table 30 of the random instruction generation control unit 3.
If CB1 = 1, update of the instruction ID of the instruction ID portion 20 is prohibited.
In this way, according to the determined instruction ID, the decoder 31 selects instruction information data (1) and instruction generation data (2) in the instruction generation table 30 corresponding to the instruction ID. The designated repeat counter data is set in the repeat counter 221 from the selected instruction information data (1). At this time, in order to prevent resetting during generation in the repetition counter 221, the setting determination unit 224 determines whether or not the setting is already set.
[0041]
The repeat counter 221 continues to pass the same instruction ID to the instruction generation table 30 until the repeat counter = 0 by the subtraction control unit 222. When the repeat counter = 0, the CB reset 223 is activated to set CB = 0. The register value control data generating means 225 generates register value control data (6) corresponding to the instruction format from the instruction information data (1) based on the data set in the repeat counter 221. The generated register value control data (6) is replaced with random data from the pseudo random number generator 1, and a random instruction is generated from the replaced register value control data (6) and the instruction generation data (2). Is done.
[0042]
At this time, since the repeat counter 221 is “−1” by the subtraction control unit 222 every time the instruction ID is generated, the value of the register value control data {circle around (6)} sequentially changes. The register value corresponding to the instruction format changes from the instruction information data {circle around (1)} of the instruction ID so that it is not duplicated. Other operations are the same as those of the first and second aspects of the invention described with reference to FIGS.
[0043]
Next, FIG. 7 is a diagram for explaining an embodiment of the means (7).
The instruction ID setting processing unit 2 includes an instruction ID unit 20, a CB reset 223, a repetition counter 221, a subtraction control unit 222, a setting determination unit 224, and approximate value data generation means 226.
[0044]
First, random data is generated from the pseudo-random number generator 1, and a random instruction ID and a random CB1 value {value of the first control bit (CB1) are sent to the instruction ID section 20 of the instruction ID setting processing section 2. }, CB2 value {value of second control bit (CB2)} is set.
[0045]
The set CB1 value {the value of the first control bit (CB1)} is
If CB1 = 0, the instruction ID is passed to the instruction generation table 30 of the random instruction generation control unit 3.
If CB1 = 1, update of the instruction ID of the instruction ID portion 20 is prohibited.
In this way, according to the determined instruction ID, the decoder 31 selects instruction information data (1) and instruction generation data (2) in the instruction generation table 30 corresponding to the instruction ID. The designated repeat counter data is set in the repeat counter 221 from the selected instruction information data (1). At this time, in order to prevent resetting during generation in the repetition counter 221, the setting determination unit 224 determines whether or not the setting is already set.
[0046]
The repeat counter 221 continues to pass the same instruction ID to the instruction generation table 30 of the random instruction generation control unit 3 until the repetition counter = 0 by the subtraction control unit 222. When the repeat counter = 0, the CB reset 223 is activated to set CB1 = 0 and CB2 = 0.
[0047]
At this time, the CB2 value {value of the second control bit (CB2)} set by the random data is
If CB2 = 0, the same processing as described above is performed.
If CB2 = 1, in addition to the above processing, the approximate value data generation means 226 performs the following processing. That is, for the random data of the pseudo random number generator 1, the approximate value data (3) corresponding to the command format is generated from the command information data (1) and set in the approximate value data register 2260 together with the random number. A random instruction is generated from the generated data in the approximate value data register 2260 and the instruction generation data (2).
[0048]
For example, the approximate value is generated by fixing the upper bits of the operand address data with the approximate value data {circle around (3)} and using the lower bits as random numbers. In this way, the operand addresses of the plurality of instruction IDs generated are predetermined approximate operand addresses in which the lower bits are slightly changed by random numbers, with the value of the upper bits being determined. Other operations are the same as those of the first and second aspects of the invention described with reference to FIG.
[0049]
FIG. 8 is a diagram for explaining an embodiment of the means (8).
In this embodiment, the instruction ID setting processing unit 2 includes an instruction ID unit 20, a CB reset 223, a repeat counter 221, a subtraction control unit 222, a setting determination unit 224, and a register value duplication data generation unit 227. It is configured.
[0050]
First, random data is generated from the pseudo-random number generator 1, and a random instruction ID and a random CB1 value {value of the first control bit (CB1) are sent to the instruction ID section 20 of the instruction ID setting processing section 2. }, The CB2 value {the value of the second control bit (CB2)} is set.
[0051]
The set CB1 value {the value of the first control bit (CB1)} is
If CB1 = 0, the instruction ID is passed to the instruction generation table 30 of the random instruction generation control unit 3.
If CB1 = 1, update of the instruction ID of the instruction ID portion 20 is prohibited.
In this way, according to the determined instruction ID, the decoder 30 selects instruction information data (1) and instruction generation data (2) in the instruction generation table 30 corresponding to the instruction ID. The designated repeat counter data is set in the repeat counter 221 from the selected instruction information data (1). At this time, in order to prevent resetting during generation in the repetition counter 221, the setting determination unit 224 determines whether or not the setting is already set.
[0052]
The repeat counter 221 continues to pass the same instruction ID to the instruction generation table 30 until the repeat counter = 0 by the subtraction control unit 222. When the repetition counter = 0, the CB reset 223 is activated to set CB1 = 0 and CB2 = 0.
[0053]
At this time, the CB2 value {value of the second control bit (CB2)} set by the random data is
If CB2 = 0, the same processing as described above is performed.
If CB2 = 1, the following processing is performed by the register value duplication data generation means 227 together with the above processing.
[0054]
That is, the register value duplication data (4) corresponding to the instruction format is generated from the instruction information data (1) for the random data of the pseudo random number generator 1. A random instruction is generated from the generated register value duplication data (4) and the instruction generation data (2). That is, in the register value duplication data generation means 227, the register value duplication data {circle around (4)} "0000 ~" takes the logical product with the random number from the pseudo random number generator 1, erases the random number, and then creates another register value. Duplicate data (4) ORed with “10” to forcibly set the register value to “10” and set it in the register value duplicate data register 2270. 10 "and the instruction generation data {circle around (2)} generate an instruction sequence having register values that overlap with the plurality of instruction IDs.
[0055]
Other operations are the same as the operations of the means (1) and (2) described with reference to FIG. In the embodiment described with reference to FIGS. 6, 7, and 8, the number of repetitions set in the repetition counter 221 is described as an example in which the instruction information data (1) in the instruction generation table 30 is intentionally specified. However, the present invention is not limited to this, and it goes without saying that the number set in the repetition counter 221 may be set by the random data of the pseudo random number generator 1.
[0056]
In the embodiment described with reference to FIG. 6, control is performed using data from instruction information data (1) in the instruction generation table 30 in order to control register values corresponding to a plurality of generated instruction IDs so as not to overlap. Although described in the example, the present invention is not limited to this example. For example, the second control bit (CB2) 23 described in FIGS. 7 and 8 may be used for control. is there.
[0057]
In the embodiment shown in FIGS. 7 and 8, the second control bit (CB2) 23 has been described as an example of setting the random number generated by the pseudo-random number generator 1. However, as described with reference to FIG. Needless to say, the command information data (1) in the command generation table 30 may be set.
[0058]
As described above, the information processing apparatus of the present invention uses a pseudo-random number generator, a command random number generated by the pseudo-random number generator, and an instruction identification code (command ID) and first and second control bits ( CB1, CB2) and instruction identification code setting processing means comprising a control bit control unit for controlling the first and second control bits (CB1, CB2), and corresponding to the generated instruction identification code (instruction ID) Then, the command information data (1) consisting of the format of the generated command and control information, and the random number from the pseudo-random number generating means are set for each field of the command format, or predetermined fixed data is set. A random command generation control means for generating a random command based on the content of the command generation table, and a predetermined command generated Number of instruction sequences to be tested It is characterized in that it is composed of a generation instruction setting processing means for setting a predetermined area as an instruction sequence and a generation instruction counter for designating the number of instructions to be generated.
[0059]
【The invention's effect】
As described above in detail, according to the information processing apparatus of the present invention,
By the means (1) to (5), a plurality of identical instructions can be generated continuously based on random numbers or the number specified by the instruction information data (1) in the instruction generation table 30.
[0060]
Also, the means (6) makes it possible to continuously generate the same instruction in which all register values do not overlap. It is possible to generate an operand address that takes an approximate value that is not, and by means of the above means (8), an intentional instruction sequence is generated in which the same instruction with overlapping register values is continuously generated by the preceding and following instructions. be able to.
[0061]
Therefore, it is possible to dramatically improve the instruction generation efficiency of the same instruction as compared with the conventional case. Further, by using this instruction sequence generation means for the test of the information processing apparatus, it is possible to perform an efficient test for shortening the execution time.
[Brief description of the drawings]
FIG. 1 is a principle configuration diagram of the present invention.
FIG. 2 is a diagram showing an embodiment of the present invention (No. 1)
FIG. 3 is a diagram showing an embodiment of the present invention (No. 2)
FIG. 4 is a diagram showing an embodiment of the present invention (part 3);
FIG. 5 is a diagram showing an embodiment of the present invention (part 4);
FIG. 6 is a diagram showing one embodiment of the present invention (No. 5).
FIG. 7 is a diagram showing an embodiment of the present invention (No. 6).
FIG. 8 is a diagram showing an embodiment of the present invention (part 7);
FIG. 9 is a diagram for explaining a conventional means for generating a random instruction sequence;
[Explanation of symbols]
1 Pseudorandom number generator, pseudorandom number generator
2 Instruction identification code setting processing means, instruction ID setting processing section
20 Instruction ID part 21 Control bit (CB1)
22 CB control unit 23 Control bit (CB2)
220,223 CB reset
221 Repeat counter 60,222 Subtraction control unit
224 Setting judgment unit 225 Register value control data generation means
2250 Register value control data register
226 Approximate value data generation means 2260 Approximate value data register
227 Register value duplicated data generation means
2270 Register value duplicate data register
3 Random instruction generation control unit, random instruction generation control means
30 Instruction generation table 31 Decoder
4 Generation command setting processing means, generation command setting processing section
5 Instruction sequence under test
6 Generated instruction counter (1) Instruction information data
(2) Instruction generation data
(3) Predetermined data, predetermined bits, approximate value data from instruction information data
(4) Predetermined data from the instruction information data (register value duplication data)
(5) Random data
(6) Register value control data

Claims (8)

An information processing apparatus comprising means for generating an instruction sequence for testing the information processing apparatus,
Pseudo-random number generating means;
An instruction identification code generated using the random number generated by the pseudo-random number generating means, a first control bit set by the random number generated by the pseudo-random number generating means, and the first control bit are controlled control bit controlling unit to the instruction identification code setting means consisting of,
And command information data consisting of format and control information creating command corresponding to the upper Symbol instruction identification code is generated by a random number of either directly setting the predetermined fixed data or setting instruction from the pseudo random number generation means A command generation table including command generation data , and once the command identification code is set by a random number, the predetermined value is set to the control bit control unit while the first control bit is a predetermined value. Until the value is reset, the random number value generated thereafter is prohibited from being set as a new instruction identification code value, and the instruction generation table is identical by decoding the same instruction identification code. Instruction information data and instruction generation data are generated, and random instruction generation control means for generating a random instruction based on the contents of the instruction generation table ;
A generation instruction setting processing means for setting a predetermined number of one instruction under test generated based on a set of instruction information data and instruction generation data on the instruction generation table, and a predetermined area as an instruction string under test;
A generated instruction counter that specifies the number of instructions that are set at startup and then subtracted each time an instruction is generated, and generated until the count value ends with zero,
The first control bit is controlled to generate a plurality of instructions identical to the instruction identification code generated using the random number generated by the pseudo-random number generating means, and reset by the first control bit Thereafter, generation of the same plurality of instructions is repeated in the same manner using the instruction identification code newly set by the random number generated after the reset, and the generation of the instruction sequence under test is completed when the generated instruction number counter is zero. An information processing apparatus characterized by that. The information processing apparatus according to claim 1,
The control bit controller of the instruction identifier setting processing unit, the first control bit set in the random number generated by the該疑similar random number generation means, for resetting a random number generated by the pseudo-random number generating means An information processing apparatus characterized by being a thing. The information processing apparatus according to claim 1,
The control bit control unit of the instruction identification code setting processing unit further includes a repeat counter set by a random number generated by the pseudo random number generation unit and a value of the repeat counter for each generation of random numbers by the pseudo random number generation unit. And a subtracting control unit for subtracting the first control bit set by the random number generated by the pseudo-random number generating means and resetting the first control bit with a predetermined count value of the repetition counter; Information processing apparatus. The information processing apparatus according to claim 1,
The control bit control unit of the instruction identification code setting processing unit further includes a repeat counter set by a random number generated by the pseudo random number generating unit and a value of the repeat counter for each generation of random numbers by the pseudo random number generating unit. A subtracting control unit for subtracting the first control bit, and resetting the first control bit set by predetermined data of the instruction information data of the instruction generation table with a predetermined count value of the repetition counter. A characteristic information processing apparatus. The information processing apparatus according to claim 1,
The control bit control unit of the instruction identification code setting processing means generates the first control bit set by predetermined data of the instruction information data in the instruction generation table, and generates the pseudo random number. An information processing apparatus that resets with a random number generated by the means. An information processing apparatus according to any one of claims 1, 3, or 4, The instruction identification code setting processing means further has a register value control data register, and is set by the value of a repetitive counter set by the random number generated by the pseudo-random number generating means or the instruction information data of the instruction generation table The value of the repeated counter is subtracted by the subtraction control unit every time the instruction identification code is generated, and the value of the repeated counter is set in the register value control data register every time the instruction is subtracted, and the generation is performed based on the value. An information processing apparatus comprising register value control data generating means for generating register numbers that do not overlap by setting register numbers of a plurality of instructions to be executed. An information processing apparatus according to any one of claims 1 to 5,
The instruction identification code setting processing means further includes an approximate value data register,
In addition to the first control bit of the control bit control unit, a second control bit that is set with a random number generated by the pseudo-random number generator and resets the first control bit is provided.
Based on the second control bit of the control bit control unit, the random number generated by the pseudo-random number generating means is generated in the lower bits of the operand addresses of the generated instructions via the approximate value data register. Approximate value data generating means for setting approximate value data corresponding to the instruction format from the instruction information data in the upper bits of the operand addresses of the plurality of instructions to be executed,
An information processing apparatus that generates similar addresses as operand addresses of the plurality of instructions generated. An information processing apparatus according to any one of claims 1 to 5,
The instruction identification code setting processing means further includes a register value duplication data register,
Based on the second control bit, the instruction identification code setting processing means causes the pseudo-random number generating means to generate a random number generated by the pseudo-random number generating means based on the duplication instruction data in the instruction information data. Logical operation means for performing a logical operation in a bit-corresponding manner, taking a logical sum with data for taking a logical sum in the instruction generation data after taking a logical product with the data for taking the product;
Register value duplication data generation means for setting the predetermined duplication instruction data after the logical operation processing in the register value duplication data register,
An information processing apparatus for generating a register number in which register numbers of the plurality of generated instructions are duplicated.

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