JP3675748B2 - Data storage controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data storage control apparatus in a computer system, and more particularly to a data storage control apparatus that detects and corrects data errors and controls storage in a memory or reading from a memory.
[0002]
[Prior art]
In the field of semiconductors, miniaturization technology has made significant progress. In various memory devices, the storage capacity per memory device increases due to the progress of this miniaturization technology. However, the amount of accumulated charges decreases due to the reduction in volume occupied by one memory cell, and the probability of occurrence of micro defects increases. Due to external factors such as the application of electrical noise accompanying an increase in operation speed, the probability of occurrence of error bits in the data increases.
In general, as a method for improving the reliability of data in a memory, a parity check method and an ECC (error detection and correction) method are known (for example, a memory system described in Japanese Patent Application Laid-Open No. 59-3800).
[0003]
In the parity check method, one parity bit is added to the data bit, and the number of bits in which the data bit and the bit value in the parity bit are “1” is unified to the odd number or even number by the parity bit and written to the memory At the time of reading, an error is detected by checking the number of bits in which the value of the data bit and the parity bit is “1”.
[0004]
In the ECC method, a check bit is generated from a data bit using an extended Hamming code, and the data bit and the check bit are written in a memory. At the time of reading, a syndrome is generated from the data bits read from the memory and the check bits, and 1-bit error correction and 2-bit error detection are performed using the syndrome.
[0005]
[Problems to be solved by the invention]
However, the parity check method described above can detect only an odd number of bits and cannot detect an even number of bits. Further, even when an odd number of bits of error is detected, it is impossible to specify which bit in the data has an error, so that the error cannot be corrected.
[0006]
In contrast, in the ECC system, 1-bit error correction and 2-bit error detection are possible. However, in the ECC method, the error detection and correction method is more complicated than in the parity check method, so that it takes time for memory access by ECC execution and there is a disadvantage that the overhead time becomes longer.
[0007]
An object of the present invention is to realize a data storage control device capable of solving these drawbacks of the prior art, performing error detection and correction and memory access at high speed, and improving the use efficiency of the memory.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
Data storage control having data storage means for storing data and information for error detection and correction of the data, and controlling data reading and writing of the data storage means in response to data reading and writing requests from the data processor In the apparatus, data stored in the data storage means and information for error detection and correction of the data are supplied, and data error detection and correction means for detecting and correcting an error in the supplied data; and the data error detection and correction means The buffer memory for storing the data corrected by the error, the data error detection correction information of the data requested to be written by the data processor, and the data requested to be written and the generated data error detection correction information A data error detection / correction information generation means to be stored in the storage means and a data write request. However, the data requested to be written is less than the data length of the data stored in the data storage means, and the data at the address corresponding to the address where the data requested to be written is stored is not stored in the buffer memory. In this case, the data at the address is read from the data storage means and supplied to the data error detection / correction means and the data error detection / correction information generation means so as to detect the data error and in parallel with the error detection of the data. The data read from the data storage means and the data requested to be written are combined so that the data length is equal to the data length, and the error detection / correction information of the combined data is generated. If no error is detected by the detection / correction means, Data and the generated data error detection and correction information, is stored in the data storage meansIn response to the data write request, the write requested data is less than the data length of the data stored in the data storage means, and the data at the address corresponding to the address where the write requested data is to be stored is If the data is stored in the buffer memory, the data stored in the buffer memory and the data requested to be written are combined so that the data length is equal to the data length. Generate detection / correction information, and use the combined data and generated data error detection / correction Store information in data storage meansData control means.
[0009]
When the data requested to be read is not stored in the buffer memory, the data requested to be read and the data related to this data are read from the data storage means, and are sent to a plurality of data error detection and correction means. Supplied. The plurality of data error detection and correction means are operated almost simultaneously by the data control means. The plurality of data subjected to error detection and correction are stored in the buffer memory. There is a high probability that the data related to the data requested to be read will be requested to be read from the data processor. When the data is requested to be read, the error detection and correction data is already stored in the buffer memory. Therefore, the data reading speed is increased.
[0010]
Further, the data requested to be written is less than the data length of the data stored in the data storage means, and the data at the address corresponding to the address where the data requested to be written is stored is stored in the buffer memory. In some cases, the data stored in the buffer memory can be combined with the data requested to be written. As a result, it is possible to omit reading data corresponding to the address where the write-requested data should be stored and error detection and correction of the read data, thereby shortening the data writing operation time.
[0011]
Further, the data requested to be written is less than the data length of the data stored in the data storage means, and the data at the address corresponding to the address where the data requested to be written is stored is not stored in the buffer memory. In this case, the data at the address is read from the data storage means, and the detection of the data error, the combination with the data requested to be written, and the generation of the error detection correction information of the combined data are executed in parallel. . When no data error is detected, the combined data and the generated data error detection / correction information are stored in the data storage means.
[0012]
Accordingly, error correction of data read from the data storage means, a combination of error-corrected data and write-requested data, and subsequent generation of error detection / correction information are omitted, and data writing time is shortened. Can be realized.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a schematic configuration diagram of a data recording control apparatus according to a first embodiment of the present invention. In FIG. 1, the address of data requested to be read from an MPU (main processor (data processor)) 14 is supplied to the control unit 7 through the address bus 12 and the control signal line 13 together with the control signal. The control unit 7 supplies an address of data to be read from the memory 15 and a control signal to the memory 15 via the address bus 10 and the signal line 11.
[0014]
The memory 15 supplies the data and check bits of the address requested from the control unit 7 to the ECC execution units 4a, 4b and 4c for detecting and correcting data errors via the memory data bus 8 and the check bit bus 9. . The ECC execution units 4a, 4b, and 4c perform error detection and correction of read data based on the supplied check bit data (data error detection and correction information) in accordance with a control signal from the control unit 7.
[0015]
Data after execution of error detection and correction from the ECC execution units 4a, 4b, and 4c is stored in the buffer memories 3a, 3b, and 3c, respectively. The output control unit 5 outputs data from the buffer memories 3 a, 3 b, 3 c to the MPU 14 via the MPU data bus 6 in accordance with a control signal from the control unit 7.
[0016]
FIG. 2 is an internal block diagram of the control unit 7.
In FIG. 2, the address comparison unit 71 determines whether data corresponding to the address of the memory accessed by the MPU 14 on the MPU address bus 12 is stored in the buffer memories 3a, 3b, and 3c. When the data accessed by the MPU 14 exists in the buffer memories 3a, 3b, and 3c, the address comparison unit 71 outputs the position of the buffer memory in which the data is stored to the data position notification bus 72. When the data accessed by the MPU 14 does not exist in the buffer memories 3 a, 3 b, 3 c, the address of the memory accessed by the MPU 14 is output to the data position notification bus 72.
[0017]
Further, the address comparison unit 71 outputs information on whether or not the data accessed by the MPU 14 exists in the buffers 3a, 3b, and 3c to the data hit information line 73. The control signal generator 74 outputs the memory address accessed by the MPU 14 to the memory address bus 10. Further, the control signal generation unit 74 determines the ECC execution units 4a, 4b, 4c and the buffer memory 3a from the control signal from the MPU on the MPU control signal line 13, the data on the data position notification bus 72, and the data hit information line 73. 3b, 3c, a signal for controlling the output control unit 5 and the memory 15 is generated and output to the control signal line 11.
FIG. 3 is a diagram showing the correspondence between the address of the memory 15 and the data stored at the address.
FIG. 4 is an operation flowchart of the example of FIG. If there is a data read request from the MPU 14 in step 100 of FIG. In step 101, the control unit 7 determines whether or not the data of the address n requested to be read is stored in the buffer memory 3a, 3b or 3c.
[0018]
If the requested data is not stored in the buffer memory 3a, 3b, or 3c, the process proceeds to step 102, where the data at the requested address n is read from the memory 15, and the data at the addresses n + 1 and n + 2 related to the address n. Is read. In steps 103, 104, and 105, error detection and correction of data at addresses n, n + 1, and n + 2 are executed in parallel by the ECC execution units 4a, 4b, and 4c, respectively. Next, in steps 106, 107, and 108, the data detected and corrected for error are stored in the buffer memories 3a, 3b, and 3c, respectively.
In step 109, the data at the address n requested from the MPU 14 is transferred from the buffer memory 3a to the MPU 14.
[0019]
In step 101, if the data at the requested address is stored in the buffer memory 3a, 3b or 3c, the process proceeds to step 109, and the MPU 14 is sent from the buffer memory in which the data is stored to the MPU 14 via the output control unit 5. Data is transferred.
That is, when data 1 at address 0001 is requested to be read from MPU 14, data 2 and 3 at addresses 0002 and 0003 related to data 1 are read together with data 1 at address 0001 (these related data are read requests). After the read data, there is a high probability of being requested to read), the memory 15 is read, and error detection and correction of these data 1, 2 and 3 is executed in parallel. Then, the data 1, 2 and 3 subjected to error detection and correction are stored in the buffer memories 3a, 3b and 3c, and the data 1 requested from the MPU 14 is transferred to the MPU 14.
[0020]
Next, when the data 2 or 3 at the address 0002 or 0003 is requested from the MPU 14, as shown in FIG. 5, the control unit 7 shows the case where the data 0002 is read and requested. ) The data requested from the buffer memory 3b or 3c is transferred to the MPU 14.
FIG. 6 shows the execution timing of error detection and correction in parallel with the data 1, 2 and 3 in the example of FIG. 1, and FIG. 7 differs from the example of FIG. The execution timing in the case of performing error detection and correction in order.
In FIG. 6, time t₀Starts the error detection and correction for data 1 from time t₃And the data is transferred to the MPU 14 ((A), (B) and (E) in FIG. 6). And time t₃Previous time t₁Starts to detect and correct data 2 from time t₄And is stored in the buffer memory 3b ((A) and (C) in FIG. 6). Next, at time t₃Previous time t₂Starts to detect and correct data 3 from time t₅And is stored in the buffer memory 3c ((A) and (D) in FIG. 6).
[0021]
On the other hand, in the example of FIG.₀Starts the error detection and correction for data 1 from time t₃The data 1 is transferred to the MPU 14. Subsequently, time t₃Starts to detect and correct data 2 from time t₆At this point in time t₆Starts to detect and correct data 3 from time t₇End with.
[0022]
In the example of FIG. 6, the time t when the error detection and correction for the data 1 ends.₃Previously, error correction detection for data 2 and 3 has been started. Therefore, in the case of the example of FIG. 6, the time t when the error detection and correction of the data 2 in the example of FIG.₆Previously, error detection and correction of data 3 is completed.
[0023]
As described above, according to the first embodiment of the present invention, the data of the address requested to be read from the MPU 14 and the data of a plurality of addresses related to the data of this address are read, and the plurality of data Error detection and correction are executed in parallel by a plurality of ECC execution units. The data subjected to error detection and correction is stored in the data buffer.
[0024]
Therefore, it is possible to realize a data storage control device that can execute error detection and correction of a plurality of data at high speed, can read related data at high speed, and can improve memory use efficiency.
[0025]
In the above-described example, the related data is data at continuous addresses. However, the data is not necessarily data at continuous addresses.
In the above-described example, a separate buffer memory is arranged for each ECC execution unit. However, it is also possible to store a plurality of pieces of data that have been subjected to error detection and correction in one memory.
[0026]
In the data storage control device, in the case of partial write, that is, when writing data having a data length smaller than the data length that is the target of check bit generation into the memory, first, the data of the data length that is the target of check bit generation Is read from memory. Then, the ECC execution unit performs error detection and correction of the read data, and combines the data after error detection and correction and the write data (data length is small) from the MPU. The combined data is further written to the memory after generating check bits by the ECC execution unit.
[0027]
That is, in the ECC execution unit 200, a check bit is generated by an extended Hamming code for certain fixed-length data. For example, check bits of 5, 6, and 7 bits are generated for data of data lengths of 8, 16, and 32 bits, respectively. Data and a check bit for the data are written to the memory, and when the data is read from the memory, the check bit is also read at the same time, and error detection and correction of the data is performed based on the check bit.
[0028]
Assuming that 7-bit check bits are generated for 32-bit data, the write data from the MPU 14 is 8 or 16 bits, which is smaller than the data length (32 bits) for which check bits are generated. In this case, if the data is written in the memory as it is, the check bit does not become a value corresponding to the data.
[0029]
Therefore, as shown in FIG. 8A, in the partial write, first, the MPU 14 reads the check bits corresponding to the 32-bit data (d1d2d3d4) from the address of the memory 15 to which 8 or 16 bits are written, and performs ECC After performing error detection and correction by the unit 200, the multiplexer 1 combines the 32-bit data after execution of error detection and correction with the 8- or 16-bit write data (D1D2) from the MPU 14 to obtain 32-bit data (D1D2d3d4). To do.
[0030]
Then, as shown in FIG. 8B, check bits are generated by the ECC execution unit 200 for the 32-bit data (D1D2d3d4), and the 32-bit data and the check bits are written into the memory 15.
[0031]
As a result, partial write reads 32-bit data from the memory, performs error detection and correction of the read data, and generates check bits for data that is a combination of 8 or 16-bit data and 32-bit data. There was a need to perform a memory write.
[0032]
In order to eliminate the partial write, and to save time for error detection and correction by reading from the memory and executing ECC, it is also possible to generate 5 check bits for each byte (8 bits) which is the minimum unit of memory access. Conceivable. However, if 5 check bits are generated for every 8 bits, the check bit length is 20 bits for 32-bit data. As a result, the ratio of the check bit length to the data length increases and the use efficiency of the memory deteriorates.
[0033]
FIG. 9 is a schematic configuration diagram of a data storage control apparatus according to the second embodiment of the present invention, and is an example in which the memory write time of data in the partial write can be shortened. In the example of FIG. 9, the same reference numerals are given to the same components as in the example of FIG.
[0034]
In the example of FIG. 9, in the example of FIG. 1, the multiplexer 1 to which data from the buffer memories 3a, 3b, 3c, and MPU 14 is supplied, and check bits are generated for the data from the multiplexer 1, A check bit generation ECC execution unit 2 for storing the generated data and check bits in the memory 15 is added.
[0035]
FIG. 10 is an operation flowchart of the example of FIG.
In step 110 of FIG. 10, when there is a data write request from the MPU 14, the process proceeds to step 111 where the control unit 7 determines whether the write data is less than a predetermined length (for example, 32-bit length). Otherwise, go to step 114. In step 114, the write data is supplied from the MPU 14 to the check bit generation ECC execution unit 2 via the multiplexer 1, and a check bit is generated. Next, proceeding to step 115, the data and check bits from the MPU 14 are transferred from the ECC execution unit 2 to the memory 15 and stored therein.
[0036]
In step 111, if the write data is less than the predetermined length, the process proceeds to step 112, where the control unit 7 determines whether or not the data write address matches the address of the data stored in the buffer memories 3a, 3b, and 3c. judge. When the address requested to be written matches the address stored in the buffer memory, the process proceeds to step 113, where the data stored in the buffer memory and the data requested to be written are sent via the multiplexer 1 to the ECC execution unit 2. And both data are combined. Next, in step 114, check bits of the combined data are generated in the ECC execution unit 2. Subsequently, in step 115, the combined data and the check bit are stored in the memory 15. The states of steps 113, 114 and 115 are shown in FIG.
[0037]
If the address does not match the address stored in the buffer memory in step 112, the corresponding data is read from the memory 15 as shown in FIG. 8, and error detection correction, data combination, and check bit generation are executed. .
[0038]
That is, if the address does not match the address stored in the buffer memory, the process proceeds from step 112 to step 116 and the corresponding data (32 bits) having a predetermined length is read from the memory 15. Next, in step 117, the read data is subjected to error detection and correction by the ECC execution unit 4a, 4b or 4c.
[0039]
In step 118, the ECC execution unit 2 combines the error detection corrected data and the write requested data. Next, in step 114, check bits are generated. In step 115, the combined data and the generated check bits are stored in the memory 15.
[0040]
As described above, according to the second embodiment of the present invention, the same effects as the first embodiment can be obtained and the following effects can be obtained.
That is, in the case of partial write, when the address stored in the buffer memory matches the address of the data requested to be written, reading of the data 2 from the memory 15 and error detection correction of the read data become unnecessary. Partial light can be speeded up. As a result, the partial write speed can be increased as in the case where the check bit is generated for each byte without increasing the check bit length, and the memory use efficiency can be improved along with the higher memory access speed.
[0041]
FIG. 12 is a schematic configuration diagram of the third embodiment of the present invention. Components equivalent to those in the example of FIG. 9 are denoted by the same reference numerals. FIG. 13 is an operation flowchart of the third embodiment.
The examples shown in FIGS. 12 and 13 are examples in which the speed of the write operation can be increased even when the address of the data requested to be written is not stored in the buffer memory in the partial write.
[0042]
Steps 110 to 115 in FIG. 13 are the same as steps 110 to 115 in FIG.
If the address stored in the buffer memory does not match the address of the data requested to be written in step 112 in FIG. In step 116, data corresponding to the data requested to be written is read from the memory 15.
[0043]
Subsequently, the process proceeds to steps 117 and 119, where error detection of the data read by the ECC execution unit 4a is executed, and the data read by the ECC execution unit 2 and the data requested to be written are combined. In step 120, check bits of the combined data are generated (see FIG. 12).
[0044]
Next, the process proceeds from step 117 and step 120 to step 121, and the control unit 7 determines whether or not an error is detected in the data read by the ECC execution unit 4a. If no error is detected in the read data, the process proceeds to step 115, and the ECC execution unit 2 stores the combined data and the generated check bit in the memory 15 (see FIG. 14).
[0045]
In step 121, if an error is detected in the read data, the process proceeds to step 122, and error correction of the data is executed by the ECC execution unit 4a. Next, in step 123, the data corrected by the ECC execution unit 4a is supplied to the ECC execution unit 2 via the multiplexer 1 and combined with the write data. Subsequently, check bits are generated in steps 114 and 15, and the generated check bits and data are stored in the memory 15.
FIGS. 12 and 14 are examples in the case where the partial write is performed on the data 4 stored in the address 0004. FIG.
In this way, when there is a partial write request for data at an address not stored in the buffer memory, the corresponding data is read from the memory, an error is detected, and the data is read in parallel with this. A combination of data and data requested to be written and check bit generation are performed. When no error is detected, the combined data and check bits are stored in the memory 15. Since it is unlikely that an error is detected in the read data, most data is combined with the write data and stored in the memory 15 without error correction.
[0046]
Therefore, when there is no error in the read data, it is possible to omit the time required for the correction of the data, the subsequent combination of the corrected data and the write data, and the generation of the check bit.
[0047]
As described above, according to the third embodiment of the present invention, the same effect as in the second embodiment can be obtained. In the case of partial write, the address stored in the buffer memory and the address of the data requested to be written When the data does not match and no error is detected in the read data, the time required to correct the data, the subsequent combination of the corrected data and the write data, and the generation of the check bit can be omitted. Furthermore, it is possible to increase the speed of partial write.
[0048]
FIG. 15 is a schematic configuration diagram of the fourth embodiment of the present invention, and FIG. 16 is an operation flowchart of the example of FIG.
The example of FIG. 15 includes one error detection / correction ECC execution unit 4a and one check bit generation ECC execution unit 2, and differs from the first to third examples in reading data. In this example, the related data is not read. In the example of FIG. 15, in the case of partial write, the corresponding data is read from the memory and an error is detected in the same manner as in the third embodiment. In this example, combination with the combined data and check bit generation are performed, and when no error is detected, the combined data and check bit are stored in the memory 15.
[0049]
Therefore, in the flowchart shown in FIG. 16, steps 112 and 113 are omitted from the flowchart shown in FIG. Then, the process proceeds from step 111 to step 116, and steps 116, 117, and 119 to 123 are executed as in the example of FIG.
As described above, according to the fourth embodiment of the present invention, in the case of partial write, when no error is detected in the read data, the correction of the data, and the subsequent combination of the corrected data and the write data, The time required for generating the check bit can be omitted, and the partial write can be speeded up.
[0050]
In the above example, three examples of error detection and correction ECC execution units are shown, but the number is not limited to three and may be two or four or more.
[0051]
【The invention's effect】
Since the present invention is configured as described above, it has the following effects.
Data of the address requested to be read and data of a plurality of addresses related to the data of this address are read, and error detection and correction of the plurality of data are executed in parallel by a plurality of ECC execution units. The data subjected to error detection and correction is stored in the data buffer.
Therefore, it is possible to realize a data storage control device that can execute error detection and correction of a plurality of data at high speed, can read related data at high speed, and can improve memory use efficiency.
In the case of partial write, when the address stored in the buffer memory matches the address of the data requested to be written, reading of data from the memory and error detection / correction of the read data are not required, and partial write is performed at high speed. Can be As a result, the partial write speed can be increased as in the case where the check bit is generated for each byte without increasing the check bit length, and the memory use efficiency can be improved along with the higher memory access speed.
[0052]
In the case of partial write, the data corresponding to the address of the data to be written is read from the data storage means, the error of the data is detected, the combination with the data requested to be written, and the error detection / correction information of the combined data is generated. Executed in parallel. When no data error is detected, the combined data and the generated data error detection / correction information are stored in the data storage means.
[0053]
Accordingly, error correction of data read from the data storage means, a combination of error-corrected data and write-requested data, and subsequent generation of error detection / correction information are omitted, and data writing time is shortened. Can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a first embodiment of the present invention.
FIG. 2 is a functional block diagram of a control unit in the example of FIG.
FIG. 3 is a diagram illustrating data stored in each address of a memory.
4 is an operation flowchart of the example of FIG.
5 is an operation explanatory diagram when read request data is stored in a buffer memory in the example of FIG. 1; FIG.
FIG. 6 is an operation timing chart of data error detection / correction in the example of FIG. 1;
FIG. 7 is an operation timing chart of data error detection and correction in an example different from the present invention.
FIG. 8 is an operation explanatory diagram in the case of writing data smaller than the data width to be a check bit generation target.
FIG. 9 is a schematic configuration diagram of a second embodiment of the present invention.
10 is an operation flowchart of the example of FIG.
11 is an explanatory diagram of partial write operation when data corresponding to data requested to be written is stored in the buffer memory in the example of FIG. 9;
FIG. 12 is a schematic configuration diagram of a third embodiment of the present invention.
13 is an operation flowchart of the example of FIG.
14 is an operation explanatory diagram of the example of FIG. 12. FIG.
FIG. 15 is a schematic configuration diagram of a fourth embodiment of the present invention.
16 is an operation flowchart of the example of FIG.
[Explanation of symbols]
1 Multiplexer
2 ECC execution unit for check bit generation
3a, 3a, 3b Buffer memory
4a, 4b, 4c ECC execution unit for error detection and correction
5 Output controller
6 MPU data bus
7 Control unit
8 Memory data bus
9 Check bit bus
10 Memory address bus
11 Control signal line
12 MPU address bus
13 MPU control signal line
14 MPU
15 memory
71 Address comparison part
72 Data position notification bus
73 Data hit information line
74 Control signal generator
200 ECC execution unit

Claims (1)

Data storage control having data storage means for storing data and information for error detection and correction of the data, and controlling data reading and writing of the data storage means in response to data reading and writing requests from the data processor In the apparatus, data stored in the data storage means and information for error detection and correction of this data are supplied, and data error detection and correction means for detecting and correcting an error in the supplied data;
A buffer memory for storing data error-corrected by the data error detection and correction means;
Data error detection / correction information generating means for generating data error detection / correction information for data requested to be written by the data processor and storing the data requested for writing and the generated data error detection / correction information in the data storage means When,
In response to the data write request, the write requested data is less than the data length of the data stored in the data storage means, and the data at the address corresponding to the address where the write requested data is to be stored is the buffer memory. The data at the address is read from the data storage means and supplied to the data error detection / correction means and the data error detection / correction information generation means to detect data errors and In parallel with the error detection, the data read from the data storage means and the data requested to be written are combined so that the data length is equal to the data length, and the error detection / correction information of the combined data is generated. After that, when no data error is detected by the data error detection and correction means The combined data and the generated data error detection and correction information, is stored in the data storage means, in response to a data write request, the write requested data is located in the data below length of the data stored in the data storage means When the data at the address corresponding to the address where the requested data is to be stored is stored in the buffer memory, the data stored in the buffer memory and the requested data are Data error detection and correction information is generated for the combined data so that the data length is equal to the data length, and the combined data and the generated data error detection and correction information are stored in the data storage means. and data control means Ru is,
A data storage control means comprising:

Images