JP3676528B2 - Radio receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a radio receiver of a straight reception system that amplifies a signal received by an antenna as it is without converting it to an intermediate frequency signal and performs detection processing.
[0002]
[Prior art]
Radio receiver reception systems include a straight reception system that performs tuning and detection processing without frequency conversion of the signal received by the antenna, and tuning and detection after converting the signal received by the antenna to an intermediate frequency signal of a constant frequency. There is a superheterodyne system that performs processing. The straight reception method amplifies a high-frequency signal as it is, so that the self-oscillation is likely to occur due to coupling between circuits and the like, and the operation is likely to be unstable. Further, since the tuning frequency of the tuning circuit must be changed according to the reception frequency, the Q of the tuning circuit cannot be set so high in terms of the circuit configuration, and the frequency selectivity characteristic is deteriorated.
[0003]
On the other hand, since the superheterodyne method converts the signal once into a low frequency intermediate frequency signal, there is no possibility of oscillation even if the received signal is greatly amplified. Further, since the intermediate frequency is always constant regardless of the reception frequency, the Q of the tuning circuit can be set sufficiently high, and the frequency selectivity characteristic is improved. For this reason, recently, superheterodyne radio receivers have been dominant.
[0004]
[Problems to be solved by the invention]
However, in the superheterodyne system, when a signal of frequency f1 is received, a local oscillation signal of frequency f0 is used to convert it to an intermediate frequency (f0 -f1), so there is a broadcast wave of frequency (f0 + f1). If this happens, it will cause interference with this broadcast wave. In addition, when the local oscillation signal includes a harmonic component, so-called whistle sound interference may occur. Thus, as long as the superheterodyne system is adopted, there is a certain limit to the improvement of reception characteristics. In addition, the superheterodyne system requires a process of once converting to an intermediate frequency, and there is a problem that the configuration of the receiver is complicated.
[0005]
The present invention was created in view of the above points, and an object of the present invention is to provide a radio receiver of a straight reception system excellent in selectivity characteristics.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problem, the radio receiver according to claim 1 has a wide bandwidth so that sampling tuning circuits are connected in cascade and the frequency of the reference clock supplied to each sampling tuning circuit is shifted by a predetermined amount. In addition, the bandwidth does not fluctuate even if the tuning frequency is changed.
[0007]
In the radio receiver according to the second aspect, the sampling tuning circuits are connected in cascade with the amplifier interposed therebetween, so that a desired bandwidth can be obtained by adjusting the gain of the amplifier.
[0008]
The radio receiver according to claim 3 can be configured with a simple configuration in which an antenna is connected to an input side of a high-frequency amplifier circuit in which a sampling tuning circuit and an amplifier are connected in cascade, and a detection circuit is connected to an output side. . In addition, since there are no adjustment points and the number of components is reduced, a receiver having excellent reliability, maintainability, and cost performance can be obtained.
[0009]
The radio receiver according to claim 4 sets the number of connection stages of the sampling tuning circuit and the frequency of the reference clock so as to obtain an optimum bandwidth for AM broadcast reception.
[0010]
The radio receiver according to claim 5 sets the number of connection stages of the sampling tuning circuit and the frequency of the reference clock so as to obtain an optimum bandwidth for receiving FM broadcasts.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a radio receiver to which the present invention is applied will be specifically described with reference to the drawings.
[0012]
FIG. 1 is a block diagram of an embodiment of a radio receiver. The radio receiver shown in the figure is a straight reception type receiver that receives a desired AM broadcast wave without being converted to an intermediate frequency, and includes an antenna 1, a straight tuning unit 2, a detection circuit 3, a low frequency The amplifier circuit 4 and the speaker 5 are included.
[0013]
The straight tuning unit 2 selectively amplifies only the broadcast wave in the frequency band desired to be selected from the broadcast waves received by the antenna 1. The detailed configuration of the straight tuning unit 2 will be described later. The detection circuit 3 detects the modulated wave signal output from the straight tuning unit 2 and extracts a low-frequency signal. The extracted low-frequency signal is amplified by the low-frequency amplifier circuit 4 and then output from the speaker 5 as sound.
[0014]
FIG. 2 is a block diagram showing a detailed configuration of the straight tuning unit 2. As illustrated, the straight tuning unit 2 includes sampling tuning circuits 11a to 11c, amplifiers 12a to 12c, clock generation circuits 13a to 13c, and a control circuit 14, and each sampling tuning circuit 11a to 11c. Are connected in cascade with the amplifiers 12a to 12c interposed therebetween. The clock generation circuits 13a to 13c are provided corresponding to the sampling tuning circuits 11a to 11c, respectively, and supply reference clocks having different frequencies to the sampling tuning circuits 11a to 11c.
[0015]
FIG. 3 is a circuit diagram showing a detailed configuration of the sampling tuning circuits 11a to 11c. As shown in the figure, the sampling tuning circuits 11 a to 11 c are connected to a ring counter 401 having 16 outputs, a MOS transistor 402 connected to each output of the ring counter 401, and a drain terminal of each MOS transistor 402. The capacitor 403 is configured to include a resistor 404 and a capacitor 405 connected in parallel.
[0016]
FIG. 4 is a waveform diagram showing changes in the output of the ring counter 401. As shown in the figure, the ring counter 401 outputs a pulse at a rate of once every 16 periods of the reference clock output from the clock generation circuits 13a to 13c of FIG. More specifically, the ring counter 401 outputs a pulse having a period 16 times the reference clock from each output terminal. Further, the phase of the pulse output from each output terminal is shifted by one clock of the reference clock.
[0017]
Each output of the ring counter 401 is input to the gate terminal of the corresponding MOS transistor 402 as shown in FIG. Since the phases of the pulses output from the respective output terminals of the ring counter 401 are shifted from each other, the timing when the MOS transistor 402 is turned on is also different, and the capacitor 403 connected to the MOS transistor 402・ Repeat charge and discharge according to turning off.
[0018]
For example, when a signal having the same frequency as the pulse signal output from the ring counter 401, that is, a signal having a period 16 times the reference clock is input to the sampling tuning circuits 11a to 11c, the voltage at the point a in FIG. Changes stepwise as shown in FIG. On the other hand, when a signal having a frequency different from the frequency of the pulse signal is input to the sampling tuning circuits 11a to 11c, the voltage at the point a in FIG. Convergence to potential. Therefore, the sampling tuning circuits 11a to 11c shown in FIG. 3 can extract only a frequency component equal to the frequency of the pulse signal output from the ring counter 401.
[0019]
Since the line at point a in FIG. 3 has high impedance, there is a possibility that the output waveform cannot be taken out as it is if it is directly connected to a subsequent circuit having low input impedance. For this reason, it is desirable that the point a line is once received by the FET 406 as shown in FIG. 3, and the source terminal of the FET 406 is connected to the circuit of the subsequent stage. Note that the capacitor 407 in FIG. 3 is for cutting the DC component of the input signal, and the resistors 408 and 409 are for applying an appropriate bias to the FET 406.
[0020]
As described above, since the sampling tuning circuits 11a to 11c whose detailed configuration is shown in FIG. 3 are configured only by components that are easily semiconductorized such as the ring counter 401 and the MOS transistor 402, the entire circuit can be easily formed into a chip. Can do. Further, according to the circuit of FIG. 3, it is possible to easily increase the number of outputs in the ring counter 401 and increase the number of samplings in one cycle, thereby improving the tuning accuracy.
[0021]
Further, Q of the sampling tuning circuits 11a to 11c is represented by Q = πfCRN (C is the capacitance of the capacitor 403, R is the resistance value of the resistor 404, and N is the number of samplings), and the Q becomes higher as the frequency of the reference clock increases. Therefore, even if the tuning frequency is changed, the bandwidth Δf = f / Q can be kept constant, and tuning can be performed with the same accuracy over a wide range of frequencies.
[0022]
In the sampling tuning circuits 11a to 11c shown in FIG. 3, a CMOS transistor 402 ′ may be used instead of the MOS transistor 402 as shown in FIG. By using the CMOS-structured transistor 402 ', it is less susceptible to parasitic capacitance. In addition, since all elements constituting the sampling tuning circuits 11a to 11c can be formed by a CMOS process, the process for forming a chip can be simplified.
[0023]
The straight tuning unit 2 shown in FIG. 1 is configured by cascading sampling tuning circuits 11a to 11c whose detailed configuration is shown in FIG. 3 in three stages across amplifiers 12a to 12c, and to each sampling tuning circuit 11a to 11c. The frequency of the input reference clock is slightly shifted.
[0024]
For example, when the tuning frequency is f0 kHz, the frequencies of the reference clocks output from the clock generation circuits 13a to 13c are 16 * (f0- [Delta] f) kHz, 16 * f0 kHz, 16 * ( f0 + Δf) kHz is set. The frequency characteristics of the sampling tuning circuits 11a to 11c in this case are as shown in FIGS. 6 (a) to 6 (c), respectively. In FIG. 6, the horizontal axis indicates the frequency f, and the vertical axis indicates the signal intensity I.
[0025]
Therefore, the modulated wave signal from the antenna 1 is first input to the sampling tuning circuit 11a, and a component having a center frequency of (f0−Δf) kHz is extracted, then amplified once by the amplifier 12a, and then the sampling tuning circuit 11b. And the component having the center frequency of f0 kHz is extracted, and then amplified by the amplifier 12b and then input to the sampling tuning circuit 11c to extract the component having the center frequency of (f0 + Δf) kHz. As a result, the frequency characteristic of the signal output from the straight tuning unit 2 is as shown in FIG.
[0026]
When receiving an AM broadcast, it is desirable to set the above-described Δf to about 1 kHz, and the control circuit 14 is provided with each clock generation circuit 13a so that the above bandwidth is always obtained even if the tuning frequency is changed. The frequency of the reference clock output from ˜13c is adjusted.
[0027]
As described above, the straight tuning unit 2 in FIG. 1 has the three sampling tuning circuits 11a to 11c connected in cascade, and the tuning frequency of each sampling tuning circuit 11a to 11c is shifted little by little. Therefore, the bandwidth can be expanded as compared with the case of only AM, and the optimum bandwidth can be set for the AM radio receiver. Therefore, an AM radio receiver can be realized with a simple configuration in which the antenna 1 is connected to the input end of the straight tuning unit 2 and the detection circuit 3 is connected to the output end, and variations in electrical characteristics of the LC resonance circuit and the like occur. Since it does not include easy-to-use circuits, it is possible to obtain a radio receiver that does not require parts cost, does not require adjustment, and has excellent reliability and maintainability. Further, the frequencies of the reference clocks supplied to the sampling tuning circuits 11a to 11c are shifted by the same amount, and even if the tuning frequency is changed, the shift amount does not change. Therefore, the bandwidth is always constant regardless of the tuning frequency. Can be controlled. Further, as shown in the circuit of FIG. 3, the sampling tuning circuits 11a to 11c can accurately extract only the same frequency component as the pulse signal output from the ring counter 401, so that a radio receiver having excellent selectivity characteristics can be obtained. can get.
[0028]
FIG. 7 is a block diagram showing a detailed configuration of each clock generation circuit 13a-13c provided corresponding to each sampling tuning circuit 11a-11c. As shown in the figure, the clock generation circuits 13 a to 13 c include a voltage controlled oscillator 501, a programmable counter 502, a reference oscillator 503, a phase comparator 504, and a low-pass filter 505. The voltage controlled oscillator 501 outputs a reference clock, and the programmable counter 502 divides the reference clock by a preset division ratio. The phase comparator 504 performs phase comparison between the output of the programmable counter 502 and the reference oscillation signal from the reference oscillator 503. As a result, a voltage corresponding to the phase difference is applied to the voltage controlled oscillator 501 via the low pass filter 505. The voltage controlled oscillator 501 changes the frequency of the reference clock according to the output voltage of the low-pass filter 505, and performs an oscillation operation such that the output reference clock is synchronized with the reference oscillation signal.
[0029]
Further, as shown in FIG. 2, a control circuit 14 is connected to each of the clock generation circuits 13a to 13c, and a control signal output from the control circuit 14 is sent to a programmable counter 502 in each of the clock generation circuits 13a to 13c. Input, and the respective division ratios are set. Thus, the reference clock output from each of the clock generation circuits 13a to 13c is controlled so as to always change by the same amount.
[0030]
For example, when receiving 954 kHz AM broadcast waves, the division ratios of the programmable counters 502 in the clock generation circuits 13a to 13c are set to 953, 954, and 955, respectively. On the other hand, the frequency of the reference oscillation signal output from the reference oscillator 503 is set to 16 kHz. As a result, the frequencies of the reference clocks output from the clock generation circuits 13a to 13c are set to 953 kHz × 16 = 15.248 MHz, 954 kHz × 16 = 15.264 MHz, and 955 kHz × 16 = 15.280 MHz, respectively. These reference clocks are respectively input to the sampling tuning circuits 11a to 11c shown in FIG. 2 and divided by 16, and eventually selective tuning is performed in a range of ± 1 kHz with a center frequency of 954 kHz.
[0031]
As described above, the clock generation circuits 13a to 13c are provided corresponding to the sampling tuning circuits 11a to 11c, and the frequency of the reference clock output from each of the clock generation circuits 13a to 13c can be arbitrarily changed. Wide frequency range. Further, since the clock generation circuits 13a to 13c are controlled by the control circuit 14, the tuning frequency of each of the sampling tuning circuits 11a to 11c can be accurately changed at the same time by the same amount, and the bandwidth can be changed even if the tuning frequency is changed. Does not change, and stable tuning processing is always possible with the same accuracy.
[0032]
In the above embodiment, an example of a radio receiver capable of receiving AM broadcasts has been described, but the present invention is also applicable to receiving FM broadcasts. FIG. 8 is a block diagram of one embodiment of an FM radio receiver. The straight tuning unit 2 'is configured in the same manner as in FIGS. 1 and 2, and the output of the straight tuning unit 2' is input to the FM detection circuit 3 '. The FM detection circuit 3 'converts the FM modulated wave signal selected by the straight tuning unit 2' into a stereo composite signal, which is input to the stereo demodulation circuit 6 and separated into an L signal and an R signal. Is done. These L signal and R signal are separately input to the de-emphasis circuits 7L and 7R, respectively, and after the high frequency range is attenuated to improve the S / N ratio, the low-frequency amplifier circuits 8L and 8R are passed through the speakers 9L and 9R. Sound is output.
[0033]
Since the FM broadcast wave has a higher frequency than the AM broadcast wave, the frequency of the reference clock output from the clock generation circuits 13a to 13c shown in FIG. It is necessary to set to an optimal value. For example, the bandwidth of the straight tuning unit 2 is desirably about 150 to 200 kHz.
[0034]
By the way, as shown in FIG. 2, when receiving an AM broadcast, it is most desirable to cascade three stages of sampling tuning circuits in consideration of bandwidth and Q. In principle, however, two stages or four stages or more are used. It may be. Further, in the above-described example, the reference oscillator 503 is provided in each of the clock generation circuits 13a to 13c as shown in FIG. 7, but since each reference oscillator 503 performs an oscillation operation at the same frequency, a common reference oscillator is provided. May be shared.
[0035]
【The invention's effect】
As described in detail above, according to the present invention, since a plurality of sampling tuning circuits are connected in cascade to perform tuning, the bandwidth can be made wider than when only one stage of the sampling tuning circuit is provided. Further, the conventional straight receiver system has a problem that the Q cannot be set very high for the purpose of making the tuning frequency variable. However, since the present invention tunes digitally in synchronization with the reference clock, Can be set sufficiently high, and a radio receiver having excellent selectivity characteristics can be obtained. Further, since the frequency of the reference clock input to each of the cascaded sampling tuning circuits is variably controlled, the bandwidth can always be controlled to be constant even if the tuning frequency is changed.
[0036]
Also, unlike the superheterodyne system, no conversion to intermediate frequencies is performed, so there is no disturbance such as image interference or whistle noise, and the overall receiver circuit configuration is simplified compared to the superheterodyne system. As a result, parts costs can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a radio receiver capable of receiving AM broadcasts.
FIG. 2 is a block diagram showing a detailed configuration of a straight tuning unit.
FIG. 3 is a circuit diagram showing a detailed configuration of a sampling tuning circuit.
FIG. 4 is a waveform diagram showing a change in output of a ring counter.
FIG. 5 is a diagram showing an example of a transistor having a CMOS configuration used in the sampling tuning circuit.
6A to 6C are frequency characteristic diagrams of each sampling tuning circuit, and FIG. 6D is a frequency characteristic diagram of a straight tuning unit.
FIG. 7 is a block diagram showing a detailed configuration of a clock generation circuit.
FIG. 8 is a block diagram of an embodiment of a radio receiver capable of receiving FM broadcasts.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Antenna 2 Straight tuning part 3 Detection circuit 4 Low frequency amplifier circuit 5 Speaker 11a-11c Sampling tuning circuit 12a-12c Amplifier circuit 13a-13c Clock generation circuit 14 Control circuit

Claims (7)

In a radio receiver that performs detection processing by extracting only the frequency components desired to be selected from the received signal received by the antenna,
A plurality of cascades that extract only the same frequency component as the pulse signal from the received signal based on a result of sampling the received signal with a pulse signal having a period that is an integral multiple of a reference clock and synchronized with the reference clock A connected sampling tuning circuit;
A plurality of clock generation circuits provided corresponding to each of the sampling tuning circuits and supplying the reference clocks shifted by a predetermined amount to each sampling tuning circuit ;
A control circuit that varies the reception frequency by changing the frequency of each reference clock generated by each of the plurality of clock generation circuits by the same amount;
Radio receiver, characterized in that it comprises a. In claim 1,
  Each of the plurality of clock generation circuits has a configuration in which a voltage oscillator, a programmable counter that performs a frequency dividing operation, a phase comparator, and a low-pass filter are connected in a loop, and a reference oscillation output from a reference oscillator A radio receiver that generates the reference clock having a frequency obtained by multiplying a frequency of a signal by a frequency division ratio of the programmable counter. In claim 2,
  A radio receiver characterized in that the common reference oscillator is used corresponding to the plurality of clock generation circuits. In any one of Claims 1-3,
  A radio receiver characterized in that each of the sampling tuning circuits is cascaded through an amplifier. In claim 4,
  A radio receiver characterized in that a high-frequency amplifier circuit is constituted by the sampling tuning circuit and the amplifier connected in cascade, the antenna is connected to the input side of the high-frequency amplifier circuit, and a detector circuit is connected to the output side . In claim 5,
  An AM detection circuit for converting an AM modulated wave signal into a signal before modulation;
  A radio characterized in that the number of connection stages of the sampling tuning circuit and the frequency of the reference clock are set so that a bandwidth capable of receiving AM broadcast is obtained, and the output of the high-frequency amplifier circuit is input to the AM detection circuit. Receiving machine. In any one of Claims 1-6,
  An FM detection circuit that converts the selected FM modulated wave signal into a stereo composite signal in which the L signal and the R signal are combined;
  A radio characterized in that the number of connection stages of the sampling tuning circuit and the frequency of the reference clock are set so that a bandwidth capable of receiving FM broadcasting is obtained, and the output of the high-frequency amplifier circuit is input to the FM detection circuit. Receiving machine.

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