JP3678291B2 - Transmission delay improvement circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transmission delay improvement circuit that improves a delay margin on the receiving side due to waveform rounding in data transmission to improve noise tolerance.
[0002]
[Prior art]
In a general data transmission system, data level determination at the receiving end is determined by whether the voltage level of the data input terminal of the input buffer is higher or lower than the voltage level of the reference voltage terminal, which is the other input terminal. The At this time, the time from the determination of the level at the data input terminal to the rising edge of the clock input to the next flip-flop (hereinafter abbreviated as F / F) is the time required for holding data in the F / F ( Hereinafter, it is a condition that data transmission is accurately performed.
[0003]
[Problems to be solved by the invention]
However, as shown in FIG. 4, in the conventional synchronous transfer system, when data transmission is performed via a cable of several meters, the rising and falling waveforms are rounded due to the waveform attenuation in the cable, and the reference voltage is crossed. There is a problem that the timing is shifted backward, and as a result, the setup time of F / F: Tsu is not satisfied and data transmission is not performed accurately.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a transmission delay improvement circuit that prevents malfunction on the receiving end side due to noise superimposed on data, and improves system performance by improving delay and reliability by improving noise tolerance. .
[0005]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention changes the reference voltage value, which has been a fixed value in the past, to advance the timing of crossing the data voltage, ensure the F / F setup time: Tsu, Data transmission is ensured even at timings that were not possible with the transmission method, and the same data is input to two input buffers with different reference voltages, and the output level is monitored. It is characterized by preventing malfunction on the end side.
[0006]
With the above configuration, the system performance is improved by improving the delay and the reliability is improved by improving the noise tolerance.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0008]
Referring to FIG. 1, the receiving circuit 2 has two input buffer circuits for inputting data voltages distributed in two to the input terminals. In each of the input buffers 3-1 and 3-2, reference voltages Vref 1 and Vref 2 that receive the output voltage of the input buffer and vary to different voltage levels are input to the other input terminals.
[0009]
The output of the input buffer 3-1 is input to the next stage F / F 9. Also, an AND circuit 8 having two inputs, an output of an exclusive NOR circuit (hereinafter abbreviated as EX_NOR) 6 for inputting an output voltage of the input buffers 3-1 and 3-2 and a clock 7 for synchronous transfer, The output of the AND circuit 8 is input to the clock terminal of the F / F 9.
[0010]
Next, the operation of the receiving circuit will be described. In the receiving circuit 2, the data waveform transmitted via the cable 1 is divided into two and input to the data input terminals of the input buffers 3-1 and 3-2, respectively. Since the input capacitance is doubled, the waveform rounding increases accordingly, but it is assumed that the influence is smaller than the waveform rounding due to cable attenuation. Further, since the two distributions are made in the receiver LSI chip, the distance between the input buffers is short, and the influence of reflection is set to a level at which no problem occurs. The other input terminals of the input buffers 3-1 and 3-2 are supplied with the output voltages of the reference voltage sources 4-1 and 4-2 that change in response to the output voltage of the input buffer.
[0011]
Next, the operation of the reference voltage sources 4-1 and 4-2 (hereinafter abbreviated as Vref1 and Vref2) will be described with reference to FIG.
[0012]
Vref1 includes resistors R1, R2, R3 and an N_ch field effect transistor Tr1. The level of the output voltage of the input buffer 3-1 is inverted by the inverter circuit INV1 and input via the delay circuit DL1 to the gate terminal of the field effect transistor Tr1.
[0013]
When the output voltage of the input buffer 3-1 becomes high level (power supply voltage level), the inverter circuit INV1 inverts it to low level, so that the field effect transistor Tr1 is delayed by an arbitrary delay time set by the delay circuit DL1. Turns off.
[0014]
When the field effect transistor Tr1 is turned off, Vref1 is
Vref1 = R2 / (R1 + R2)
It becomes.
[0015]
When the output voltage of the input buffer 3-1 is at the low level (ground voltage level), the inverter circuit INV1 inverts the signal to the high level, so that the electrolytic effect is delayed by an arbitrary delay time set by the delay circuit DL1. The transistor Tr1 is turned on.
[0016]
When the field effect transistor Tr1 is turned on, Vref1 is
Vref1 = (R2 // (R3 + Ron)) / {R1 + (R2 // (R3 + Ron))}
However, R2 // (R3 + Ron)... R2 and (R3 + Ron) are connected in parallel (Ron: N_ch field effect transistor on-resistance value).
[0017]
When the output level of the input buffer 3-1 is low level (transistor on), the parallel connection resistance value of R2 and (R3 + Ron) is smaller than the resistance value R2 at high level (transistor off). The value of Vref1 is larger than that at the low level.
[0018]
On the other hand, the circuit configuration of Vref2 is substantially the same as the circuit of the reference voltage source: Vref1, but in order to input the output voltage of the input buffer 3-2 to the gate terminal of the field effect transistor Tr2, the inverter circuit is deleted and the delay is made. Input is made only through the circuit DL2. Therefore, since the field effect transistor Tr2 is turned on when the output level of the input buffer 3-2 is at a high level and is turned off when the output level of the input buffer 3-2 is low, the value of Vref2 at the high level is smaller.
[0019]
Note that the voltage level at which both Vref1 and Vref2 can be varied can be arbitrarily set according to the resistance value to be used.
[0020]
Next, the operation will be described in detail with reference to FIGS. Data with a large rounded waveform is input to the input buffers 3-1 and 3-2 via the cable 1, respectively.
[0021]
In the input buffer 3-1, when the data changes from the high level to the low level, since the output voltage of the input buffer 3-1 is at the high level in the Vref1 before the data change, the N_ch field effect transistor Tr1 is turned off and the low level. It is set to a value larger than the time, that is, a value close to the data voltage value. Therefore, the data level is determined at an early timing, and a time that satisfies the setup time of the next stage F / F: Tsu is secured. The delay time is set by the delay circuit DL1 so that the value of Vref1 changes after the data is determined.
[0022]
The same applies when the data changes from the Low level to the High level.
[0023]
The input buffer 3-2 is used to prevent erroneous recognition of the data level in the F / F when voltage fluctuation (noise) occurs such that data and Vref1 cross each other.
[0024]
Vref2 input to the input buffer 3-2 is set so as to be at a level distant from the voltage value of data, contrary to Vref1. That is, when the data changes from the High level to the Low level, Vref2 is a value lower than that at the Low level because the output voltage of the input buffer 3-2 is at the High level before the data change, so that the field effect transistor Tr2 is turned on. That is, since it is set to a value that is distant from the data voltage level, the output level of the input buffer 3-2 does not change even if noise is superimposed on the data waveform.
[0025]
If the data level changes normally, the output levels of the input buffers 3-1 and 3-2 are the same. Therefore, the outputs of the input buffers 1 and 2 are input to the EX_NOR circuit 6 (a high level is output if they are the same level, and a low level is output if they are different levels), and the output of the EX_NOR circuit 6 and the synchronous clock 7 are input to the AND circuit 8. When the input and the output of the AND circuit 8 are input to the clock terminal of the F / F circuit 9, if the outputs of the input buffers 3-1 and 3-2 are at the same level, the output of the EX_NOR circuit 6 becomes a high level. The rising edge of 7 becomes valid, and if the level is different, the output of the EX_NOR circuit 6 becomes a low level, so the rising edge of the clock 7 becomes invalid, and the receiving circuit has noise tolerance.
[0026]
As described above, by varying the reference voltage of the input buffer before the F / F, the delay margin can be improved by determining the data level at an early timing, and the same data is input and the reference voltage is By preparing an input buffer that can be changed to a value different from the reference voltage of the input buffer, it is possible to determine whether the data voltage level change is due to noise or normal level change, and prevent malfunction due to noise. be able to.
[0027]
【The invention's effect】
As described above, the present invention can improve the system performance and reliability by improving the delay margin tightness at the setup timing due to waveform rounding during cable transmission and providing a receiver circuit with noise tolerance.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a transmission delay improvement circuit of the present invention.
FIG. 2 is a configuration diagram of a reference voltage source used in a transmission delay improvement circuit of the present invention.
FIG. 3 is a time chart showing the operation of the transmission delay improving circuit of the present invention.
FIG. 4 is an explanatory diagram showing waveform rounding in a conventional synchronous transfer method.
[Explanation of symbols]
1 Cable 2 Receiving circuit 3-1, 3-2 Input buffer 4-1, 4-2 Reference voltage source 5-1, 5-2 Delay circuit 6 Exclusive NOR circuit (EX_NOR)
7 Clock for synchronous transfer 8 AND circuit 9 Flip-flop (F / F)

Claims (5)

In the receiving circuit for data transmission,
First and second input buffer circuits that receive the transmitted data signal as input and output the result of comparison with a reference voltage;
A flip-flop circuit which receives the output of the first input buffer circuit,
An exclusive NOR circuit that receives the outputs of the first and second input buffer circuits;
An AND circuit that receives the output of the exclusive NOR circuit and the synchronous transfer clock; and
First and second variable voltage sources connected to other input terminals of the first and second input buffer circuits, respectively , and outputting a variable voltage as the reference voltage,
The output of the AND circuit is the clock input of the flip-flop circuit,
An output of the first input buffer circuit is connected to an input of the first variable voltage source through a first delay circuit, and the first variable voltage source outputs an output voltage in the same direction according to the input change. is varied,
The output of the second input buffer circuit is connected to the input of the second variable voltage source via a second delay circuit, and the second variable voltage source outputs an output voltage in the opposite direction according to the input change. A transmission delay improvement circuit characterized by changing the frequency. In the receiving circuit for data transmission,
First and second input buffer circuits that receive the transmitted data signal as input and output the result of comparison with a reference voltage;
A flip-flop circuit having the output of the first input buffer circuit as an input;
An exclusive NOR circuit that receives the outputs of the first and second input buffer circuits;
An AND circuit that receives the output of the exclusive NOR circuit and the synchronous transfer clock; and
First and second variable voltage sources connected to other input terminals of the first and second input buffer circuits, respectively, and outputting a variable voltage as the reference voltage,
The output of the AND circuit is the clock input of the flip-flop circuit,
The output of the first input buffer circuit is connected to the input of the first variable voltage source via an inverter circuit and a first delay circuit, and the first variable voltage source is in the opposite direction according to the input change. Change the output voltage to
The output of the second input buffer circuit is connected to the input of the second variable voltage source via a second delay circuit, and the second variable voltage source outputs an output voltage in the opposite direction according to the input change. A transmission delay improvement circuit characterized by changing the frequency. The first and second variable voltage sources are connected in series with the first resistance element on the power supply side and the second resistance element on the ground side, and with the third resistance element and the switching element connected in series. , Configured in parallel with the second resistance element,
3. The transmission delay improving circuit according to claim 2 , wherein an output of the delay circuit is input to a gate of the switching element. 4. The transmission delay improving circuit according to claim 3 , wherein the switching element is an N-channel field effect transistor. The delay times of the first and second delay circuits, transmission delay correction circuit according to any one of claims 1 to 4, characterized in that larger than the setup time of the flip-flop circuit.

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