JP3678331B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data amplification circuit capable of high-speed data amplification and a semiconductor memory device using the same.
[0002]
[Prior art]
In recent years, the speeding up of CPUs, the performance of applications, and the speeding up of the entire system have progressed, and therefore, the speed of random access is demanded in addition to the speed of data transfer in the main memory. On the other hand, portable information terminal devices are strongly required to reduce the power consumption of the main memory in order to enable long-time battery operation. Until now, in DRAMs, a method of operating an internal element using an internal step-down power supply VINT has been taken in order to ensure the reliability of the internal element and reduce power consumption. The data amplification, especially the amplification speed of the sense amplifier, has been slowed down, which has prevented the speeding up of random access.
[0003]
Conventionally, this has been dealt with using the following method.
[0004]
The first method is a method disclosed in Japanese Patent Laid-Open No. 9-204777. At the start of the amplification operation of the sense amplifier, the external power supply is temporarily used as the power supply voltage of the sense amplifier instead of the internal step-down potential VINT. In this method, the potential VDD is used.
[0005]
This is a method proposed to solve the following problems. That is, when the data read from the memory cell by the sense amplifier is amplified, a large amount of current is consumed in the sense amplifier section. Originally, the internal step-down power supply potential VINT is used as the power supply potential of the sense amplifier to reduce power consumption, but the current supply capability of the internal step-down power supply potential VINT is limited. For this reason, at the time of data amplification in the above-described sense amplifier, a voltage drop due to insufficient charge supply occurs, and the data amplification speed of the sense amplifier is slowed down.
[0006]
On the other hand, in the method disclosed in the above Japanese Patent Laid-Open No. 9-204777, as shown in FIG. 16, the power supply potential of each sense amplifier drive circuit is switched between the internal high voltage power supply potential VINT and the external power supply potential VDD. A power supply voltage switching circuit is provided for each sense amplifier block so that an external power supply potential VDD having sufficient charge supply capability is switched and supplied instead of the internal step-down power supply potential VINT at the time of data amplification. By switching the power supply potential, a delay in the data amplification speed of the sense amplifier due to insufficient charge supply is prevented, and a high speed is realized.
[0007]
The second method is disclosed in Japanese Patent Application Laid-Open Nos. 9-330591 and 10-1225067, in which read data from a cell is once taken into a sense amplifier and then amplified. In this method, the switching transistor (shared switch: SS) between the sense amplifier and the bit line is completely closed.
[0008]
This method is a method proposed to solve the following problems. Normally, when the sense amplifier is not selected, the gate potential of the shared switch is the external power supply potential VDD. The gate potential of the shared switch on the memory cell side selected at the time of selection of the sense amplifier transits to the word line boosted potential VPP which is the rewrite potential, and the gate potential of the non-selected side shared switch transits to the ground potential VSS. The switch is closed. However, since the shared switch is fully open when the data is amplified by the sense amplifier, the capacity and resistance of the bit line on the memory cell side act as a load on the sense amplifier through this shared switch, and the sense amplifier The amplification operation was delayed.
[0009]
On the other hand, in the systems disclosed in the above-mentioned JP-A-9-330591 and JP-A-10-1225067, as shown in FIG. 17A, when a word line is activated, a shared switch is used. Is opened, and the read charge from the memory cell is taken into the sense amplifier. Thereafter, the gate potential of the shared switch is lowered from the external power supply potential VDD to the ground potential VSS, and the shared switch is completely closed. As a result, at the time of subsequent data amplification by the sense amplifier, the capacity and resistance of the bit line on the memory cell side do not become a load of the sense amplifier via the shared switch, and the data amplification operation of the sense amplifier is accelerated. Can be realized. After data amplification, the gate potential of the shared switch is raised from the ground potential VSS to the power supply potential VPP of the word line all at once, and rewriting is performed.
[0010]
The third method is a method disclosed in the paper [ISSCC-1997 DIGEST OF TECHNICAL PAPER P.66-67], in which the gate potential of the shared switch at the time of data amplification by the sense amplifier is set to a minute value from the memory cell. In this method, the read charge is suppressed to a minimum level necessary for being taken into the sense amplifier.
[0011]
In this system, as shown in FIG. 17B, when the sense amplifier is not selected, the gate potential of the shared switch is set to the ground potential VSS, and the shared switch is closed, thereby closing the bit line and the memory on the sense amplifier side. The bit line on the cell side is completely separated. At this time, the bit line precharge potential on the sense amplifier side is set to a potential higher than the bit line precharge potential on the memory cell side. When the sense amplifier is selected, the gate potential of the shared switch is raised to the minimum level (β + Vtn) (Vtn is the threshold voltage of the NMOS transistor) that is necessary for reading charges from the memory cell into the sense amplifier. The data amplification operation is performed by the sense amplifier. When rewriting to the memory cell, the gate potential of the shared switch does not change, and the necessary and minimum level is maintained because the read charge from the memory cell is taken into the sense amplifier.
[0012]
Therefore, when the sense amplifier is selected, the bit line on the sense amplifier side has a higher precharge potential and a smaller capacity than the bit line on the memory cell side. When the data is taken in, the potential difference between the bit lines of the bit line pair (BIT, / BIT) becomes larger than that in the previous reading (the potential on the Low side drops and the potential difference from the Hi side increases). This reduces the load on the sense amplifier caused by the capacitance and resistance of the bit line on the memory cell side from the shared switch during data amplification by the sense amplifier, and the potential difference between the paired bit lines at the start of the amplification operation. By increasing the size, it was attempted to increase the data amplification speed of the sense amplifier.
[0013]
The fourth method is a method using an inverter chain connected with a capacitor as a timing setting delay element for starting a sense amplifier.
[0014]
As shown in FIG. 18, in order to match the delay characteristics of the start / stop timing of the sense amplifier with the RC delay characteristics of the rise and fall times of the word line from the start of the word line, In this method, the delay time of the stop timing is set using an inverter chain connected with a capacitor as the delay circuit. As a result, it becomes a circuit configuration that can eliminate the extra delay time of the start / stop timing of the sense amplifier with respect to the start / stop timing of the word line required corresponding to the temperature change, and the start timing of the sense amplifier is advanced. I was trying to achieve high speed.
[0015]
[Problems to be solved by the invention]
However, these conventional methods also have the following problems.
[0016]
With respect to the first method, although the amount of charge supplied at the time of data amplification by the sense amplifier increases, the supply charge from the voltage switching circuit is insufficient with respect to the charge consumed by the sense amplifier operating simultaneously when the sense amplifier block is selected. A situation was invited. For this reason, the amplification capability of the sense amplifier cannot be sufficiently increased, and the effect of increasing the data amplification speed cannot be obtained sufficiently.
[0017]
Regarding the second method, it is difficult to adjust the timing for reducing the gate potential of the shared switch to the ground potential VSS after taking the read charge from the memory cell into the sense amplifier. In this timing setting, it is necessary to add a timing margin in consideration of power supply voltage dependency, temperature dependency, and process variation. For example, the power supply voltage dependency has the following problems. The time required for reading from the sense amplifier may be short when the power supply voltage is high, but long when the power supply voltage is low. For this reason, if the timing is set in accordance with the readout characteristics at the time of low voltage, the shared switch is closed before data is taken in at the time of readout at the time of high voltage. On the other hand, if the timing is set in accordance with the read characteristic at the time of high voltage, the shared switch is not easily closed even when data is taken in at the time of read at low voltage, which causes a delay in starting the sense amplifier. In other words, it may be possible to increase the speed of the amplification operation of the sense amplifier itself, but it is difficult to increase the operation speed including the activation and rewriting of the sense amplifier while accurately adjusting the timing.
[0018]
In addition, since the gate potential of the shared switch is boosted from the ground potential VSS to the power supply potential of the word line at the time of rewriting, the burden on the word line boosted potential generating circuit, which is the potential generating circuit, increases. An increase in power consumption in the generation circuit itself by increasing the charge supply capability of the generation circuit and an increase in chip area due to an increase in capacitance to reduce fluctuations in the word line boost potential are caused.
[0019]
In the third method, although the read potential difference from the memory cell between the paired bit lines (BIT, / BIT) can be increased during data amplification, rewriting to the cell is not possible only with this shared switch potential control method. Therefore, the configuration of the sense amplifier needs to be complicated. Specifically, it is necessary to install a P-type MOS transistor on the bit line side of the shared switch for sufficiently raising the level of Hi side data. However, when this configuration is adopted, two P-type MOS transistors are added as compared with a normal sense amplifier, and the area of the sense amplifier itself is increased and the structure is complicated when well separation is taken into consideration. Also, when inverting the memory cell data, it is necessary to invert according to the data that captures the potential difference between the bit lines via the P-type MOS transistor with the shared switch in between, so the operation of writing different data to the memory cell Cause a delay in speed.
[0020]
As for the fourth method, the sense amplifier start / stop timing is set by setting the delay characteristics of the sense amplifier start signal generation circuit to changes in the external power supply voltage and process variations, and the time from the start of the word line to the rise of the word line. Because the difference in the delay characteristics of the time from the stop to the fall of the word line must be taken into account, it is necessary to provide a margin for the start / stop timing of the sense amplifier with respect to the start / stop timing of the word line This causes a delay in the activation timing of the sense amplifier.
[0021]
The main object of the present invention is to improve the read operation speed without violating the demand for lower voltage, lower power consumption and smaller size.
[0022]
More specifically, supplying sufficient charges when amplifying the memory cell data by the sense amplifier, reducing the load of the sense amplifier during data amplification while simplifying the potential switching control of the gate potential of the shared switch, It is possible to reduce the burden of the word line potential generation circuit at the time of writing, or to match the timing of starting and stopping the sense amplifier with the timing of starting and stopping the word line while ensuring a sufficient writing potential to the memory cell. An object of the present invention is to provide a semiconductor memory device.
[0023]
[Means for Solving the Problems]
The present invention Half of The conductor storage device includes a memory cell array in which memory cells for storing information are arranged in a matrix, and a word extending along a row of the memory cell array and connected to each memory cell arranged along the row A line, a bit line extending along the column of the memory cell array and connected to each memory cell arranged along the column, and a word line of the memory cell array and connected to the bit line. A plurality of sense amplifier arrays configured by a plurality of sense amplifiers for amplifying information stored in the memory cells, and a plurality of sense amplifiers provided for each of the sense amplifier arrays and supplying a sense amplifier drive signal to each sense amplifier An amplifier driving circuit and a plurality of power supply voltages are received, an output is switched to one of the plurality of power supply voltages, and the output is switched to the sense amplifier drive. And a power supply voltage control circuit for supplying a power supply voltage to the circuit, the power supply voltage control circuit, a sense amplifier driving circuits arranged along the bit line (4A, 4B, 4C) Arranged in each Sense amplifier drive power supply wiring for supplying sense amplifier drive power to the plurality of sense amplifier drive circuits extends along the bit line. .
[0024]
As a result, individual power supply voltage control circuits are connected to a plurality of sense amplifier drive circuit groups operating simultaneously, so that the charge supply capability to each sense amplifier is improved. This is because a power supply voltage control circuit is provided for each sense amplifier drive circuit arranged in the direction of the bit line with a small number of sense amplifiers operating at the same time. A sufficient charge can be supplied to the sense amplifier when the cell data is amplified.
[0025]
In the first semiconductor memory device, one of the plurality of power supply potentials is set as an internal step-down potential, and the power supply voltage control circuit is configured to use only the internal step-down potential as the sense amplifier drive circuit in the low power consumption mode. By configuring so that power is supplied, power consumption in an operation (for example, CBR refresh, self-refresh, etc.) in the low power consumption mode is reduced.
[0026]
In the first semiconductor memory device, one of the plurality of power supply potentials is an internal step-down potential, and is interposed between the bit line and the sense amplifier, and switches between a conductive state and a non-conductive state. A switching transistor and a sense amplifier control circuit that holds the gate potential of the switching transistor at the internal step-down potential for a predetermined time when the switching transistor is in a conductive state can be further provided.
[0027]
As a result, even if the power supply voltage of the sense amplifier is switched to the external power supply potential for data amplification by the sense amplifier control circuit, the gate potential of the switching transistor is suppressed to about the internal step-down potential, so the memory cell side sandwiching the switching transistor This bit line is suppressed to the internal step-down power supply potential or lower without being boosted to the external power supply potential.
[0028]
In the first semiconductor memory device, by arranging the power supply voltage control circuit on both sides of the memory cell array, the charge supply capability is maintained high even when the number of word lines activated simultaneously is large.
[0051]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described. A semiconductor memory device in each of the following embodiments specifically functions as a so-called DRAM.
[0052]
(First embodiment)
First, a semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings.
[0053]
−Configuration−
FIG. 1 is a circuit diagram showing a schematic configuration of the semiconductor memory device according to the present embodiment.
[0054]
As shown in FIG. 1, the semiconductor memory device according to the first embodiment of the present invention has a memory cell array in which a large number of memory cells 9 are arranged in a matrix (in the figure, one memory cell is divided into memory cells). Only the cell block 19 is displayed), a sense amplifier block 10 provided with the sense amplifier 5 and the like, and power supply voltage switching circuits 1A, 1B, 1C. The sense amplifier block 10 includes a sense amplifier activation circuit 2, a sense amplifier control circuit 3X, sense amplifier drive circuits 4A, 4B, and 4C, and sense amplifier rows 6A and 6B in which a large number of sense amplifiers 5 are arranged. ing. In the present embodiment, the power supply voltage switching circuits 1A, 1B, and 1C function as power supply voltage control circuits.
[0055]
A number of word lines 7 extending in the row direction and connected to the gate electrodes of the memory cells 9 and a number of bit lines 8 extending in the column direction and connected to the drains of the memory cells 9 are provided. Yes. The memory cell 9 includes a memory cell transistor and a memory cell capacitor connected to the source of the memory cell transistor. The sense amplifier 5 is connected to the bit line 8 and detects whether the data is “0” or “1” according to the charge held by the memory cell capacitor. The sense amplifier drive circuits 4A, 4b, 4C and the sense amplifier control circuit 3X control the operation of each sense amplifier 5. The sense amplifier starting circuit 2 starts and stops the amplification operation of each sense amplifier drive circuit 4A, 4B, 4C. In the memory cell block 19, a large number of memory cells are arranged in a matrix, and a large number of word lines 7 and a large number of bit lines 8 exist. Although connected to the bit line, since this structure is a well-known memory cell block structure, their display is omitted. Further, a large number of memory cell blocks 19, 19 and sense amplifier blocks are alternately arranged on the left side of the figure, but their display is omitted in FIG.
[0056]
Here, the semiconductor memory device according to the present embodiment is characterized in that the power supply voltage switching circuits 1A, 1B, and 1C receiving the external power supply potential VDD and the internal step-down power supply potential VINT lower than this are provided for each sense amplifier row 5. For example, each of the sense amplifier drive circuits 4A, 4B, and 4C that are provided is individually provided, and power is supplied to the drive power supply wirings 12a, 12B, and 12C that extend in parallel to the bit lines 8. The voltage switching circuits 1A, 1B, and 1C are connected. That is, in general common sense, the control of the sense amplifier is performed in units of the sense amplifier block 10, but in this embodiment, the sense amplifier drive circuit group arranged along the bit line across the plurality of sense amplifier blocks 10. For example, the power supply voltage switching circuit 1A is provided for each sense amplifier drive circuit group in which only the sense amplifier drive circuit 4A in each sense amplifier block 10 is extracted.
[0057]
The power supply voltage switching circuits 1A, 1B, and 1C receive the bank selection signal Sbs input via the wiring 11, switch the output signal between the external power supply voltage VDD and the internal step-down power supply potential VPP, and output the output signal. The drive power supply wirings 12A, 12B, and 12C are supplied to the sense amplifier drive circuits 4A, 4B, and 4C, respectively. The drive power supply wirings 12A, 12B, and 12C are connected to each other by the power connection wiring 13, but the power connection wiring 13 is not necessarily provided.
[0058]
When the sense amplifier activation circuit 2 receives the address selection signal Sas through the wiring 14, the sense amplifier activation circuit 2 outputs a sense amplifier activation signal Ssa for starting and stopping the amplification operation of the memory cell data at the address, and this sense amplifier activation signal Ssa is sent to the sense amplifier drive circuits 4A, 4B, and 4C through the wiring 15.
[0059]
FIG. 2 is a circuit diagram showing a connection relationship between the configuration in the sense amplifier 5 and the sense amplifier control circuit 3X. As shown in the figure, the sense amplifier 5 includes a memory cell data amplifier circuit 24 interposed in the bit line 8 and a pair of shared switches interposed in the bit line 8 with the memory cell data amplifier circuit 24 interposed therebetween. 25A and 25B (switching MOS transistors). The gates of the shared switches 25A and 25B are connected to the sense amplifier control circuit 3X via wirings 16A and 16B, respectively. In other words, FIG. 1 shows only one wiring 16 connecting the sense amplifier control circuit 3X and each sense amplifier 5, but in actuality it is a pair of wirings.
[0060]
The sense amplifier control circuit 3X receives the address selection signal Sas and outputs shared switch control signals SctA and SctB for controlling the gate potentials of the shared switches 25A and 25B from the wirings 16A and 16B, and this shared switch control signal SctA. , SctB controls on / off of the shared switches 25A, 25B. That is, when one shared switch 25A is opened, the data of the memory cell 9 is taken into the memory cell data amplifier circuit 24 via the bit line 8. When the other shared switch 25B is opened, data of a memory cell (not shown) arranged on the left side in the drawing is taken into the memory cell data amplifier 24.
[0061]
Each sense amplifier drive circuit 4A, 4B, 4C receives the external power supply VDD or the internal step-down potential VINT supplied via the drive power supply wirings 12A, 12B, 12C and the sense amplifier activation signal Ssa, and drives the sense amplifier. The signal Ssd is output, and the sense amplifier drive signal Ssd is supplied to the sense amplifiers 5 in the sense amplifier arrays 6A and 6B via the sense amplifier power supply potential wiring 17.
[0062]
The bank selection signal Sbs may be a signal for distinguishing activation between a low power consumption mode such as a CBR refresh operation and a self-fresh operation and an external access operation mode.
[0063]
-Circuit operation-
Next, the operation of the semiconductor memory device having the above configuration will be described.
[0064]
First, during the selection operation of a certain memory cell 9, the output of the power supply voltage switching circuits 1A, 1B, 1C is switched from the internal step-down power supply potential VINT during standby to the external power supply potential VDD by the bank selection signal Sbs. In parallel with this, in the sense amplifier block 10 selected across the memory cell block 19, the shared switch control signal SctA (or SctB) for controlling the gate potential of the shared switch 25A (or 25B) is activated. The memory cell data read onto the bit line 8 is taken into the sense amplifier 5. After the memory cell data is taken in, the sense amplifier activation signal Ssa is activated, and the sense amplifier drive circuits 4A, 4B, and 4C start operating. Then, the potential of the sense amplifier power supply potential wiring 17 is switched from the bit line precharge level to the external power supply potential VDD, and the sense amplifier 5 performs an operation of amplifying the memory cell data.
[0065]
The supply path of the power supply voltage of the sense amplifier 5 when the memory cell data is amplified differs depending on the arrangement location. That is, the path through which the power supply voltage is supplied from the power supply voltage switching circuit 1A via the sense amplifier drive circuit 4A and the drive power supply wiring 12A, and the power supply voltage via the sense amplifier drive circuit 4B and the drive power supply wiring 12B. There are a path supplied from the power supply voltage switching circuit 1B and a path where the power supply voltage is supplied from the power supply voltage switching circuit 1C via the sense amplifier drive circuit 4C and the drive power supply wiring 12C.
[0066]
When a certain time elapses after the memory cell data is amplified, the power supply voltage switching circuits 1A, 1B, and 1C return the potentials of the drive power supply lines 12A, 12B, and 12C from the external power supply potential VDD to the internal step-down power supply potential VINT. When the potential of the shared switch control signal Sct rises at this timing and the gate potential of the shared switch 25A (or 25B) is boosted to the word line boost potential VPP, the rewrite operation is started. This timing can be adjusted by using a delay circuit for the wiring 11 through which the bank selection signal Sbs flows, for example.
[0067]
Here, the bank selection signal Sbs is divided into a low power consumption mode such as CBR refresh and self refresh operation and an external access operation mode, and the power supply voltage switching operation by the power supply voltage switching circuits 1A, 1B and 1C is performed with a low power consumption operation. It is preferable to adopt a configuration that is not performed in the mode. The reason is that the supply voltage is increased when the sense amplifier 5 is accessed. In order to shorten the time required for access, it is necessary to quickly extract data from the sense amplifier 5 after the address selection signal from the column decoder is input. This is because the data needs to be quickly amplified in the sense amplifier 5 before the address selection signal Sas from the column decoder is input. However, since the CBR refresh, self-refresh operations, etc. are performed regardless of external access, it is not necessary to increase the speed as described above. Therefore, a control that switches the supply voltage to the sense amplifier from the internal step-down potential VINT to the external power supply voltage VDD only in the external access operation mode in an operation unrelated to external access such as CBR refresh and self-refresh. May be performed.
[0068]
-Effect-
As described above, in the semiconductor memory device of this embodiment, the power supply voltage switching circuits 1A, 1B, and 1C are arranged along the bit line 8 as the power supply voltage supply source of the sense amplifier. Therefore, when the memory cell data is amplified, it is possible to supply charges necessary for data amplification in the sense amplifier 5 from these voltage switching circuits 1A, 1B, 1C. It is possible to prevent the supply of charges necessary for Hi-side data amplification, which occurred when the sense amplifiers 5 in the sense amplifier arrays 6A and 6B are simultaneously activated, and to increase the data amplification speed of the sense amplifiers.
[0069]
In particular, the sense amplifier drive circuits 4A, 4B, and 4C are connected by the drive power supply wirings 12A, 12B, and 12C that extend along the bit line 8 from the power supply voltage switching circuits 1A, 1B, and 1C. The ability improvement effect is increased. The reason is that the number of sense amplifiers connected to the wirings connecting the sense amplifier drive circuits 4A, AB, and AC along the direction of the word line 7 is about 1000, for example, as in the present embodiment. When the sense amplifier circuits 4A, 4B, 4C are connected along the bit line 8 direction by the supply wirings 12A, 12B, 12C, the number of sense amplifiers connected to the drive power supply wirings 12A, 12B, 12C is as follows. This is because the load on the drive power supply wirings 12A, 12B, and 12C is significantly reduced because of being reduced to about 1/9 to 1/8.
[0070]
Further, when a relatively low power consumption mode such as CBR refresh or self-refresh operation, that is, a relatively high speed data amplification operation of the sense amplifier is relatively unnecessary, a control configuration in which the bank selection signal Sbs is not generated in this operation mode is adopted. Therefore, only in this operation mode, power supply voltage switching control by the power supply voltage switching circuits 1A, 1B, 1C is not performed, so that the drive power supply wirings 12A, 12B, 12C to the sense amplifier drive circuits 4A, 4B, 4C Therefore, it is possible to eliminate the charge / discharge of the wiring accompanying the potential change with the sense amplifier power supply potential wiring 17, and to reduce the CBR current, the self-refresh current, and the like.
[0071]
(Second Embodiment)
Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings.
[0072]
−Configuration−
Also in this embodiment, the configuration of the sense amplifier 5 and the sense amplifier control circuit 3X shown in FIG. 2 described in the first embodiment is adopted.
[0073]
FIG. 3 is a circuit diagram showing a specific configuration of the sense amplifier control circuit 3X according to the present embodiment. As shown in FIG. 3, the sense amplifier control circuit 3X includes a PMOS transistor 28 that supplies a word line boosted potential VPP to the gates of the shared switches 25A and 25B, a ground potential VSS, and an external power supply potential VDD (VDDmax = VPP−Vtn). , An NMOS transistor 30 that receives the output of the inverter 29 at its drain, and an inverter 31 of a power supply voltage VPP that supplies the gate (node 2) potential of the NMOS transistor 30. Here, the node 1 is a node between the output side of the inverter 29 and the drain of the NMOS transistor 30, the node 2 is a node between the output side of the inverter 31 and the gate of the NMOS transistor 30, and the node 3 is This is a node connected to the gate of the PMOS transistor 28.
[0074]
-Circuit operation-
FIG. 4 is a timing chart showing the sequence of operations of the shared switch control signals SctA and SctB and the sense amplifier control circuit 3X for generating the control signals SctA and SctB during the read operation of the semiconductor memory device according to the present embodiment. .
[0075]
As shown in the figure, when the word line of the memory cell block 19 is selected (timing tws in the figure), when the inverter 29 is driven by the rising edge of the address selection signal Sas, the ground potential VSS is maintained during standby. The shared switch control signal SctA to the shared switch 25A on the selected word line side is boosted from the node 1 via the NMOS transistor 30 to a value determined by the potential of the node 1 by the external power supply (potential VDD). At this time, since the potential of the node 3 is still the word line boosted potential VPP, the PMOS transistor 28 is in an OFF state. Further, since the potential of the node 2 is the standby word line boosted potential VPP, the NMOS transistor 30 is in the on state. Therefore, the shared switch control signal SctA of the shared switch 25A is the external power supply potential VDD when VDD ≦ VPP−Vtn (Vtn is the threshold voltage of the NMOS transistor 30), and the potential when VDD> VPP−Vtn. The voltage is boosted to (VPP-Vtn). That is, the voltage is boosted to the potential VDD when the external power supply potential VDD is low, and to the potential (VPP−Vtn) when the external power supply potential VDD is high.
[0076]
Subsequently, when the sense amplifier activation signal Ssa transitions from the ground potential VSS to the external power supply potential VDD (timing trw in the figure), the potential of the node 2 is changed to the ground potential VSS, and then the potential of the node 3 is also changed to the ground potential VSS. Transition. At this time, the NMOS transistor 30 is turned off and the PMOS transistor 28 is turned on. The shared switch control signal SctA to the shared switch 25A is boosted to the word line boosted potential VPP for rewriting data to the memory cell via the PMOS transistor 28.
[0077]
On the other hand, at the time of resetting the word line (timing twr in the figure), the potential of the node 3 transitions to the word line boosted potential VPP (the PMOS transistor 28 is turned off) due to the fall of the address selection signal Sas. By resetting the sense amplifier activation signal Ssa (falling from the external power supply potential VDD to the ground potential VSS), the potential of the node 2 becomes the word line boosted potential VPP (the NMOS transistor 30 is turned on), so that the shared switch 25A The shared switch control signal SctA is stepped down to the ground potential VSS that is the potential of the node 1 through the NMOS transistor 30.
[0078]
It should be noted that the boosting timing (timing trw in the figure) of the shared switch control signal SctA for rewriting data to the memory cell is delayed by a certain time from the rise of the sense amplifier activation signal Ssa, as shown by the broken line in FIG. It may be timing. Alternatively, the boost timing of the shared switch control signal SctA for rewriting may be set to a timing that is later than the rising edge of the address selection signal Sas by a certain time.
[0079]
Here, the shared switch control signal SctB of the shared switch 25B of the memory cell block on the non-selected side (not shown in FIG. 2, but present on the left side of the sense amplifier control circuit 3X) , And is maintained at the ground potential VSS.
[0080]
-Effect-
As described above, in the semiconductor memory device according to the present embodiment, the gate potential (shared switch control signal SctA) of the shared switch 25A is set to the external power supply potential VDD for a certain period during which the memory cell data is amplified in the sense amplifier 5. In particular, when the external power supply potential VDD is low, the charge (load) for charging / discharging the shared switch 25A to the bit line 22 on the memory cell side by the sense amplifier 5 is reduced when the external power supply potential VDD is low. For this control, it is not necessary to perform the operation of opening the shared switch 25A from the closed state during the operation of taking the memory cell data into the sense amplifier as in the technique of the above-mentioned conventional publication. There is no difficulty in timing adjustment, and the operation speed including the activation of the sense amplifier 5 can be increased.
[0081]
In the data rewrite operation (timing trw in FIG. 4), the gate potential (shared switch control signal SctA) of the shared switch 25A that has already been boosted to the external power supply potential VDD (or VPP-Vtn) is boosted to the word line. The potential difference that needs to be boosted by the word line boosted potential generation circuit (not shown) is merely the voltage boosted to the potential VPP. The difference between the word line boosted potential VPP and the external power supply potential VDD (VPP to VDD) ) Therefore, the boosted potential difference can be greatly reduced as compared with the conventionally required boosted potential difference (VPP to VSS), and the charge supply capability of the word line boosted potential generating circuit can be suppressed. Therefore, the power consumption of the word line boosted potential generation circuit can be reduced, and the chip area can be reduced by reducing the smoothing capacitance by suppressing the charge supply capability.
[0082]
(Third embodiment)
Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to the drawings.
[0083]
−Configuration−
FIG. 5 is a circuit diagram showing a schematic configuration of the semiconductor memory device according to the present embodiment.
[0084]
As shown in the figure, in addition to the configuration of the semiconductor memory device according to the first embodiment, the semiconductor memory device according to the present embodiment outputs signals from the power supply voltage switching circuits 1A, 1B, and 1C (drive power supply). A voltage switching timing generation circuit 18 for controlling the timing of switching the power supply supplied to the sense amplifier drive circuits 4A, 4B, 4C via the supply wirings 12A, 12B, 12C to the external power supply potential VDD and the internal step-down potential VINT. It has. In the present embodiment, the power supply voltage switching circuits 1A, 1B, 1C and the voltage switching timing generation circuit 18 constitute a power supply voltage control circuit. Further, the shared switch control signal Sct (shared switch control signals SctA, SctB), which is an output signal of the sense amplifier control circuit 3, is set to the internal step-down power supply potential VINT for a certain period when the memory cell data is amplified by the sense amplifier 5. It is configured to hold a potential (VINT + Vtn) obtained by adding the potential of the threshold voltage (Vtn) of the NMOS transistor 30 (see FIG. 3). Other configurations are the same as those of the semiconductor memory device according to the first embodiment.
[0085]
In this embodiment, the voltage switching timing generation circuit 18 is connected to the wiring 11 and receives the bank selection signal Sbs as an input signal. In the first embodiment, which outputs the sense amplifier activation signal Ssa. The circuit configuration is the same as that of the sense amplifier starting circuit 2.
[0086]
FIG. 6 is a circuit diagram showing a configuration of the sense amplifier control circuit 3Y in the present embodiment.
[0087]
As shown in the figure, in addition to the configuration of the sense amplifier control circuit 3X in the second embodiment, the sense amplifier control circuit 3Y in the present embodiment includes an inverter 44 provided on the previous stage side of the node 6, and an inverter And an NMOS transistor 46 interposed between the NMOS transistor 30 and two NMOS transistors 47 and 48 interposed in a power supply line connected to the node 5 between the NMOS transistor 46 and the NMOS transistor 30. And a circuit 49 for determining a potential when the power is turned on. However, the nodes 1, 2, and 3 in FIG. 3 are displayed as nodes 4, 5, and 6 in FIG. The drain of the NMOS transistor 47 is connected to a power supply for supplying the internal step-down power supply potential VINT.
[0088]
-Operation-
In the semiconductor memory device according to the present embodiment, the power supply potential switching operation of the power supply voltage switching circuits 1A, 1B, and 1C is controlled by the voltage switching timing generation circuit 18 during the memory cell selection operation. That is, the drive power supply wirings 12A, 12B, and 12C are switched after a predetermined time has elapsed since the voltage switching in which the potentials of the drive power supply wirings 12A, 12B, and 12C are switched from the internal step-down potential VINT to the external power supply potential VDD and the amplification of the memory cell data. Is switched in accordance with the data amplifying operation of the sense amplifier 5.
[0089]
The shared switch control signal Sct is changed from the potential (VINT + Vtn) to the word line boosted potential VPP in accordance with the voltage switching timing from the external power supply voltage VDD to the internal step-down power supply potential VINT of the sense amplifier power supply wirings 12A, 12B, 12C. The voltage is boosted, and a data rewrite operation is performed.
[0090]
FIG. 7 is a timing chart showing the shared switch control signal Sct during the read operation of the semiconductor memory device according to the present embodiment and the operation sequence of the sense amplifier control circuit 3Y that generates this signal Sct.
[0091]
As shown in the figure, when the word line of the memory cell block 19 is selected (timing tws in the figure), when the inverter 29 is driven by the rising edge of the address selection signal Sas, the ground potential VSS is maintained during standby. The shared switch control signal Sct is driven and boosted by an external power supply. At this time, the node 5 is boosted from the potential (VPP−Vtn) of the difference between the standby word line boosted potential VPP and the threshold voltage Vtn of the NMOS transistor 30 by the self-boot effect by the NMOS transistor 30. However, the maximum value of the potential of the node 5 is the potential (VINT + 2) obtained by adding the internal step-down potential VINT and the threshold voltages of the NMOS transistors 47 and 48 (both are Vtn) by the NMOS transistor 47 and the NMOS transistor 48. × Vtn). At this time, the PMOS transistor 28 is in an off state, and the NMOS transistor 30 is in an on state. Therefore, the voltage value of the shared switch control signal Sct is set to the maximum value potential (VINT + Vtn) by the nodes 4 and 5 and the NMOS transistor 29. However, this maximum value varies depending on the value of the external power supply potential VDD of the node 4, and when the external power supply potential VDD is equal to or lower than the potential (VINT + Vtn), it becomes the external power supply potential VDD, and the external power supply voltage VDD is equal to or higher than the potential (VINT + Vtn). In this case, the potential is (VINT + Vtn).
[0092]
Subsequently, when the sense amplifier activation signal Ssa transitions from the ground potential VSS to the external power supply potential VDD (timing trw in the figure), the potential of the node 5 is changed to the ground potential VSS, and subsequently the potential of the node 6 is also changed to the ground potential VSS. Transition. At this time, the NMOS transistor 30 is turned off and the PMOS transistor 28 is turned on. The shared switch control signal SctA to the shared switch 25A is boosted to the word line boosted potential VPP for rewriting data to the memory cell via the PMOS transistor 28.
[0093]
On the other hand, at the time of resetting the word line (timing twr in the figure), the potential of the node 6 transitions to the word line boosted potential VPP (the PMOS transistor 28 is turned on) due to the fall of the address selection signal Sas. As the sense amplifier activation signal Ssa is reset (falling from the external power supply potential VDD to the ground potential VSS), the potential of the node 5 becomes the potential (VPP−Vtn) (the NMOS transistor 30 is turned on), so the shared switch 25A. The shared switch control signal SctA is stepped down to the ground potential VSS that is the potential of the node 4 through the NMOS transistor 30.
[0094]
Note that the boosting timing (timing trw in the figure) of the shared switch control signal Sct for data rewriting to the memory cell is delayed by a certain time from the rising edge of the sense amplifier activation signal Ssa, as shown by the broken line in FIG. It may be timing. Alternatively, the boosting timing of the shared switch control signal Sct for rewriting may be set to a timing that is delayed for a certain time from the rising edge of the address selection signal Sas.
[0095]
-Effect-
As described above, the semiconductor memory device according to the present embodiment holds the potential (VDD + Vtn) obtained by adding the internal step-down power supply potential VINT and the threshold voltage Vtn of the NMOS transistor to the shared switch control signal Sct for a certain period. By providing the control circuit 3Y, the gate potentials of the shared switches 25A and 25B can be suppressed to a potential (VINT + Vtn) or less when the read data is amplified by the sense amplifier 5. As a result, as in the first and second embodiments, the bit line load of the sense amplifier 5 is reduced for a certain period during data amplification. Therefore, for the above reason, the data amplification operation at the time of low voltage is performed. The speed can be increased.
[0096]
In addition, in this embodiment, even if the potential of the sense amplifier power supply potential wiring 17 is switched to the external power supply voltage VDD by the power supply voltage switching circuits 1A, 1B, and 1C, the sense amplifier 5 is connected with the shared switches 25A and 25B interposed therebetween. Thus, the potential of the bit line 8 on the memory cell side can be suppressed to the internal step-down power supply potential VINT or less without excessively boosting the external power supply voltage VDD, and the reliability of the memory cell transistor 9 can be improved.
[0097]
In this case, by making the configuration of the voltage switching timing generation circuit 18 the same as that of the sense amplifier starting circuit 2, when the data is amplified by the sense amplifier 5, driving according to the timing of the memory cell data amplification by the sense amplifier 5 is performed. The potential of the power supply wirings 12A, 12B, and 12C can be switched from the external power supply voltage VDD to the internal step-down power supply potential VINT. Thus, the timing for switching the potential of the drive power supply wirings 12A, 12B, and 12C from the external power supply voltage VDD to the internal step-down power supply potential VINT, and the potential of the shared switch control signal Sct from the potential (VINT + Vtn) to the word line boosted potential. Since the timing for switching to the VPP can be relatively matched, the rewrite operation can be speeded up while ensuring the reliability of the memory cell transistor 9.
[0098]
(Fourth embodiment)
Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to the drawings.
[0099]
−Configuration−
FIG. 8 is a circuit diagram showing a schematic configuration of the semiconductor memory device according to the present embodiment. The semiconductor memory device according to the present embodiment is different from the semiconductor memory device according to the third embodiment in that the power supply voltage switching circuit and the voltage switching timing generation circuit described above are paired with a memory cell array, a sense amplifier, and the like interposed therebetween. The difference is that it is provided.
[0100]
That is, as shown in FIG. 8, a memory cell array & sense amplifier unit 41 including a memory cell array and sense amplifier block 10 (FIG. 5 shows some of the memory cell blocks 19 and sense amplifier block 10). A pair of voltage switching units 52T and 52B are provided in which power supply voltage switching circuits 1AT, 1BT, 1CT and 1AB, 1BB, 1CB and voltage switching timing generation circuits 18T, 18B are respectively arranged. . However, the detailed structure of the memory cell array & sense amplifier section 41 can be easily understood from FIG. Between the power supply voltage switching circuit 1AT and the power supply voltage switching circuit 1AB, between the power supply voltage switching circuit 1BT and the power supply voltage switching circuit 1BB, and between the power supply voltage switching circuit 1CT and the power supply voltage switching circuit 1CB, respectively. They are connected by drive power supply wirings 12A, 12B, 12C for supplying output signals to the sense amplifier drive circuits 4A, 4B, 4C.
[0101]
Here, although not shown in FIG. 8, the voltage switching timing generation circuits 18T and 18B adjust the difference in time when the bank selection signal Sbs reaches the voltage switching timing generation circuits 18T and 18B from the transmission source. A circuit is provided for this purpose.
[0102]
-Operation-
Also in the present embodiment, the voltage switching operation of the drive power supply wirings 12A, 12B, and 12C is the same as the operation described in the third embodiment. However, in the voltage switching units 52T and 52B installed across the memory cell array, the difference in arrival time of the bank selection signal Sbs, which is the activation signal, to each circuit is adjusted by the voltage switching timing circuits 18T and 18B, and the driving is performed. The operation of switching the potentials of the power supply wirings 12A, 12B, and 12C is performed at the same timing.
[0103]
In addition, also in this embodiment, since the voltage switching timing circuits 18T and 18B have the same configuration as the sense amplifier starting circuit 2, the switching operation is relatively synchronized with the starting and stopping operations of the sense amplifier 5. Done.
[0104]
-Effect-
As described above, in the semiconductor memory device of this embodiment, the voltage switching timing circuits 18T and 18B and the power supply voltage switching circuits 1AT to 1CT and 1AB to 1CB are installed on both sides of the memory cell array & sense amplifier unit 41. Thus, even when the number of word lines selected simultaneously per memory cell array increases with an increase in storage capacity, the data supply speed of the sense amplifier can be increased by maintaining a high charge supply capability during data amplification by the sense amplifier. The speed can be increased.
[0105]
(Fifth embodiment)
Next, a semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to the drawings.
[0106]
−Configuration−
FIG. 9 is a circuit diagram showing a schematic configuration of the semiconductor memory device according to the present embodiment.
[0107]
The semiconductor memory device according to the present embodiment is premised on a semiconductor memory device having the same configuration as the semiconductor memory device shown in the first embodiment. However, the power supply voltage switching circuits 1A, 1B, and 1C shown in FIG. 1 are not necessarily provided, or the power supply voltage switching circuit may be provided at the position shown in FIG. Although a sense amplifier control circuit and a sense amplifier drive circuit are not shown, these circuits are also generally provided.
[0108]
As shown in FIG. 9, the semiconductor memory device according to the present embodiment includes a word line selection signal generation circuit 61, a word line drive signal generation circuit 62, a word line drive circuit 63, and a sense amplifier activation circuit 2X. ing. The sense amplifier activation circuit 2X according to the present embodiment has the same circuit configuration as the dummy word line selection signal generation circuit 67 and the word line drive signal generation circuit 62 that have the same circuit configuration as the word line selection signal generation circuit 61. A dummy word line drive signal generation circuit 68, a dummy word line drive circuit 69 having the same circuit configuration as the word line drive circuit 63, and a timing adjustment delay circuit 70 are provided. The word line selection signal generation circuit 61, the word line drive signal generation circuit 62, and the word line drive circuit 63 shown in FIG. 9 are also provided in the semiconductor memory device according to each of the above embodiments. The memory cell 9 in which the memory cell transistor 64 and the memory cell capacitor 65 are arranged is arranged in the memory cell block 19 shown in FIG. 1, and the sense amplifier 5 has the sense amplifier array 6A, FIG. Although it is arranged at 6B, it is shown here in an isolated state for easy understanding of the operation.
[0109]
Reference numeral 74 denotes a wiring to which a row address signal (row block selection signal) Srb, which is an activation signal of the word line selection signal generation circuit 61, is input. Reference numeral 75 denotes a wiring to which a word line activation signal Swa is input. Further, similar to the configuration shown in FIG. 1 and the like, the sense amplifier is a signal for starting and stopping the sense amplifier in accordance with the reading of the memory cell data by the word line 7, the bit line 8, and the word line 7 and the selection of the word line. Wiring such as the wiring 15 through which the signal Ssa flows is provided.
[0110]
-Operation-
First, the word line setting operation will be described.
[0111]
The word line drive signal generation circuit 62 operates in response to the word line activation signal Swa, and subsequently, the word line selection signal generation circuit 61 operates in response to the row address signal Srb. The output signal of the word line drive signal generation circuit 62 and the word line The word line driving circuit 63 is driven by the output signal of the selection signal generating circuit 61 to activate the memory cell selecting word line 7. When the memory cell selection word line 7 is activated, charges are read from the memory cell 9 to the bit line 8 through the memory cell transistor 64. The charge read from the memory cell 9 is amplified by the sense amplifier 5 activated by the sense amplifier activation signal Ssa. After completion of the setting operation of the word line 7 (operation in which the read charge from the memory cell is taken into the sense amplifier 5), the setting operation of the sense amplifier activation signal Ssa is started.
[0112]
Next, the word line reset operation will be described.
[0113]
First, the word line drive signal generation circuit 62 is reset by resetting the word line activation signal Swa. Thereby, the reset of the potential of the word line 7 to the ground potential VSS is started via the word line driving circuit 63. Subsequently, the word line selection signal generation circuit 61 is reset by resetting the word line activation signal Swa. After completion of the reset operation of the word line 7, the reset operation of the sense amplifier activation signal Ssa is started.
[0114]
Next, the setting operation by the sense amplifier activation signal Ssa will be described.
[0115]
First, similarly to the activation of the memory cell selection word line 7, the dummy word line drive signal generation circuit 68 operates in response to the word line activation signal Swa, and then the dummy word line selection signal generation circuit 67 in response to the row address signal Srb. The dummy word line drive circuit 69 is activated by the output signal of the dummy word line drive signal generation circuit 68 and the output signal of the dummy word line selection signal generation circuit 67. The output signal of the dummy word line driving circuit 69 is output as a sense amplifier activation signal Ssa via the delay circuit 70. The delay circuit 70 has a delay value that optimizes the timing shift of the sense amplifier activation signal Ssa with respect to the rising timing of the memory cell selection word line 7 at that time. That is, when the potential of the word line 7 rises and data comes out from the memory cell 9, both timings are adjusted so that the sense amplifier 5 is operated to start the data amplification operation.
[0116]
Next, the reset operation of the sense amplifier activation signal Ssa will be described.
[0117]
After the reset operation of the word line 7 is completed, the dummy word line drive signal generation circuit 68 is reset by resetting the word line activation signal Swa. As a result, the reset operation by the sense amplifier activation signal Ssa is started via the dummy word line driving circuit 69 and the delay circuit 70. Subsequently, the word line selection signal generation circuit 67 is reset by resetting the row address signal Srb. The delay circuit 70 has such a delay value that the shift of the falling timing of the sense amplifier activation signal Ssa with respect to the falling timing of the memory cell selection word line 72 is optimized.
[0118]
-Effect-
As described above, the semiconductor memory device according to the present embodiment is a circuit (word line selection signal circuit 61, word line control circuit) for controlling the operation from selection to generation of the memory cell selection word line 7 and from non-selection to reset. A circuit (dummy word line selection signal circuit 67, dummy word line drive signal generation circuit 68) for controlling the operation up to the generation of the sense amplifier start signal Ssa and the reset, and the line drive signal generation circuit 62 and the word line drive circuit 63). , The dummy word line drive circuit 69) have the same circuit configuration, so that the potential of the memory cell selection word line 7 depends on the power supply voltage, the temperature, and the process variation (for example, the variation in the gate length of the transistor). Is matched with the power supply voltage dependency, temperature dependency, and process variation dependency of the start / stop timing of the sense amplifier 5 Door can be. That is, the direction and the degree of change of the potential of the word line 7 and the sense amplifier activation signal Ssa according to changes in the power supply voltage, temperature, etc. are made almost common, so the influence of changes in these parameters. As a result, the speed of data amplification by the sense amplifier can be increased.
[0119]
However, since it is sufficient that the timing as a whole is not greatly changed by the change of each parameter, for example, only the dummy word line selection signal generation circuit 67 may have the same layout as the word line selection signal generation circuit 61. The dummy word line drive signal generation circuit 68 may not have the same layout as the word line drive signal generation circuit 62. Further, the dummy word line driving circuit 69 may not have the same layout as the word line driving circuit 63.
[0120]
Next, FIG. 10 is a circuit diagram showing a configuration of a semiconductor memory device according to a modification of the present embodiment. As shown in the figure, the sense amplifier activation circuit 2Y does not include the dummy word line drive signal generation circuit 68 as shown in FIG. A sense amplifier activation signal Ssa is output in response to the output and the word line boosted potential VPP. The configuration of this modification can also simplify the circuit configuration while exhibiting the same effects as those of the semiconductor memory device of the present embodiment as described above.
[0121]
Here, as the activation signal of the word line selection signal generation circuit 61 and the word line activation signal Swa, for example, a normal word line selection signal that is an output signal of the redundancy determination circuit or a redundancy word line selection signal is used. If the stop timing is made common, the circuit configuration can be further simplified. That is, since the potential of the word line 7 and the sense amplifier activation signal Ssa change the timing and the degree of change according to changes in the power supply voltage, temperature, etc., the influence of these parameter changes is affected. The expected timing margin can be minimized, and as a result, the data amplification by the sense amplifier can be speeded up.
[0122]
(Sixth embodiment)
Next, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to the drawings.
[0123]
−Configuration−
FIG. 11 is a circuit diagram showing a part of the memory cell array of the semiconductor memory device according to this embodiment, and FIG. 12 is a cross-sectional view showing the structure of the memory cell of the semiconductor memory device according to this embodiment. This embodiment also assumes the configuration of the semiconductor memory device shown in FIG. However, the power supply voltage switching circuits 1A, 1B, and 1C shown in FIG. 1 are not arranged. Then, the word line selection signal generation circuit 61, the word line drive signal generation circuit 62, the word line drive circuit 63, and the sense amplifier activation circuit 2 shown in FIG. 9 or FIG. It is a premise to have.
[0124]
As shown in FIG. 11, the semiconductor memory device according to this embodiment includes a memory cell 9 used for reading and writing data, and a memory cell selection word line that also functions as the gate of the memory cell transistor of each memory cell 9. 7. Further, the memory cell is composed of a memory cell transistor and a memory cell capacitor having the same structure as that of the memory cell 9, and is made of the same material as that of the memory cell selection word line 7 and the dummy memory cell 82 which is not normally used for reading and writing data. A dummy wiring 81 that is provided to alleviate the level difference between the region and the sense amplifier section and is not normally used for memory cell selection, and a level detection circuit 83 for detecting the level of the dummy wiring 81. 81 and the level detection circuit 83 constitute the delay circuit 70 shown in FIG. 9 or FIG. The level detection circuit 83 is characterized in that the logic threshold value is set by changing the ratio of transistor size or the like. A disconnecting word line 84 connected to the ground is provided to disconnect the bit line 8 and the dummy bit line 86.
[0125]
Next, the cross-sectional structure of the memory cell portion of the semiconductor memory device according to this embodiment will be described. As shown in FIG. 12, the semiconductor memory device according to the present embodiment has a memory cell selection word line 7 that becomes a gate electrode of a memory cell transistor of the memory cell 9, a separation word line 84, and a memory cell of a dummy cell 82. A dummy wiring 81 serving as a word line of the transistor is arranged in order. At this time, the dummy wiring 81 is provided at the end of the memory cell array, that is, at the boundary between the memory cell portion and the sense amplifier portion, and alleviates the step between the memory cell portion and the sense amplifier portion on the substrate. It is configured as follows.
[0126]
-Operation-
In this embodiment, the sense amplifier activation signal Ssa, which is an output signal of the dummy word line drive circuit 69 in the sense amplifier activation circuit 2X (or 2Y) shown in FIG. When input to the detection circuit 83, the following operation is performed. That is, the signal is transmitted to the level detection circuit 83 via the dummy wiring 81 having the same load 82 as the word line 7 used for memory selection, and the level detection circuit 83 outputs the sense amplifier activation signal Ssa. At this time, the RC characteristic that determines the delay time of the dummy wiring 81 has the same characteristic as that of the word line 7 for memory cell selection. Further, this level detection circuit 83 has a hysteresis characteristic, and the logic threshold value is (bit line precharge potential) + (threshold voltage Vtn of the memory cell transistor) + (back bias) when the dummy wiring 81 rises. At the time of falling, it is set to (the threshold voltage VtnLow of the memory cell transistor). However, VtnLow is a threshold voltage when the source-substrate voltage is small. As a result, the level detection circuit 83 outputs a sense amplifier activation signal Ssa whose rising and falling timings match the timing at which the gates of the memory cell transistors open and close, respectively.
[0127]
-Effect-
As described above, the semiconductor memory device according to the present embodiment includes the dummy wiring 81 having the same load as the memory cell selection word line 7 used for reading and writing data, and the level detection circuit 83 having hysteresis characteristics. Since the delay circuit 70 in the sense amplifier activation circuit 2 is configured, the output timing of the sense amplifier activation signal Ssa is determined based on the RC characteristics of the memory cell selection word line 7, the reading of the memory cell data, and the memory cell transistor. Therefore, it is possible to increase the speed of the amplification operation of the sense amplifier 5 by optimizing the operation timing of the sense amplifier 5 (particularly at a low voltage).
[0128]
Further, in the cross-sectional structure of the semiconductor memory device, there is generally a step between the memory cell portion and the sense amplifier portion. This is because a memory cell has members necessary for configuring a memory cell capacitor such as a storage node, a capacitor film, and a cell plate, whereas the sense amplifier unit has a member corresponding to such a memory cell capacitor. Because it does not exist. Here, in the memory cell of this embodiment, as shown in FIG. 12, since the dummy wiring 81 and the dummy bit line 86 are arranged at the end of the memory cell portion, the step can be relaxed as much as possible. . (Note: Isn't there an effect of providing the separation word line 84?)
(Seventh embodiment)
Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to the drawings.
[0129]
−Configuration−
FIG. 13 is a plan view showing a wiring structure constituting a delay circuit in the semiconductor memory device according to the present embodiment. The semiconductor memory device of this embodiment has a circuit configuration similar to a circuit having a dummy wiring 81, a dummy cell 82, a level detection circuit 83, and a separation word line 84 as shown in FIG.
[0130]
That is, as shown in FIG. 13, the semiconductor memory device according to the present embodiment uses a dummy wiring 91 made of the same material (for example, polysilicon) as the memory cell selection word line 7 and the dummy wiring 91 as gates. An NMOS transistor 92, a level detection circuit 93 that receives a signal from the dummy wiring 91 and detects the level thereof, and a wiring 94 that is made of the same material as the memory cell selection word line 7 and that is fixed at the ground potential VSS. And a sense amplifier starting circuit having a delay circuit consisting of 95. Reference numeral 95 is a wiring for supplying a potential to the source / drain of the NMOS transistor 92, and 96 is a contact hole connecting the wiring 95 and the source / drain of the NMOS transistor 92. The wiring 95 is made of the same material as the bit line (for example, aluminum alloy, polycide, etc.), and the contact hole 96 has the same opening area as the contact hole connecting the bit line and the source / drain of the memory cell transistor. It has a depth.
[0131]
The dummy wiring 91 has substantially the same thickness, width (gate length) and length as the memory selection word line 7, and the NMOS transistor 92 uses one common memory cell selection word line 7 as a gate. The memory cells 9 are meandering so as to have substantially the same channel region as the entire channel region of the NMOS transistors of the memory cells 9. In addition, the dummy wiring 91 has an interlayer insulating film sandwiched between the wiring 94 and the wiring 95, and is equivalent to the capacitance between adjacent wirings that the actual memory cell selection word line 7 receives from the unselected word line 7. It is formed so as to be adjacent to each other with a distance having a capacity. Similarly to the sixth embodiment described above, the logical threshold value of the level detection circuit 93 is (bit line precharge potential) + (threshold voltage Vtn of the memory cell transistor) + (back bias effect). Is set to
[0132]
-Operation-
In this embodiment, the sense amplifier activation signal Ssa, which is the output signal of the dummy word line drive circuit 69 in the sense amplifier activation circuit 2X (or 2Y) shown in FIG. When input to the detection circuit 93, the following operation is performed. That is, since the dummy wiring 91 is sandwiched between the wirings 94 and 95 whose potential is fixed to the ground potential VSS and has the same gate capacitance of the transistor as the memory cell selection word line 7, the memory cell The wiring load is almost the same as that of the selection word line 7. The sense amplifier activation signal Ssa is transmitted to the level detection circuit 93 via the dummy wiring 91. As a result, the time (delay time) required from input to output to the dummy wiring 91 has the same RC characteristic as that of the actual memory cell selection word line 7. Similarly to the sixth embodiment described above, the logical threshold value of the level detection circuit 93 is (bit line precharge potential) + (threshold voltage Vtn of the memory cell transistor) + (back bias effect). In addition to the characteristics of the memory cell selection word line 7, the sense amplifier activation signal Ssa is output in accordance with the data read timing from the memory cell. Further, the level detection circuit 93 is provided with hysteresis characteristics, and the logic threshold is set to (bit line precharge potential) + (memory cell transistor threshold voltage Vtn) + (back bias effect component) when the dummy wiring 91 rises. ), At the time of falling, the threshold voltage VtnLow level of the memory cell transistor is set to output the sense amplifier starting signal 73 in synchronization with both rising and falling. However, VtnLow is a threshold voltage when the source-substrate voltage is small.
[0133]
-Effect-
As described above, in the semiconductor memory device of this embodiment, the dummy capacitance having the gate capacitance of the memory cell selection word line 7 on which data is read / written and the wiring load equivalent to the capacitance between adjacent interconnections. A sense amplifier starting circuit having a delay circuit 91 is arranged. As a result, the output timing of the sense amplifier activation signal Ssa can be matched with the RC characteristics of the memory cell selection word line 7 and the read timing of the memory cell data, and the operation of the sense amplifier 5 (especially at a low voltage). The amplification operation of the sense amplifier 5 can be speeded up by optimizing the timing.
[0134]
(Eighth embodiment)
Next, a semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to the drawings.
[0135]
−Configuration−
FIG. 14 is a circuit diagram showing a configuration of a delay circuit in the sense amplifier starting circuit of the semiconductor memory device according to the present embodiment.
[0136]
As shown in the figure, the delay circuit in the sense amplifier activation circuit of the semiconductor memory device according to this embodiment is configured by inserting a resistor R1 into the drain of the PMOS transistor and a resistor R2 into the drain of the NMOS transistor. There is provided a delay element array 100 in which a plurality of sets of inverter elements 101 and gate capacitance load elements 102 configured by connecting gates of PMOS transistors and NMOS transistors whose source and drain are short-circuited are alternately connected in series. ing. However, the output signal of the dummy word line driving circuit 69 in the activation circuit 2 shown in FIGS. 9 and 10 is input from the wiring 104. Further, a level detection circuit 103 for detecting the output level of the delay element array 100 is provided. The delay element array 100 and the level detection circuit 103 correspond to the delay circuit 70 shown in FIG. 9 or FIG. A delay circuit is configured. Here, as the power supply voltage of the inverter element 101 and the gate capacitive load element 102 in the delay element array 100, the internal step-down potential VINT which is the power supply voltage having the same VDD dependency as the external power supply voltage VDD dependency of the word line boost potential VPP. Is used. Further, the logical threshold value of the level detection circuit 103 is set by changing the ratio of the transistor size and the like.
[0137]
-Operation-
An output signal of the dummy word line 91 in the sense amplifier starting circuit is transmitted from the wiring 104 to the level detection circuit 103 via the delay element 100. At that time, the resistance values of the resistance elements R1 and R2 inserted in the drains of the PMOS transistor and the NMOS transistor are sufficiently larger than the resistances of the PMOS transistor and the NMOS transistor, and can take a constant value. Since the time T (= RC) is kept constant, the dependency of the charge / discharge capacity on the power supply voltage is small. In other words, with regard to the electrical resistance of the portion formed by connecting a transistor that also functions as a resistor and a resistance element in series, if the resistance value of the resistance element is made much larger than the resistance value of the transistor, the resistance value of the transistor The power supply voltage dependence of the power supply does not contribute much to the overall resistance value. Since the resistance elements R1 and R2 are made of polysilicon and the temperature dependence of the resistance value is small, the resistance including the transistor of the inverter element 101 is also less temperature dependent. As a result, the change in delay time caused by the power supply voltage dependency and temperature dependency of the capability of the PMOS transistor and NMOS transistor can be suppressed, and the characteristics of the inverter element 101 can be reduced in the power supply voltage dependency and temperature dependency. The RC delay characteristic of the selection word line 72 is adapted. In order to change the delay time of the delay element row 100 between the rise and fall of the potential of the memory cell selection word line 72, the odd-numbered inverter elements 101 and the even-numbered inverter elements 101 having opposite logics to each other are used. The ratio of the resistance values of the resistance element R1 and the resistance element R2 may be changed in accordance with the ratio of the rise / fall time of the memory cell selection word line 72.
[0138]
Further, the level detection circuit 103 has a change in logic threshold value and hysteresis characteristics as in the sixth and seventh embodiments.
[0139]
-Effect-
As described above, in the semiconductor memory device according to the present embodiment, the output line of the sense amplifier activation signal Ssa is used for data read / write as in the sixth and seventh embodiments. The RC characteristic and the read timing of the memory cell data can be matched, and the amplification operation of the sense amplifier 5 can be speeded up by optimizing the operation timing of the sense amplifier 5 (particularly at a low voltage). it can.
[0140]
(Ninth embodiment)
Next, a semiconductor memory device according to a ninth embodiment of the invention is described with reference to the drawings.
[0141]
−Configuration−
FIG. 15 is a circuit diagram showing a schematic configuration of a delay circuit (corresponding to the delay circuit 70 in FIGS. 9 and 10) in the sense amplifier starting circuit of the semiconductor memory device according to the present embodiment. As shown in the figure, the delay circuit according to this embodiment includes delay element rows 113 and 114 in which a large number of inverter elements are arranged, and the delay element row 113 for each of the rising edge and the falling edge of the input signal. , 114, and a level shifter 116 for changing the output level from the internal step-down potential VINT to the external power supply potential VDD. However, the output signal of the dummy word line driving circuit 69 in the activation circuit 2 shown in FIGS. 9 and 10 is input from the wiring 104. The delay element rows 113 and 114 include an inverter element 111 including a PMOS transistor and an NMOS transistor having a resistor element R3 inserted in the drain, and a PMOS transistor and an NMOS transistor having a resistor element R4 inserted in the drain. Inverter elements 112 constituted by are arranged alternately and in series.
[0142]
-Operation-
As described in the sixth embodiment, the output signal of the dummy word line driving circuit 69 in the sense amplifier starting circuit 2 is set to the Hi level and the Low level in accordance with the rise and fall of the memory cell selection word line 7, respectively. Transition. At this time, the timing delay characteristics, including power supply voltage dependency, differ between the rise and fall of the word line.
[0143]
When the sense amplifier is activated, the output signal of the dummy word line driving circuit 69 needs to match the transition timing to the Hi level with the rising edge of the word line 7, so that the delay element array 114 is not operated as a delay circuit. Only the column 113 is operated as a delay circuit.
[0144]
The delay element array 113 outputs a connection portion between the first stage PMOS transistor and the resistance element R3, and outputs a connection portion between the opposite NMOS transistor and the resistance element R4 in the next stage. Here, in the delay element array 113, it is only necessary that the resistor element R3 is inserted in the drain of the NMOS transistor that is turned on among the first-stage inverter elements 111 to which the Hi level signal is input at the time of rising, and the OFF state. Since no current flows through the drain of the PMOS transistor, there is no need to insert a resistance element. Similarly, in the second-stage inverter element 112 to which a low level signal is input at the time of rising, the resistor element R4 may be inserted only into the drain of the PMOS transistor that is turned on. With such a configuration, charge is charged and discharged via the resistance elements R3 and R4 of the delay element array 113 to delay the signal.
[0145]
In addition, when the sense amplifier is stopped, the output signal of the dummy word line driving circuit 69 input from the wiring 104 needs to match the transition timing to the Low level with the falling of the word line 7, so that the delay element array 113 is Only the delay element array 114 is operated as a delay circuit without operating as a delay circuit.
[0146]
Similarly to the delay element array 113, the delay element array 114 has a resistance element R3 inserted only in the drain of the NMOS transistor in the first stage inverter element 111, and a resistance only in the drain of the PMOS transistor in the inverter element 112 in the next stage. An element R4 is inserted. Similar to the delay element array 113 already described, at the fall time, the NMOS transistor of the first-stage inverter element 111 to which a Hi-level signal is input and the second-stage PMOS transistor to which a Low-level signal is input. This is because a resistor element may be inserted. That is, charges are charged and discharged through the resistance elements R3 and R4 of the delay element array 114 to delay the signal.
[0147]
Here, since the delay element array 114 at the time of starting the sense amplifier and the delay element array 113 at the time of stop transfer the input signal without going through the resistance elements R3 and R4, the time until reset is short, and the next cycle There is no effect on the operation.
[0148]
-Effect-
As described above, in the semiconductor memory device according to the present embodiment, in the inverter element configuring the delay element array, the resistance element is inserted only into the drain of the transistor that is turned on at the time of signal transition among the PMOS transistor and the NMOS transistor. A delay circuit having delay element rows 113 and 114 formed by combining inverter elements whose output nodes are alternately switched between the drain of the NMOS transistor and the drain of the PMOS transistor is formed, and the rise and fall of the word line is prevented. The configuration is such that the sense amplifier start / stop timing is individually set. As a result, as in the sixth to eighth embodiments, the output timing of the sense amplifier activation signal Ssa can be matched with the RC characteristics of the memory cell selection word line 7 used for data read / write. The speed of the sense amplifier amplification operation can be increased by optimizing the operation timing of the sense amplifier (particularly at a low voltage). In addition, the number of resistance elements required to obtain the same delay time can be reduced, and the rise and fall individual timings of the memory cell selection word line 7 can be easily set.
[0149]
【The invention's effect】
According to the first semiconductor memory device of the present invention, the sense amplifier drive circuit group in which the power supply voltage control circuits for switching the outputs of the plurality of sense amplifier drive circuits that supply the sense amplifier drive signal to a plurality of types are arranged along the bit lines. By arranging each, it is possible to prevent a situation in which the charge supply to the sense amplifier becomes insufficient.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a sense amplifier in the first and second embodiments of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a sense amplifier control circuit according to a second embodiment of the present invention.
FIG. 4 is a timing chart illustrating an operation sequence of a sense amplifier control circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a sense amplifier control circuit according to a third embodiment of the present invention.
FIG. 7 is a timing chart illustrating an operation sequence of a sense amplifier control circuit according to a third embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a configuration of a semiconductor memory device according to a fifth embodiment of the present invention.
FIG. 10 is a circuit diagram showing a configuration of a modification of the semiconductor memory device according to the fifth embodiment of the present invention.
FIG. 11 is a circuit diagram showing a part of a dummy cell and a memory cell array constituting a delay circuit in a sixth embodiment of the present invention.
FIG. 12 is a cross-sectional view of a memory cell portion of a semiconductor memory device in a sixth embodiment of the present invention.
FIG. 13 is a plan view showing a wiring structure constituting a delay circuit arranged in a sense amplifier starting circuit in a seventh embodiment of the present invention.
FIG. 14 is a circuit diagram showing a configuration of a delay circuit arranged in a sense amplifier starting circuit in an eighth embodiment of the present invention.
FIG. 15 is a circuit diagram showing a configuration of a delay circuit arranged in a sense amplifier starting circuit in a ninth embodiment of the present invention.
FIG. 16 is a circuit diagram showing a configuration of a conventional semiconductor memory device provided with means for switching the power supply potential of the sense amplifier.
FIG. 17 is a timing chart showing an operation sequence of a conventional sense amplifier control circuit that performs an operation of turning on and off a shade switch during a read operation, and another conventional sense that controls the gate potential of the shade switch to a low potential during a read operation; FIG. 6 is a timing chart illustrating an operation sequence of an amplifier control circuit.
FIG. 18 is a circuit diagram showing a configuration of a conventional sense amplifier starting signal generating delay circuit using invar and chain.
[Explanation of symbols]
1 Power supply voltage switching circuit
2 Sense amplifier starting circuit
3 Sense amplifier control circuit
4 Sense amplifier drive circuit
5 sense amplifiers
6 sense amplifiers
7 Word line
8-bit line
9 Memory cells
10 sense amplifier block
11 Bank selection signal
12 Drive power supply wiring
13 Power connection line
14-18 wiring
17 Sense amplifier power supply potential wiring
19 Memory cell block
Sas address selection signal
Sbs Bank selection signal
Ssa Sense amplifier start signal
Sct Shared switch control signal

Claims (8)

A memory cell array in which memory cells for storing information are arranged in a matrix;
A word line extending along a row of the memory cell array and connected to each memory cell arranged along the row;
A bit line extending along a column of the memory cell array and connected to each memory cell arranged along the column;
A plurality of sense amplifier rows that are arranged in parallel to the word lines of the memory cell array and are connected to the bit lines to amplify information stored in the memory cells;
A plurality of sense amplifier drive circuits that are provided for each sense amplifier row and supply a sense amplifier drive signal to each sense amplifier;
A power supply voltage control circuit that receives a plurality of power supply voltages, switches an output to any one of the plurality of power supply voltages, and supplies the output as a power supply voltage to the sense amplifier drive circuit;
The power supply voltage control circuit is arranged for each sense amplifier drive circuit group (4A, 4B, 4C) arranged along the bit line, and supplies sense amplifier drive power to the plurality of sense amplifier drive circuits. A semiconductor memory device, characterized in that a supply wiring extends along the bit line . The semiconductor memory device according to claim 1.
One of the plurality of power supply potentials is an internal step-down potential,
The semiconductor memory device, wherein the power supply voltage control circuit is configured to supply only the internal step-down potential to the sense amplifier drive circuit in the low power consumption mode. The semiconductor memory device according to claim 1 or 2,
One of the plurality of power supply potentials is an internal step-down potential,
A switching transistor interposed between the bit line and the sense amplifier and switching between a conductive state and a non-conductive state;
And a sense amplifier control circuit for holding the gate potential of the switching transistor at the internal step-down potential for a predetermined time when the switching transistor is in a conductive state. The semiconductor memory device according to any one of claims 1 to 3,
The semiconductor memory device, wherein the power supply voltage control circuit is disposed on both sides of the memory cell array. The semiconductor memory device according to claim 1.
A switching transistor interposed between the bit line and the sense amplifier and switching between a conductive state and a non-conductive state;
A control circuit for controlling the gate potential of the switching transistor,
The switching transistor is non-conductive during standby,
The control circuit raises the gate potential in the conductive state of the switching transistor to the second power supply potential higher than the first power supply potential when a predetermined time has elapsed after setting the first power supply potential to the gate potential. A semiconductor memory device. The semiconductor memory device according to claim 5.
The first power supply potential is an internal step-down potential or an external power supply potential,
The semiconductor memory device, wherein the second power supply potential is a boosted potential. The semiconductor memory device according to claim 6.
The first power supply potential is an internal step-down potential,
The semiconductor memory device, wherein the second power supply potential is an external power supply potential or a boosted potential. The semiconductor memory device according to claim 5.
The semiconductor memory device, wherein the control circuit switches any one of a ground potential, an external power supply potential, and a boosted potential and supplies the switching potential as a gate potential of the switching transistor.

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