JP3678620B2 - Data consistency maintenance control method in multiprocessor system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data consistency maintenance control method in a multiprocessor system in which each processor includes a cache.
[0002]
[Prior art]
In a multiprocessor system, data having the same address may exist on a plurality of caches in the system. Therefore, it is necessary to perform control for maintaining data consistency between caches holding data at the same address and data consistency maintenance control.
[0003]
This data consistency maintenance control is a control for guaranteeing that when a processor writes to a certain block, it can be performed exclusively, and the latest value is obtained at the time of reading. . Therefore, first, it must be possible to identify in which cache the block to be written exists. Then, it is necessary to be able to specify where the latest block exists in the case of a reading mistake. Here, the block is a minimum unit of data management, and the size is, for example, 64 bytes.
[0004]
For example, in the literature (“A New Solution to CoherencyProblems in Multisystem Systems” LUCIEN M. CENSIER and PAUL FEAUTRIER, IEEE Transactions on Computers, 78113D, e. First, the first feature is to hold information on whether or not the block is shared in units of blocks in the cache. The second feature is that information for specifying a cache holding the block in the memory unit and information indicating whether or not the latest block exists in the memory are held. The third feature is that when writing to a block shared by a processor, the block of another cache is invalidated to cancel the shared state, and the latest block exists only in the cache. There is to do.
[0005]
Hereinafter, the operation of this method will be described.
[0006]
Referring to FIG. 1, a multiprocessor system according to the related art and the present invention includes a processor PRi that executes an instruction and accesses a memory, a cache CMi that is connected to each processor PRi and temporarily holds data accessed by the processor PRi, and data Memory MMi, a cache CMi, and an interconnection network 12 connecting the memories MMi. In the system shown in FIG. 1, the interconnection network 12 has eight ports. The port 0 has a cache CM1, the port 1 has a cache CM2, the port 2 has a cache CM3, and the port 3 has a port 3. The cache CM4 is connected to the port 4, the memory MM1 is connected to the port 5, the memory MM2 is connected to the port 5, the memory MM3 is connected to the port 6, and the memory MM4 is connected to the port 7.
[0007]
Hereinafter, taking a case where the processor PR1 accesses data in the memory MM2 as an example, a series of operations for maintaining data consistency performed by the access will be described.
[0008]
An operation when the processor PR1 accesses data of a certain block but the block does not exist in the cache CM1 (hereinafter, this case is referred to as a cache miss) will be described. In this case, a read request message is first issued from the cache CM1 to the memory MM2. The memory MM2 that has received the read request checks whether or not the latest block exists in the memory, and if it exists, transmits the block to the cache CM1. If it does not exist, there is only one cache that holds the latest block, so a write-back request message is issued to that cache, for example, the cache CM 3. The cache CM 3 that has received the write-back request writes the block back to the memory MM2. The memory MM2 transmits the block written back from the cache CM3 to the cache CM1. The cache CM1 that received the block again evaluates the memory access performed by the processor PR1 and performs processing necessary for maintaining data consistency.
[0009]
As a result of the above processing, in addition to the cache that previously held the block, the cache CM1 also newly holds the latest block. Also, the latest block exists in the memory MM2.
[0010]
Next, the operation when the processor PR1 reads data of a certain block and the block exists in the cache CM1 (hereinafter this case is referred to as a read hit) will be described. In this case, the cache CM1 passes the block data to the processor PR1 to complete the process.
[0011]
Next, the operation when the processor PR1 writes data to a certain block and the block exists in the cache CM1 and is not in a shared state (hereinafter this case is referred to as a write hit) will be described. In this case, the processing is completed by reflecting the writing performed by the processor PR1 to the cache CM1 in the block held by the cache CM1 and notifying the processor PR1 that the writing has been completed.
[0012]
Next, the operation when the processor PR1 writes data to a certain block and the block exists in the cache CM1 and is in a shared state (hereinafter this case is referred to as write shared) will be described. In this case, the write performed by the processor PR1 is reflected in the cache CM1, and a write request message is issued to the memory MM2. The memory MM2 that has received the write request issues an invalidation request message to the cache CM3 and the cache CM4 if, for example, the cache CM3 and the cache CM4 other than the cache CM1 hold a block. Receiving the invalidation request, the cache CM3 and the cache CM4 invalidate the block and transmit an invalidation completion message to the memory MM2. When the memory MM2 receives the invalidation completion message from both the cache CM3 and the cache CM4, the memory MM2 transmits a completion response message to the cache CM1. When the cache CM1 receives the completion response message, the cache CM1 notifies the processor PR1 that the writing has been completed and completes the processing. As a result of the above processing, only the cache in which writing has been performed holds the latest block, and the memory does not have the latest block.
[0013]
As a result of the above processing, the latest block exists only in the cache CM1, and the latest block does not exist in the other cache CMi and the memory MM2.
[0014]
In the above description of the operation for maintaining data consistency, for example, the memory MM2 receives a read request from the cache CM1, issues a writeback request to the cache CM3, and waits for a block to be written back. In this state, the operation when there is a read request from the cache CM 2 is omitted.
[0015]
[Problems to be solved by the invention]
The first problem is that it takes a long time for data to be returned from the cache to the processor when a cache miss occurs due to reading by the processor.
[0016]
For example, consider an operation when the processor PR1 performs writing and then the processor PR4 performs reading in a state where the blocks of the memory MM2 exist and are shared in the cache CM1 and the cache CM3. When the processor PR1 performs writing, the latest block exists only in the cache CM1, and the latest data does not exist in the memory MM2. Next, when the processor PR4 performs reading, a cache miss occurs because no block exists in the cache CM4. As a result, a read request message is transmitted to the memory MM2, but since there is no latest data in the memory MM2, a write-back is requested to the cache CM1 holding the latest data. The memory MM2 receives the block write-back from the cache CM1, and then transmits the block to the cache CM4. The cache CM 4 that has received the block again evaluates the read performed by the processor PR 4, and since the block exists, passes the data to the processor PR 4 and completes the processing.
[0017]
As described above, the reason for the above problem is that the latest block does not exist in the memory after the processor performs writing.
[0018]
The second problem is that many messages are exchanged between the cache and the memory for data consistency maintenance control.
[0019]
The reason is that after the processor writes, the latest block no longer exists in the memory. That is, when a cache miss occurs in another cache after a certain processor writes, a write-back request to the cache holding the latest data in addition to a read request message to the memory and block transfer to the cache This is because it is necessary to write back the message and the block from its cache.
[0020]
An object of the present invention is to provide a data consistency maintenance control method in which the time required for data consistency maintenance control when a cache miss due to reading occurs is shortened.
[0021]
Another object of the present invention is to provide a data consistency control method that prevents an increase in the number of messages generated by data consistency maintenance control.
[0022]
[Means for Solving the Problems]
In the first data consistency maintenance control method of the present invention, when a write is performed on a block shared by a processor, the write is reflected on the cache and memory blocks, and the other cache blocks are related. Has a means (23 in FIG. 2 and 44 in FIG. 3) for performing data consistency maintenance control in the cache and the memory, which invalidates and keeps the state of the block of the cache where writing has been performed.
[0023]
According to the second data consistency maintenance control method of the present invention, when writing to a block shared by a processor, the latest block exists only in the cache and the memory, and other caches If the latest block is not held, the data is reflected to the cache and memory blocks, but the state of the cache block where the data was written is changed from the shared state to the non-shared state. Means (23 in FIG. 2 and 44 in FIG. 3) for controlling in the cache and memory.
[0024]
The third data consistency maintenance control method of the present invention provides a counter for each block in the memory, initializes the counter value to 0 when a block is newly fetched into the cache, and blocks shared by the processor When a write is performed to the block, the counter value of the block is incremented. When a write is performed to a block shared by the processor, the latest block exists only in the cache and memory. If the other cache does not hold the latest block and the counter value is a certain value, the write is reflected to the cache and the memory block. Cache data consistency maintenance control that changes the block state from shared state to non-shared state. And means for performing the memory (44 of 23 and 3 in Figure 2).
[0025]
The data consistency maintenance control means in the first data consistency maintenance control method of the present invention, when writing to the block shared by the processor, updates the cache and memory in which the writing is performed to the latest Assume that a block exists.
[0026]
In the second data consistency maintenance control method of the present invention, the data consistency maintenance control means continuously writes to a block that is actually shared by a plurality of caches while the other cache accesses When the first write is not performed, the first two writes are reflected in the memory, but the block sharing state is canceled after the second write, and the third write and subsequent steps are performed only for the cache.
[0027]
The data consistency maintenance control means in the third data consistency maintenance control method of the present invention is such that the processor continuously writes to a block that is actually shared by a plurality of caches, while other caches When access is not performed, a certain number of writes are reflected in the memory, but subsequent writes are performed only on the cache.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0029]
Referring to FIG. 1 again, the multiprocessor system according to the present invention includes a processor PRi that executes an instruction and performs memory access, a cache CMi that is connected to each processor PRi and temporarily holds data accessed by the processor PRi, data Memory MMi, a cache CMi, and an interconnection network 12 connecting the memories MMi. In the system shown in FIG. 1, the interconnection network 12 has eight ports. The port 0 has a cache CM1, the port 1 has a cache CM2, the port 2 has a cache CM3, and the port 3 has a port 3. The cache CM4 is connected to the port 4, the memory MM1 is connected to the port 5, the memory MM2 is connected to the port 5, the memory MM3 is connected to the port 6, and the memory MM4 is connected to the port 7.
[0030]
Here, each cache CMi and memory MMi is assigned a 3-bit device number corresponding to the port number connected to the interconnection network 12, the cache CM1 is “000”, the cache CM2 is “001”, The cache CM3 is “010”, the cache CM4 is “011”, the memory MM1 is “100”, the memory MM2 is “101”, the memory MM3 is “110”, and the memory MM4 is “111”. Each memory MMi manages an area in which the upper 2 bits of the address match the lower 2 bits of its own device number. For example, the memory MM2 manages an area in which the upper 2 bits of the address are “01”.
[0031]
Next, referring to FIG. 2, the cache CMi according to the present invention includes a tag memory 22 that holds information about blocks such as tag states, a cache memory 25 that holds data in units of blocks, and a memory access from the processor PRi. A memory access management unit 21 that holds and manages the message, a first message reception unit 26 that receives a message delivered by the interconnection network 12, and a first message transmission unit 27 that transmits a message to the interconnection network 12. The first data control unit 24 for accessing the cache memory 25, the memory access held by the memory access management unit 21 and the message held by the first message receiving unit 26 for data consistency maintenance control Reading of information stored in the tag memory 22 for processing A first function having a function of instructing the first data control unit 24 to access the cache memory 25 and a function of instructing the first message transmission unit 27 to transmit a message. The consistency maintenance control unit 23 is configured.
[0032]
Next, referring to FIG. 3, the memory MMi according to the present invention is delivered by the directory memory 43 that holds information about blocks such as the directory state and the directory map, the main memory 46 that holds data, and the interconnection network 12. A second message receiving unit 41 that receives the received message, a second message transmitting unit 42 that transmits a message to the interconnection network 12, a first data control unit 24 that accesses the main memory 46, a second In order to perform processing for data consistency maintenance control on the message held in the message receiving unit 41, a function for reading and writing information stored in the directory memory 43, and a second data as a control function A function of instructing the control unit 45 to access the main memory 46; And a second coherence maintaining control unit 44 and a function of instructing the transmission of a message to the second message transmitting unit 42.
[0033]
Next, in the data consistency maintenance control method according to the first embodiment, the tag state held in the tag memory 22 represents the state of the block stored in the cache memory 25, and I, S, E , D, each having the following meaning. The I state represents that the latest block does not exist in the cache memory 25. The S state indicates the possibility that the latest block exists in the cache memory 25 and also exists in another cache memory 25, that is, the block may be shared. The E state represents that the latest block exists in the cache memory 25 and the latest block exists in the main memory 46 but does not exist in the other cache memory 25. The D state indicates that the latest block exists in the cache memory 25, and the latest block does not exist in the other cache memory 25 or the main memory 46. In addition, the initial value of the tag state in the cache memory 25 is I, and there is no latest block in the cache memory 25.
[0034]
In the data consistency maintenance control method according to the first embodiment, the directory map held in the directory memory 43 represents the cache CMi that holds the corresponding block in the main memory 46. “A New Solution to Coherency Programs in Multisystem Systems” LUCIEN M. CENSIER and PAUL FEAUTRIER, IEEE Transactions on Computers, p1112-11118, Full map, which is disclosed in 19 In the full map method, a bit corresponding to each cache CMi is provided and indicates whether or not the cache CMi holds a block according to the bit. In the system of FIG. Composed. FIG. 4 shows the relationship between the value of the directory map and which cache CMi holds the block. In FIG. 4, ◯ indicates that it is held, and × indicates that it is not held. As is apparent from the figure, when the 0th bit of the directory map is 1, it indicates that the cache CM1 holds the block. When the 1st bit is 1, the cache CM2 is present. When the 2nd bit is 1, the cache CM3 is present. However, when the third bit is 1, it indicates that the cache CM 4 holds a block. In the directory memory 43, the initial value of the directory map is “0000”, and no cache CMi holds a block.
[0035]
In the data consistency maintenance control method according to the first embodiment, the directory state stored in the directory memory 43 represents the state of the corresponding block stored in the main memory 46, and C, M, It consists of four states, RMP and WSP, and has the following meanings. The C state indicates that there is a latest block in the main memory 46, and the cache CMi indicated by the directory map may hold data. In this state, the directory map can take all 16 values shown in FIG. The M state indicates the possibility that the latest block does not exist in the main memory 46, and suggests the possibility that only one cache CMi indicated in the directory map holds the latest block. In this state, the directory map can take only four types of values “0001”, “0010”, “0100”, and “1000”. The RMP state receives an RM message described later in the M state, issues an FR message to only one cache CMi indicated by the directory map, and waits for an FD or ACK message from the cache CMi to arrive. Represents that In this state, the directory map can take only four types of values “0001”, “0010”, “0100”, and “1000”. In the WSP state, a WS message (to be described later) is received in the C state, and IV messages are sent to all the cache CMi that may hold the data indicated by the directory map, except for the cache CMi that issued the WS message. It is issued and indicates that ACK messages from all the cache CMi are waiting to arrive. In this state, the directory map can take only three types of values “0011”, “0010”, or “0001”. This value does not represent the cache CMi to be held, “0011” represents waiting for the arrival of three ACKs, and “0010” represents waiting for the arrival of two ACKs. , '0001' represents waiting for arrival of one ACK. Further, the initial value of the directory state in the directory memory 43 is C, and the latest block exists in the main memory 46.
[0036]
In the data consistency maintenance control method according to the first embodiment, messages exchanged between the cache CMi and the memory MMi include RM, WS, WB, FR, IV, FD, ACK, SDR, EDR, There are 11 types of messages, CR and NCR, each having the following meaning.
[0037]
The RM message is a read request message issued from the cache CMi to the memory MMi when a cache miss occurs. The WS message is a write request message issued from the cache CMi to the memory MMi when write sharing occurs. Data written by the processor is added to the WS message. The WB message is a write-back message that is issued when writing back a block to be replaced. A block to be replaced is added to this WB message. The FR message is a write-back request message issued by the memory MMi that has received the RM message to the cache CMi that holds the latest block. The IV message is an invalidation request message issued from the memory MMi that has received the WS message to the cache CMi that holds the block. The FD message is a write-back message issued to the memory MMi by the cache CMi that has received the FR message. The latest block held by the cache CMi is added to the FD message. The ACK message is a response message issued to the memory MMi by the cache CMi that has received the FR or IV message. The SDR and EDR messages are response messages that notify the memory MMi that the processing for maintaining data consistency for the RM message has been completed in the memory MMi to the cache CMi that issued the RM message. The latest block is added to the SDR and EDR messages. The CR message is a response message in which the memory MMi notifies the cache CMi that issued the WS message that processing for the WS message has been completed in the memory MMi. The NCR message is a message notifying the cache CMi that has issued the RM or WS message when the RM or WS message cannot be processed in the memory MMi.
[0038]
A message is composed of a header part and a data part, and six types of messages such as RM, FR, IV, ACK, CR, and NCR are composed only of the header part. The WS message is composed of a header part and a data part composed of data written by the processor. The four types of messages WB, FD, SDR, and EDR are composed of a header part and a data part composed of block unit data.
[0039]
The configuration of the message header portion will be described with reference to FIG.
[0040]
The message header is composed of five fields: a destination device number, a message identifier, an address, and a request source device number. The destination device number field indicates which port of the interconnection network 12 is connected to the cache CMi or the memory MMi. For example, in the case of “101”, the destination device number field is addressed to the memory MM2 connected to the port 5. The message is delivered to The message identifier field indicates which of the 11 types of messages the message is. Eleven types of messages are identified. The address field indicates to which address each message is a message. The request source device number field indicates the processor number of the cache CMi connected to the processor PRi, indicating which processor PRi each message originated from. For example, if the message originates from a memory access performed by the processor PR1, the request source device number of the message is “000”.
[0041]
Next, in the data consistency maintenance control method according to the first embodiment, a case where the processor PR1 accesses data in the memory MM2 is taken as an example, and a series of operations for data consistency maintenance control performed by the access is performed. This will be described with reference to the drawings.
[0042]
First, when the processor PR1 issues a memory access, the memory access management unit 21 takes in the memory access therein. A memory access command for identifying read access or write access, an address indicating an access target, and data in the case of write access are captured. The command and address are supplied to the first consistency maintenance control unit 23, and the data is supplied to the first data control unit 24.
[0043]
The first consistency maintenance control unit 23 detects that the memory access has been taken into the memory access management unit 21, and determines the tag state of the corresponding block from the memory address stored in the memory access management unit 21. The data is read from the data 22 and the processing to be performed is determined according to the value.
[0044]
First, the operation when the tag state is “I”, that is, when there is a cache miss will be described.
[0045]
In this case, if there is no free space in the cache memory 25 for fetching a block at an address that has been accessed, it is necessary to replace it with another block that already exists in the cache memory 25. If there is no need for replacement, the first consistency maintenance control unit 23 starts from a process of transmitting an RM message to the memory MMi identified from the address (here, the memory MM2).
[0046]
When replacement is necessary and the tag state of the block to be replaced is “D”, this block is the only latest block in the system, so write back to the memory MMi that manages the block. It is necessary to perform the process first. 6 and 7 show a sequence flow in this case. The figure shows a case where the block to be replaced is a block managed by the memory MM3.
[0047]
The first consistency maintenance control unit 23 first generates a header part of the WB message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is “110” representing the memory MM3, the message identifier is the identifier representing WB, the address is the address of the block to be replaced, and the request source device number is the cache It becomes “000” indicating the device number of CM1. Further, the first consistency maintenance control unit 23 instructs the first data control unit 24 to read the replacement target block from the cache memory 25, and the read block is the first message transmission unit. 27 is supplied as the data part of the WB message. The first message transmission unit 27 sends the message to the interconnection network 12 by combining the header unit supplied from the first consistency maintenance control unit 23 and the data unit supplied from the first data control unit 24. In addition, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the block to be replaced to “I”.
[0048]
The transmitted WB message is delivered by the interconnection network 12, and is taken into the second message receiving unit 41 of the memory MM3. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the second data control unit 45.
[0049]
The second consistency maintenance control unit 44 of the memory MM3 detects that the WB message has been taken into the second message receiving unit 41, and determines the corresponding block from the address of the header part stored in the second message receiving unit 41. The directory state and the directory map are read from the directory memory 43, and what kind of processing is to be performed is determined according to the values. At this time, possible values of the directory state are limited to 'M' or 'RMP' in terms of the method.
[0050]
When the directory state is M, the sequence shown in FIG. The second consistency maintenance control unit 44 writes in the directory memory 43 and updates the directory state to C and the directory map to “0000” indicating that no cache CMi holds a block. In addition, the second consistency maintenance control unit 44 causes the second data control unit 45 to write the block added to the WB message to the corresponding block in the main memory 46.
[0051]
When the directory state is RMP, the sequence shown in FIG. The second consistency maintenance control unit 44 only causes the second data control unit 45 to write the block added to the WB message to the corresponding block of the main memory 46, and does not update the directory memory 43.
[0052]
The above is the sequence when replacement is necessary and the tag state of the block to be replaced is “D”.
[0053]
Next, when replacement is necessary and the tag state of the block to be replaced is other than 'D', the first consistency maintenance control unit 23 writes the tag memory 22 and sets it as the target of rewriting. The tag state of the new block is updated to “I”.
[0054]
When the replacement process is completed in the first consistency maintenance control unit 23, the first consistency maintenance control unit 23 generates a header part of the RM message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is “101” representing the memory MM2, the message length is stored in the RM message length, the message identifier is stored in the identifier indicating RM, and the address is stored in the memory access management unit 21. The request source device number is “000” indicating the device number of the cache CM1. The first message transmission unit 27 sends the header portion supplied from the first consistency maintenance control unit 23 as a message to the interconnection network 12 (common to FIGS. 8, 9, 10, 11, and 12). sequence).
[0055]
The sent RM message is delivered by the interconnection network 12, and is taken into the second message receiving unit 41 of the memory MM2. The header part of the captured message is supplied to the second consistency maintenance control unit 44.
[0056]
The second consistency maintenance control unit 44 of the memory MM2 detects that the RM message has been taken into the second message receiving unit 41, and determines the corresponding block from the address of the header part stored in the second message receiving unit 41. The directory state and the directory map are read from the directory memory 43, and what kind of processing is to be performed is determined according to the values.
[0057]
A cache CMi that holds a block other than the cache CMi that has the directory state C and the value of the directory map has been issued from the RM message (identified from the request source device number added to the message, and in this case, the cache CMi). (In this case, the directory map is “0000” or “0001”), the sequence shown in FIG.
[0058]
The second consistency maintenance control unit 44 first generates a header part of the EDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier is an identifier representing EDR. The address and the request source apparatus number are the address and request source apparatus number (here, “000”) of the message header stored in the second message receiving unit 41. Further, the second consistency maintenance control unit 44 reads the block specified by the address of the message header part stored in the second message reception unit 41 from the main memory 46 to the second data control unit 45. Instruct. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data part of the EDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and changes the directory state to M and the directory map to “0001”. The value of this directory map is a value obtained as a result of an operation of setting the bit corresponding to the cache CM1 that issued the RM message to “1” and setting the other bits to “0”.
[0059]
The sent EDR message is delivered by the interconnection network 12, and is taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the first data control unit 24.
[0060]
The first consistency maintenance control unit 23 of the cache CM 1 detects that the EDR message has been taken into the first message reception unit 26 and is added to the EDR message to the cache memory 25 with respect to the first data control unit 24. Instructed to fetch the block data that had been stored. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the corresponding block to “E”.
[0061]
Thereafter, the first consistency maintenance control unit 23 evaluates the memory access stored in the memory access management unit 21 again, and performs processing necessary for maintaining data consistency.
[0062]
Next, as a result of the second consistency maintenance control unit 44 of the memory MM2 receiving the RM message reading the directory state and directory map of the corresponding block of the directory memory 43, the directory state is C and the value of the directory map Indicates that there is a cache CMi that holds a block other than the cache CMi that issued the RM message (here, the cache CM1) (here, since the cache CM1 has issued the RM message, the directory map is 9 is a sequence other than “0000” or “0001”.
[0063]
The second consistency maintenance control unit 44 first generates a header part of the SDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents SDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). Further, the second consistency maintenance control unit 44 reads the block specified by the address of the message header part stored in the second message reception unit 41 from the main memory 46 to the second data control unit 45. Instruct. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data part of the SDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. Further, the second consistency maintenance control unit 44 writes the directory memory 43, and changes the directory state to C and the value of the directory map to “1101”. The value of this directory map is a bit corresponding to the cache CM1 specified from the request source device number stored in the second message receiving unit 41 with respect to the value of the directory map immediately before receiving the RM message. This is the value obtained as a result of performing the operation.
[0064]
The sent SDR message is delivered by the interconnection network 12, and is taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the first data control unit 24.
[0065]
The first consistency maintenance control unit 23 of the cache CM 1 detects that the SDR message has been taken into the first message reception unit 26 and is added to the SDR message to the cache memory 25 with respect to the first data control unit 24. Instructed to fetch the block data that had been stored. Further, the first consistency maintenance control unit 23 writes in the tag memory 22 and updates the tag state of the corresponding block to “S”.
[0066]
Thereafter, the first consistency maintenance control unit 23 evaluates the memory access stored in the memory access management unit 21 again, and performs processing necessary for maintaining data consistency.
[0067]
Next, when the second consistency maintenance control unit 44 of the memory MM2 that has received the RM message reads the directory state and directory map of the corresponding block of the directory memory 43, the directory state is M. FIG. Or it becomes a sequence shown in FIG. In this case, the directory map uniquely determines the cache CMi that holds the latest block. In the example shown in FIGS. 10 and 11, since the value of the directory map is “0100”, it can be confirmed that the cache CM 3 holds only the latest data.
[0068]
The second consistency maintenance control unit 44 first generates a header part of the FR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is “010” representing the cache CM 3 holding the latest block, the message identifier is an identifier representing FR, the address and the request source device number are the second message receiving unit 41. Are the address of the message header part stored in and the request source device number (here, “000”). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 as a message to the interconnection network 12. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and updates the directory state to RMP, but leaves the directory map as it is.
[0069]
The sent FR message is delivered by the interconnection network 12 and taken into the first message receiving unit 26 of the cache CM 3. The header part of the captured message is supplied to the second consistency maintenance control unit 44.
[0070]
The first consistency maintenance control unit 23 of the cache CM 3 detects that the FR message has been taken into the first message receiving unit 26, and responds from the address of the header part stored in the first message receiving unit 26. The tag state of the block is read from the tag memory 22, and what kind of processing is to be performed is determined according to the value. At this time, a possible value of the tag state is 'I', 'E' or 'D', and cannot be 'S'.
[0071]
When the tag state is 'E' or 'D' and the latest block exists, the sequence shown in FIG. 10 is obtained.
[0072]
The first consistency maintenance control unit 23 first generates a header part of the FD message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is a device number representing the memory MMi specified from the address of the header stored in the first message receiving unit 26 (here, the memory MM2 is specified from the address and the destination device is specified). The message identifier is an identifier representing FD, the address and the request source device number are the address of the message header portion stored in the second message receiving unit 41 and the request source device number (here, “101”). 000 '). In addition, the first consistency maintenance control unit 23 instructs the first data control unit 24 to read the block specified from the address stored in the first message receiving unit 26 from the cache memory 25, and The issued block is supplied to the first message transmission unit 27 as the data portion of the FD message. The first message transmission unit 27 sends the message to the interconnection network 12 by combining the header unit supplied from the first consistency maintenance control unit 23 and the data unit supplied from the first data control unit 24. Further, the first consistency maintenance control unit 23 writes in the tag memory 22 and updates the tag state of the corresponding block to “S”.
[0073]
The sent FD message is delivered by the interconnection network 12 and taken into the second message receiver 41 of the memory MM2. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the second data control unit 45.
[0074]
The second consistency maintenance control unit 44 of the memory MM2 detects that the FD message has been taken into the second message reception unit 41, and determines the corresponding block from the address of the header part stored in the second message reception unit 41. The directory state and the directory map are read from the directory memory 43. At this time, the possible value of the directory state is limited to 'RMP' in terms of the method.
[0075]
The second consistency maintenance control unit 44 first generates a header part of the SDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents SDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second consistency maintenance control unit 44 causes the second data control unit 45 to write the block added to the FD message to the corresponding block in the main memory 46. The second data control unit 45 performs writing to the main memory 46 and at the same time supplies the block added to the FD message to the second message transmission unit 42 as a data portion of the SDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. Further, the second consistency maintenance control unit 44 writes the directory memory 43, and changes the directory state to C and the value of the directory map to “1101”. The value of this directory map is a bit corresponding to the cache CM1 specified from the request source device number stored in the second message receiving unit 41 with respect to the value of the directory map immediately before receiving the FD message. This is the value obtained as a result of performing the operation.
[0076]
The sent SDR message is delivered by the interconnection network 12, and is taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the first consistency maintenance control unit 23, and the data part is supplied to the first data control unit 24.
[0077]
The operation when the first consistency maintenance control unit 23 of the cache CM 1 detects that the SDR message has been taken into the first message receiving unit 26 is performed when the cache CM 1 receives the SDR message in the sequence shown in FIG. Is the same.
[0078]
Next, when the first consistency maintenance control unit 23 of the cache CM 3 that has received the FR message reads the tag state of the corresponding block of the tag memory 22 and the tag state is “I”, FIG. It becomes the sequence shown.
[0079]
The first consistency maintenance control unit 23 first generates a header part of the ACK message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is a device number representing the memory MMi specified from the address of the header stored in the first message receiving unit 26 (here, the destination where the memory MM2 is specified from the address) (The device number is '101'), the message identifier is an identifier indicating ACK, the address and the request source device number are the address of the message header part stored in the second message receiver 41 and the request source device number (here, '000'). The first message transmission unit 27 sends the header part supplied from the first consistency maintenance control unit 23 to the interconnection network 12 as a message.
[0080]
The transmitted ACK message is delivered by the interconnection network 12, and is taken into the second message receiving unit 41 of the memory MM2. The header part of the captured message is supplied to the second consistency maintenance control unit 44.
[0081]
The second consistency maintenance control unit 44 of the memory MM2 detects that the ACK message has been taken into the second message reception unit 41, and determines the corresponding block from the address of the header part stored in the second message reception unit 41. The directory state and the directory map are read from the directory memory 43. At this time, the possible values of the directory state are limited to 'WSP' and 'RMP' in terms of the method, but here, the case where the directory state is 'RMP' in the sequence shown in FIG.
[0082]
The second consistency maintenance control unit 44 first generates a header part of the EDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents EDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). Further, the second consistency maintenance control unit 44 reads the block specified by the address of the message header part stored in the second message reception unit 41 from the main memory 46 to the second data control unit 45. Instruct. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data part of the EDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and changes the directory state to M and the directory map to “0001”. In this directory map value, the bit corresponding to the cache CMi (here, the cache CM1) specified by the request source device number of the message header stored in the second message receiver 41 is set to '1', This is a value obtained as a result of performing an operation to set other bits to “0”.
[0083]
The sent EDR message is delivered by the interconnection network 12, and is taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the first data control unit 24.
[0084]
The operation when the first consistency maintaining control unit 23 of the cache CM 1 detects that the EDR message is taken into the first message receiving unit 26 is performed when the cache CM 1 receives the EDR message in the sequence shown in FIG. Is the same.
[0085]
Next, as a result of the second consistency maintenance control unit 44 of the memory MM2 receiving the RM message reading the directory state and directory map of the corresponding block of the directory memory 43, the directory state is “RMP” or “WSP”. If there is, the sequence shown in FIG. 12 is obtained.
[0086]
The second consistency maintenance control unit 44 first generates a header portion of the NCR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents NCR. In the identifier, the address and the request source apparatus number are the address of the message header part supplied to the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message.
[0087]
The sent NCR message is delivered by the interconnection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the first consistency maintenance control unit 23.
[0088]
The first consistency maintenance control unit 23 of the cache CM 1 detects that the NCR message is taken into the first message reception unit 26, evaluates the memory access stored in the memory access management unit 21 again, and performs data consistency. Perform necessary processing to maintain sex.
[0089]
The above is the operation for maintaining data consistency in the case of a cache miss.
[0090]
Next, it is detected that the memory access has been taken into the memory access management unit 21, and the tag state of the corresponding block is read from the tag memory 22 from the access stored in the memory access management unit 21. The operation when the memory access taken into the management unit 21 is read and the tag state is 'S', 'E', or 'D' (in the case of a read hit) will be described.
[0091]
The first consistency maintenance control unit 23 can read the data specified by the address stored in the memory access management unit 21 from the cache memory 25 to the first data control unit 24. The read data is supplied to the memory access management unit 21 and captured. The data fetched into the memory access management unit 21 is supplied to the processor PR1. Further, the first consistency maintenance control unit 23 sends a memory access completion response to the processor PR1, causes the processor PR1 to take in data supplied by the memory access management unit 21, and completes the read access.
[0092]
Next, it is detected that the memory access is taken into the memory access management unit 21, and the tag state of the corresponding block is read from the tag memory 22 from the address stored in the memory access management unit 21. The operation when the memory access taken into the management unit 21 is writing and the tag state is 'E' or 'D' will be described (in the case of a write hit).
[0093]
The first consistency maintenance control unit 23 causes the first data control unit 23 to rewrite the data specified from the address output from the memory access management unit 21 of the cache memory 25 to the data supplied by the memory access management unit 21. . In addition, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state to “D”. The first consistency maintenance control unit 23 sends a memory access completion response to the processor PR1 to complete the write access.
[0094]
Next, it is detected that the memory access is taken into the memory access management unit 21, and the tag state of the corresponding block is read from the tag memory 22 from the address stored in the memory access management unit 21. The operation when the memory access taken into the management unit 21 is writing and the tag state is 'S' will be described (in the case of write sharing).
[0095]
The first consistency maintenance control unit 23 first generates a header part of the WS message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is “101” representing the memory MM2, the message identifier is the identifier representing WS, the address is the address stored in the memory access management unit 21, and the request source device number is It becomes “000” indicating the device number of the cache CM1. In addition, the first consistency maintenance control unit 23 supplies the data specified by the address output from the memory access management unit 21 of the cache memory 25 to the data supplied by the memory access management unit 21 to the first data control unit 24. Let them be rewritten. At this time, the first data control unit 24 writes the data supplied from the memory access management unit 21 to the cache memory 25 and also supplies it to the first message transmission unit 27. The first message transmission unit 27 sends a message to the interconnection network 12 by combining the header unit supplied from the first consistency maintenance control unit 23 and the data unit supplied from the first data control unit 24.
[0096]
The sent WS message is delivered by the interconnection network 12 and taken into the second message receiver 41 of the memory MM2. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the second data control unit 45.
[0097]
The second consistency maintaining control unit 44 of the memory MM2 detects that the WS message has been taken into the second message receiving unit 41, and determines the corresponding block from the address of the header part stored in the second message receiving unit 41. The directory state and the directory map are read from the directory memory 43. At this time, the possible values of the directory state are limited to 'C' or 'WSP' in terms of the method. When the directory state is C, the bit of the directory map corresponding to the cache CM1 that issued the WS message is always “1”.
[0098]
When the directory state is “C” and the value of the directory map indicates that there is no cache CMi that holds a block other than the cache CMi that issued the WS message (here, the cache CM1 is issuing the WS message) (This is the case where the directory map is “0001”).
[0099]
The second consistency maintenance control unit 44 first generates a header part of the CR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents CR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message. In addition, the second consistency maintenance control unit 44 supplies the data specified from the address output from the second message reception unit 41 of the main memory 46 to the second data control unit 45 by the second message reception unit 41. Let the data be rewritten.
[0100]
The sent CR message is delivered by the interconnection network 12, and is taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the first consistency maintenance control unit 23.
[0101]
The first consistency maintenance control unit 23 of the cache CM 1 detects that the CR message has been taken into the first message reception unit 26, sends a memory access completion response to the processor PR 1, and completes the write access.
[0102]
Next, as a result of the second consistency maintenance control unit 44 of the memory MM2 receiving the WS message reading the directory state and directory map of the corresponding block of the directory memory 43, the directory state is C, and the directory map When the value indicates that there is a cache CMi that holds a block other than the cache CMi that issued the WS message (here, since the cache CM1 has issued the WS message, the value of the directory map is other than “0001”) This is the sequence shown in FIG. Hereinafter, in the example illustrated in FIG. 14, a case where the value of the directory map when the WS message is received is, for example, “1101” will be described.
[0103]
The second consistency maintenance control unit 44 first checks whether the cache CM1 holds the latest block and is not the cache CMi that issued the WS message. At this time, since the cache CM1 is a cache CMi that has issued a WS message from the request source device number stored in the second message receiving unit 41, nothing is done in this case.
[0104]
Next, the second consistency maintenance control unit 44 checks whether the cache CM2 holds the latest block and is not the cache CMi that issued the WS message. At this time, from the directory map value “1101”, the cache CM 2 does not hold the latest data, so nothing is done in this case.
[0105]
Next, the second consistency maintenance control unit 44 checks whether or not the cache CM 3 holds the latest block and is not the cache CMi that has issued the WS message. At this time, since the cache CM 3 holds the latest block and is not the cache CMi that issued the WS message, the following processing is performed. The second consistency maintenance control unit 44 generates a header part of the IV message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is “010” representing the cache CM 3, the message identifier is the identifier representing IV, the address and the request source device number are the messages stored in the second message receiving unit 41. The address of the header part and the request source device number (here, “000”). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 as a message to the interconnection network 12.
[0106]
Next, the second consistency maintenance control unit 44 checks whether the cache CM 4 holds the latest block and is not the cache CMi that has issued the WS message. At this time, since the cache CM 4 holds the latest block and is not the cache CM i that issued the WS message, the header part of the IV message is generated as in the case of the cache CM 3 described above. However, the destination device number is “011” representing the cache CM4.
[0107]
Finally, the second consistency maintenance control unit 44 supplies the data specified from the address output from the second message reception unit 41 of the main memory 46 to the second data control unit 45 by the second message reception unit 41. To rewrite the data. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and changes the directory state to “WSP” and the directory map to “0010”. The directory map value represents the number of transmitted IV messages.
[0108]
The two transmitted IV messages are delivered by the interconnection network 12, and are taken into the first message receiving unit 26 of the cache CM3 and the cache CM4, respectively. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the first data control unit 24.
[0109]
The first consistency maintenance control unit 23 of the cache CM 3 detects that the IV message has been taken into the first message reception unit 26, and responds from the address of the header part stored in the first message reception unit 26. The tag state of the block is read from the tag memory 22, and what kind of processing is to be performed is determined according to the value. At this time, the possible value of the tag state is limited to 'I' or 'S'.
[0110]
When the tag state is “I”, the first consistency maintenance control unit 23 first generates a header part of the ACK message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is a device number representing the memory MMi specified from the address of the header stored in the first message receiving unit 26 (here, the memory MM2 is specified from the address and the destination device is specified). The message identifier is an identifier indicating ACK, the address and the request source device number are the address of the message header part stored in the second message receiving unit 41 and the request source device number (here, ' 000 '). The first message transmission unit 27 sends the header part supplied from the first consistency maintenance control unit 23 to the interconnection network 12 as a message.
[0111]
If the tag state is 'S', the first consistency maintenance control unit 23 first generates a header part of the ACK message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is a device number representing the memory MMi specified from the address of the header stored in the first message receiving unit 26 (here, the memory MM2 is specified from the address and the destination device is specified). The message identifier is an identifier indicating ACK, the address and the request source device number are the address of the message header part stored in the second message receiving unit 41 and the request source device number (here, ' 000 '). The first message transmission unit 27 sends the header part supplied from the first consistency maintenance control unit 23 to the interconnection network 12 as a message. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the corresponding block to “I”.
[0112]
The transmitted ACK message is delivered by the interconnection network 12, and is taken into the second message receiving unit 41 of the memory MM2. The header part of the captured message is supplied to the second consistency maintenance control unit 44.
[0113]
The second consistency maintenance control unit 44 of the memory MM2 detects that the ACK message has been taken into the second message reception unit 41, and determines the corresponding block from the address of the header part stored in the second message reception unit 41. The directory state and the directory map are read from the directory memory 43. At this time, the possible values of the directory state are limited to 'WSP' and 'RMP' in terms of the method. Here, the case where the directory state is 'WSP' in the sequence shown in FIG. At this time, different processing is performed depending on whether the value of the directory map is '0001' or not.
[0114]
When the directory state is 'WSP' and the directory map is not '0001' (here, '0010'. In this case, an ACK message issued by the cache CM 3 in the sequence shown in FIG. 14 is received) 2 The consistency maintaining control unit 44 writes in the directory memory 43, and the directory state is “WSP” as it is, but the directory map is a value obtained by decrementing the values of all directory maps (here, “0001”). Update to
[0115]
Next, when the directory state is “WSP” and the value of the directory map is “0001” (when the ACK message issued by the cache CM 4 is received in the sequence shown in FIG. 14), the second consistency maintenance control First, the unit 44 generates a header part of the CR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents CR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and changes the directory state to M and the directory map to “0001”. The value of this directory map is such that the bit corresponding to the cache CMi (here, the cache CM1) specified from the request source device number in the header stored in the second message receiving unit 41 is set to “1”. This is a value obtained as a result of performing an operation to set the bit to “0”.
[0116]
The sent CR message is delivered by the interconnection network 12, and is taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the first data control unit 24.
[0117]
The operation when the first consistency maintaining control unit 23 of the cache CM 1 detects that the CR message is taken into the first message receiving unit 26 is performed when the cache CM 1 receives the CR message in the sequence shown in FIG. Is the same.
[0118]
Next, when the second consistency maintenance control unit 44 of the memory MM2 that has received the WS message reads the directory state and the directory map of the corresponding block of the directory memory 43, the directory state is 'WSP'. The sequence shown in FIG. 15 is obtained. At this time, a WS message from another cache CMi is already being received and processed in the same block, and when processing the WS message, the memory MM2 transmits an IV message to the cache CM1. . Thereby, the tag state of the block stored in the tag memory 22 in the cache CM1 is updated from 'S' to 'I'.
[0119]
The second consistency maintenance control unit 44 first generates a header portion of the NCR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents NCR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message.
[0120]
The sent NCR message is delivered by the interconnection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the first consistency maintenance control unit 23.
[0121]
The operation when the first consistency maintenance control unit 23 of the cache CM 1 detects that the NCR message is taken into the first message reception unit 26 is performed when the cache CM 1 receives the NCR message in the sequence shown in FIG. Is the same.
[0122]
Next, effects of the first exemplary embodiment of the present invention will be described.
[0123]
For example, consider an operation when the processor PR1 performs writing and then the processor PR4 performs reading in a state where the blocks of the memory MM2 exist and are shared in the cache CM1 and the cache CM3. Since the write performed by the processor PR1 is reflected in the cache CM1 and the memory MM2, the latest data exists in the cache CM1 and the memory MM2.
[0124]
Therefore, when the processor PR4 next reads, a read request message is transmitted to the memory MM2, but since the latest data exists in the memory MM2, the memory MM2 immediately stores the latest block in the cache CM1. An attached message can be transmitted. For this reason, there is no processing for requesting write-back to the cache CMi that only holds the latest block in the memory MM2, and receiving the response, thereby shortening the time required for responding to the data read by the processor PR4. Can do. Further, since it is not necessary to request write back, the number of messages exchanged between the cache and the memory can be reduced in order to maintain data consistency.
[0125]
Next, in the data consistency maintenance control method in the second embodiment, the tag states stored in the tag memory 22 are I, S, E, as in the data consistency maintenance control method in the first embodiment. It consists of four states of D. Further, the directory map stored in the directory memory 43 is also constituted by a full map system consisting of 4 bits. The directory state is also composed of four states, C, M, RMP, and WSP.
[0126]
The messages exchanged between the cache CMi and the memory MMi in the data consistency maintenance control method in the second embodiment include RM, WS, and the like in the data consistency maintenance control method in the first embodiment. An ECR message is newly added to 11 types of messages such as WB, FR, IV, FD, ACK, SDR, EDR, CR, and NCR, and there are 12 types of messages. Like the CR message, the ECR message is a response message for notifying the cache CMi from which the memory MMi has issued the WS message that processing for the WS message has been completed in the memory MMi.
[0127]
Next, in the data consistency maintenance control method according to the second embodiment, a case where the processor PR1 accesses data in the memory MM2 is taken as an example, and a series of operations for maintaining data consistency performed by the access are performed. Only the differences from the data consistency maintenance control method in the first embodiment are shown.
[0128]
The operation of the data consistency maintenance control method in the second embodiment is different from the operation of the data consistency maintenance control method in the first embodiment in that the second consistency maintenance of the memory MM2 that has received the WS message is different. As a result of the control unit 44 reading the directory state and directory map of the corresponding block in the directory memory 43, the directory state is C, and the value of the directory map is a cache that holds blocks other than the cache CMi that issued the WS message. This is a case where the CMi does not exist (here, since the cache CM1 issues a WS message, the value of the directory map is “0001”). That is, the data consistency maintaining control method according to the first embodiment is a sequence shown in FIG.
[0129]
In this case, the data consistency maintenance control method according to the second embodiment takes the sequence shown in FIG.
[0130]
The second consistency maintenance control unit 44 first generates a header part of the ECR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents ECR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message. In addition, the second consistency maintenance control unit 44 supplies the data specified from the address output from the second message reception unit 41 of the main memory 46 to the second data control unit 45 by the second message reception unit 41. Let the data be rewritten. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and changes the directory state to M and the directory map to “0001”. The value of this directory map is a value obtained as a result of an operation of setting the bit corresponding to the cache CM1 that issued the RM message to “1” and setting the other bits to “0”.
[0131]
The sent ECR message is delivered by the interconnection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44, and the data part is supplied to the first data control unit 24.
[0132]
The first consistency maintenance control unit 23 of the cache CM1 writes the tag memory 22 and updates the tag state of the corresponding block from 'S' to 'E'. In addition, the first consistency maintenance control unit 23 sends a memory access completion response to the processor PR1 to complete the write access.
[0133]
Next, effects of the second exemplary embodiment of the present invention will be described.
[0134]
For example, in a state where the block state of the cache CM1 is a shared state and the latest block exists only in the cache CM1 and the memory MM2, the processor PR1 writes continuously, and no other processor PRi accesses during that time. Think about the case. In this case, in the data consistency maintenance control method according to the first embodiment, a write request message is issued from the cache CM1 to the memory MM2 for each write, and the number of messages for data consistency maintenance control in this case increases. There is a problem of doing.
[0135]
In the data consistency maintenance control method according to the second embodiment, in the above case, the write request message is issued from the cache CM1 to the memory MM2 for the first two writes, but the subsequent third time. No message for data consistency maintenance control is issued with respect to writing from, and an increase in the number of messages in this case can be prevented.
[0136]
Next, in the data consistency maintenance control method in the third embodiment, the tag states stored in the tag memory 22 are I, S, E, and the like, as in the data consistency maintenance control method in the second embodiment. It consists of four states of D. Further, the directory map stored in the directory memory 43 is also constituted by a full map system consisting of 4 bits. The directory state is also composed of four states, C, M, RMP, and WSP.
[0137]
In the data consistency maintenance control method according to the third embodiment, in addition to the directory state and the directory map, the update frequency value is held in the directory memory 43 as information about the block. The update frequency value indicates how many times the memory MMi holds the latest block before receiving the RM message from the other cache CMi in a state where one cache CMi and the memory MMi hold the latest block. This is a value obtained by counting whether a WS message has been received from the cache CMi.
[0138]
In the data consistency maintenance control method according to the third embodiment, an update frequency upper limit value is newly defined as a parameter.
[0139]
Further, in the data consistency maintenance control method in the third embodiment, the message exchanged between the cache CMi and the memory MMi is similar to the message in the data consistency maintenance control method in the second embodiment. There are 12 types of messages: RM, WS, WB, FR, IV, FD, ACK, SDR, EDR, CR, NCR, and ECR.
[0140]
Next, in the data consistency maintenance control method according to the third embodiment, a case where the processor PR1 accesses data in the memory MM2 will be described as an example, and a series of operations for maintaining data consistency performed by the access will be described. To do.
[0141]
The operation of the cache CMi in the data consistency maintenance control method in the third embodiment is the same as the operation of the cache CMi in the data consistency maintenance control method in the second embodiment. Is omitted. Hereinafter, the operation of the memory MMi in the data consistency maintenance control method according to the third embodiment will be described in the order in which five types of messages of RM, WS, WB, FD, and ACK are received.
[0142]
When the second consistency maintenance control unit 44 of the memory MM2 detects that the RM message has been taken into the second message reception unit 41, the second consistency maintenance control unit 44 determines the corresponding block from the header part address stored in the second message reception unit 41. The directory state, the directory map, and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined based on the values.
[0143]
Cache CMi that holds a block other than the cache CMi that has a directory state of C and the directory map value has issued an RM message (identified from the request source device number added to the message and in this case is cache CM1) (In this case, the directory map is “0000” or “0001”), regardless of the value of the update frequency value, in the sequence shown in FIG. Processing when an RM message is received.
[0144]
The second consistency maintenance control unit 44 first generates a header part of the EDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents EDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). Further, the second consistency maintenance control unit 44 reads the block specified by the address of the message header part stored in the second message reception unit 41 from the main memory 46 to the second data control unit 45. Instruct. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data part of the EDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. In addition, the second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to M, the directory map to “0001”, and the update frequency value to “0”. The value of this directory map is a value obtained as a result of an operation of setting the bit corresponding to the cache CM1 that issued the RM message to “1” and setting the other bits to “0”.
[0145]
When the directory state is C and the value of the directory map indicates that there is a cache CMi that holds a block other than the cache CMi that issued the RM message (here, the cache CM1) (here, the cache CM1 is RM) (This is a case where the directory map is other than “0000” or “0001” since the message is issued), and the memory MM2 receives the RM message from the cache CM1 in the sequence shown in FIG. 18 regardless of the value of the update frequency value. Process if received.
[0146]
The second consistency maintenance control unit 44 first generates a header part of the SDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents SDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). Further, the second consistency maintenance control unit 44 reads the block specified by the address of the message header part stored in the second message reception unit 41 from the main memory 46 to the second data control unit 45. Instruct. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data part of the SDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. The second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to C, the directory map value to “1101”, and the update frequency value to “0”. The value of this directory map is a bit corresponding to the cache CM1 specified from the request source device number stored in the second message receiving unit 41 with respect to the value of the directory map immediately before receiving the RM message. This is the value obtained as a result of performing the operation.
[0147]
When the directory state is M, processing is performed when the memory MM2 receives the RM message from the cache CM1 in the sequence shown in FIGS. 19 and 20 regardless of the value of the update frequency value. In this case, the cache CMi holding the latest block is uniquely determined from the directory map. In the example shown in FIGS. 19 and 20, since the value of the directory map is “0100”, it can be confirmed that the cache CM 3 holds only the latest data.
[0148]
The second consistency maintenance control unit 44 first generates a header part of the FR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is “010” representing the cache CM 3 holding the latest block, the message identifier is an identifier representing FR, the address and the request source device number are the second message receiving unit 41. Are the address of the message header part stored in and the request source device number (here, “000”). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 as a message to the interconnection network 12. The second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to RMP and the update frequency value to “0”, but leaves the directory map as it is.
[0149]
When the directory state is 'RMP' or 'WSP', the process when the memory MM2 receives the RM message from the cache CM1 in the sequence shown in FIG. 21 regardless of the value of the directory map and the update frequency value. To do.
[0150]
The second consistency maintenance control unit 44 first generates a header portion of the NCR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents NCR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message.
[0151]
Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the WS message has been taken into the second message reception unit 41, the address of the header part stored in the second message reception unit 41 is used. The directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined based on the values.
[0152]
The directory state is “C” and the value of the directory map indicates that there is no cache CMi that holds a block other than the cache CMi that issued the WS message (in this case, the cache CM1 has issued the WS message). If the update frequency value does not match the update frequency upper limit value, the process when the memory MM2 receives the WS message from the cache CM1 in the sequence shown in FIG. do.
[0153]
The second consistency maintenance control unit 44 first generates a header part of the CR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header part stored in the second message receiving unit 41 (in this case, “000”). The message identifier is an identifier representing CR, and the address and the request source device number are the address of the message header part stored in the second message receiving unit 41 and the request source device number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message. In addition, the second consistency maintenance control unit 44 supplies the data specified from the address output from the second message reception unit 41 of the main memory 46 to the second data control unit 45 by the second message reception unit 41. Let the data be rewritten. In addition, the second consistency maintenance control unit 44 writes the directory memory 43, keeps the directory state and the directory map as they are, and updates the update frequency value to a value added by one. In the sequence shown in FIG. 22, the update frequency value is updated from “0” to “1”.
[0154]
The directory state is “C” and the value of the directory map indicates that there is no cache CMi that holds a block other than the cache CMi that issued the WS message (in this case, the cache CM1 has issued the WS message). If the update frequency value matches the update frequency upper limit value, the processing when the memory MM2 receives the WS message from the cache CM1 is performed in the sequence shown in FIG. . The sequence shown in FIG. 23 is a case where the update frequency upper limit value is set to “2”.
[0155]
The second consistency maintenance control unit 44 first generates a header part of the ECR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents ECR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message. In addition, the second consistency maintenance control unit 44 supplies the data specified from the address output from the second message reception unit 41 of the main memory 46 to the second data control unit 45 by the second message reception unit 41. Let the data be rewritten. In addition, the second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to M, the directory map to “0001”, and the update frequency value to “0”. The value of this directory map is a value obtained as a result of an operation of setting the bit corresponding to the cache CM1 that issued the RM message to “1” and setting the other bits to “0”.
[0156]
When the directory state is C and the value of the directory map indicates that there is a cache CMi that holds a block other than the cache CMi that issued the WS message (in this case, the cache CM1 has issued the WS message) This is the case when the memory MM2 receives a WS message from the cache CM1 in the sequence shown in FIG. 24, regardless of the update frequency value. Hereinafter, in the example shown in FIG. 24, a case where the value of the directory map when the WS message is received is, for example, “1101” will be described.
[0157]
The second consistency maintenance control unit 44 first checks whether the cache CM1 holds the latest block and is not the cache CMi that issued the WS message. At this time, since the cache CM1 is a cache CMi that has issued a WS message from the request source device number stored in the second message receiving unit 41, nothing is done in this case.
[0158]
Next, the second consistency maintenance control unit 44 checks whether the cache CM2 holds the latest block and is not the cache CMi that issued the WS message. At this time, from the directory map value “1101”, the cache CM 2 does not hold the latest data, so nothing is done in this case.
[0159]
Next, the second consistency maintenance control unit 44 checks whether or not the cache CM 3 holds the latest block and is not the cache CMi that has issued the WS message. At this time, since the cache CM 3 holds the latest block and is not the cache CMi that issued the WS message, the following processing is performed. The second consistency maintenance control unit 44 generates a header part of the IV message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is “010” representing the cache CM 3, the message identifier is the identifier representing IV, the address and the request source device number are the messages stored in the second message receiving unit 41. The address of the header part and the request source device number (here, “000”). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 as a message to the interconnection network 12.
[0160]
Next, the second consistency maintenance control unit 44 checks whether the cache CM 4 holds the latest block and is not the cache CMi that has issued the WS message. At this time, since the cache CM 4 holds the latest block and is not the cache CM i that issued the WS message, the header part of the IV message is generated as in the case of the cache CM 3 described above. However, the destination device number is “011” representing the cache CM4.
[0161]
Finally, the second consistency maintenance control unit 44 supplies the data specified from the address output from the second message reception unit 41 of the main memory 46 to the second data control unit 45 by the second message reception unit 41. To rewrite the data. Further, the second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to “WSP”, the directory map to “0010”, and the update frequency value to “0”. The directory map value represents the number of transmitted IV messages.
[0162]
When the directory state is “WSP”, the processing when the memory MM2 receives the WS message from the cache CM1 is performed in the sequence shown in FIG. 25 regardless of the directory map and the update frequency value.
[0163]
The second consistency maintenance control unit 44 first generates a header portion of the NCR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiver 41 (in this case, “000”), and the message identifier represents NCR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second message transmission unit 42 sends the header part supplied from the second consistency maintenance control unit 44 to the interconnection network 12 as a message.
[0164]
Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the WB message has been taken into the second message reception unit 41, the second consistency maintenance control unit 44 uses the address of the header part stored in the second message reception unit 41. The directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined based on the values. At this time, possible values of the directory state are limited to 'M' or 'RMP' in terms of the method.
[0165]
When the directory state is “M”, the processing when the memory MM3 receives the WB message from the cache CM1 is performed in the sequence shown in FIG. 26 regardless of the value of the update frequency value. The second consistency maintenance control unit 44 writes the directory memory 43, sets the directory state to C, sets the directory map to “0000” indicating that no cache CMi holds a block, and sets the update frequency value to “0”. Update to '. In addition, the second consistency maintenance control unit 44 causes the second data control unit 45 to write the block added to the WB message to the corresponding block in the main memory 46.
[0166]
When the directory state is RMP, the processing when the memory MM3 receives the WB message from the cache CM1 is performed in the sequence shown in FIG. 27 regardless of the values of the directory map and the update frequency value. The second consistency maintenance control unit 44 only causes the second data control unit 45 to write the block added to the WB message to the corresponding block of the main memory 46, and does not update the directory memory 43.
[0167]
Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the FD message is taken into the second message reception unit 41, the second consistency maintenance control unit 44 uses the address of the header part stored in the second message reception unit 41. Processing when the directory state and directory map and the update frequency value of the corresponding block are read from the directory memory 43 and the memory MM2 receives the FD message from the cache CM3 in the sequence shown in FIG. 19 regardless of the update frequency value. do. At this time, the possible value of the directory state is limited to 'RMP' in terms of the method.
[0168]
The second consistency maintenance control unit 44 first generates a header part of the SDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents SDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The second consistency maintenance control unit 44 causes the second data control unit 45 to write the block added to the FD message to the corresponding block in the main memory 46. The second data control unit 45 performs writing to the main memory 46 and at the same time supplies the block added to the FD message to the second message transmission unit 42 as a data portion of the SDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. The second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to C, the directory map value to “1101”, and the update frequency value to “0”. The value of this directory map is a bit corresponding to the cache CM1 specified from the request source device number stored in the second message receiving unit 41 with respect to the value of the directory map immediately before receiving the FD message. This is the value obtained as a result of performing the operation.
[0169]
Next, when the second consistency maintaining control unit 44 of the memory MM2 detects that the ACK message has been taken into the second message receiving unit 41, the address of the header part stored in the second message receiving unit 41 is used. The directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined based on the values. At this time, the possible values of the directory state are limited to 'WSP' or 'RMP' in terms of the method.
[0170]
When the directory state is “RMP”, processing is performed when the memory MM2 receives an ACK message from the cache CM3 in the sequence shown in FIG. 20 regardless of the update frequency value.
[0171]
The second consistency maintenance control unit 44 first generates a header part of the EDR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents EDR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). Further, the second consistency maintenance control unit 44 reads the block specified by the address of the message header part stored in the second message reception unit 41 from the main memory 46 to the second data control unit 45. Instruct. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data part of the EDR message. The second message transmission unit 42 sends the message to the interconnection network 12 by combining the header unit supplied from the second consistency maintenance control unit 44 and the data unit supplied from the second data control unit 45. In addition, the second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to M, the directory map to “0001”, and the update frequency value to “0”. In this directory map value, the bit corresponding to the cache CMi (here, the cache CM1) specified by the request source device number of the message header stored in the second message receiver 41 is set to '1', This is a value obtained as a result of performing an operation to set other bits to “0”.
[0172]
When the directory state is “WSP” and the directory map is not “0001”, the processing when the memory MM2 receives the ACK message issued by the cache CM3 in the sequence shown in FIG. 24 is performed regardless of the value of the update frequency value. .
[0173]
The second consistency maintenance control unit 44 writes in the directory memory 43 and sets the directory state to “WSP” as it is, but the directory map is a value obtained by decrementing the value of the previous directory map (here, “0001”). ), The update frequency value is updated to '0'.
[0174]
Next, when the directory state is “WSP” and the value of the directory map is “0001”, the memory MM2 receives the ACK message issued by the cache CM4 in the sequence shown in FIG. 24 regardless of the value of the update frequency value. Process if
[0175]
First, the second consistency maintenance control unit 44 generates a header part of the CR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the request source device number of the message header stored in the second message receiving unit 41 (in this case, “000”), and the message identifier represents CR. In the identifier, the address and the request source apparatus number are the address of the message header part stored in the second message receiving unit 41 and the request source apparatus number (here, “000”). The header part supplied from the second message transmission unit 42 and the second consistency maintenance control unit 44 is sent to the interconnection network 12 as a message. Further, the second consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to M, the directory map to “0001”, and the update frequency value to “0”. In this directory map value, the bit corresponding to the cache CMi (here, the cache CM1) specified from the request source device number in the header stored in the second message receiver 1 is set to “1”, This is a value obtained as a result of performing an operation to set the bit to “0”.
[0176]
Next, effects of the third exemplary embodiment of the present invention will be described.
[0177]
For example, in a state where the block state of the cache CM1 is a shared state and the latest block exists only in the cache CM1 and the memory MM2, the processor PR1 writes continuously, and no other processor PRi accesses during that time. Think about the case. In this case, in the data consistency maintenance control method according to the first embodiment, a write request message is issued from the cache CM1 to the memory MM2 for each write. Therefore, there is a problem that the number of messages for data consistency maintenance control in this case increases. In the data consistency maintenance control method in the second embodiment, the first two writes are reflected in the memory, but the third and subsequent writes are not reflected in the memory. Therefore, after the second writing, the latest block does not exist in the memory MM2. Therefore, when another processor PRi accesses thereafter, the latest block does not exist in the memory MM2, and in this case, it takes a long time until the data is responded to the processor after a cache miss occurs. Become.
[0178]
In the data consistency maintenance control method according to the third embodiment, when the update frequency upper limit value that is a parameter is set to N, the first N + 1 writes are also reflected in the memory MM2. Therefore, the latest block exists in the memory MM2 until N + 1 writing is performed. For this reason, when another processor PRi accesses during that time, the latest block exists in the memory MM2, and therefore it is possible to reduce the time required until data is returned to the processor after a cache miss occurs. If there is no access during that time, the writing is not reflected in the memory MM2 from the (N + 2) th time. Therefore, an increase in messages in this case can be prevented.
[0179]
【The invention's effect】
The first effect is that, when a cache miss occurs due to reading by the processor, it is possible to shorten the time required until data is returned from the cache to the processor.
[0180]
The reason is that when writing is performed on a block shared by the processors, the memory also reflects the writing and the latest block exists.
[0181]
The second effect is that it is possible to reduce messages for data consistency maintenance control generated when a cache miss occurs due to reading by the processor.
[0182]
The reason is that when writing is performed on a block shared by the processors, the memory also reflects the writing and the latest block exists.
[0183]
A third effect is that an increase in the number of messages generated by processor writing can be suppressed.
[0184]
The reason is that if the processor writes continuously to the block that is actually shared by multiple caches, and the other cache does not access during that time, the write is not reflected in the memory. This is because it is cut off.
[0185]
The fourth effect is that it is possible to adjust whether the first and second effects are strengthened or the third effect is strengthened.
[0186]
The reason is that the number of times the processor continuously writes to a block that is shared by multiple caches and when the other cache does not access during that time, the write is reflected in memory. This is because it can be set with a parameter.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a conventional multiprocessor system according to the present invention.
FIG. 2 is a configuration explanatory diagram of a cache according to the present invention.
FIG. 3 is a diagram illustrating the configuration of a memory according to the present invention.
FIG. 4 is a diagram illustrating a relationship between a directory map value and a cache held therein;
FIG. 5 is a view for explaining the structure of a message header in the data consistency maintenance control method according to the first embodiment.
FIG. 6 is a sequence flow in the case where a block to be replaced is written back to the memory in the case of a cache miss in the data consistency maintenance control method according to the first embodiment.
FIG. 7 is a sequence flow for writing back a block that is a replacement target in the case of a cache miss in the data consistency maintenance control method according to the first embodiment to a memory;
FIG. 8 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the first embodiment.
FIG. 9 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the first embodiment.
FIG. 10 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the first embodiment.
FIG. 11 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the first embodiment.
FIG. 12 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the first embodiment.
FIG. 13 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the first embodiment.
FIG. 14 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the first embodiment.
FIG. 15 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the first embodiment.
FIG. 16 is a diagram for explaining the operation of the data consistency maintenance control method according to the second embodiment;
FIG. 17 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the third embodiment.
FIG. 18 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the third embodiment.
FIG. 19 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the third embodiment.
FIG. 20 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the third embodiment.
FIG. 21 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the third embodiment.
FIG. 22 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the third embodiment.
FIG. 23 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the third embodiment.
FIG. 24 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the third embodiment.
FIG. 25 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing in the third embodiment.
FIG. 26 is a sequence flow for writing back a block that is a replacement target in the case of a cache miss in the data consistency maintaining method according to the third embodiment to a memory;
FIG. 27 is a sequence flow in the case where a block to be replaced is written back to the memory in the case of a cache miss in the data consistency maintaining method according to the third embodiment.
[Explanation of symbols]
PRi processor
CMi cache
MMi memory
12 Interconnection network
21 Memory Access Manager
22 Tag memory
23 First Consistency Maintenance Control Unit
24 First data control unit
25 Cache memory
26 First message receiver
27 First message transmitter
41 Second message receiver
42 Second message transmitter
43 Directory memory
44 Second consistency maintenance control unit
45 Second data control unit
46 Main memory

Claims (2)

  In a directory-based data consistency maintenance control method in a multiprocessor system in which a plurality of processors and memories each having a cache are connected by an interconnection network,
  In the cache, manage whether for each block whether the block being held is in a shared state held in the cache of multiple processors or in a non-shared state that exists only in the cache of the processor,
  In the memory, which processor holds the block, manages whether the latest data exists in the memory, for each block,
  When the processor writes to a block in the cache, if the cache block status is unshared, the cache is reflected in the cache block, and the cache block status is in the shared status. If the information managed in the memory indicates that the cache of another processor holds the block, the write is reflected in the cache and the memory block, and the cache of the other processor holds the block. If so, invalidate the block, leave the state of the cache block in which the write was performed, as shared,
  If the cache block status is shared and the information managed in the memory indicates that the cache of another processor does not hold the block, the write is reflected in the cache and memory block. A data consistency maintenance control method, wherein the state of a cache block in which writing has been performed is transitioned to a non-shared state.   In a directory-based data consistency maintenance control method in a multiprocessor system in which a plurality of processors and memories each having a cache are connected by an interconnection network,
  In a cache, whether the block being held is in a shared state held in the cache of multiple processors or exists only in the cache of that processor To manage whether it is in a non-shared state
  In the memory, which processor holds the block, whether the latest data exists in the memory, and the update frequency value are managed for each block,
The update frequency value indicates that the cache of one processor having the information managed in the memory holds the block and the latest data exists in the memory, and the update frequency value is written from the processor holding the block in the cache. Record the number of reflections and if there is an access from another processor, return the number to 0,
  If the cache block is in a non-shared state, write is reflected in the cache block,
  If the cache block is in the shared state and the information managed in the memory indicates that the other processor's cache holds the block, the write is reflected in the cache and memory block. However, if the cache of another processor holds the block, the block is invalidated, and the state of the block of the cache in which the writing is performed remains the shared state.
  If the cache block status is shared, the information managed in the memory indicates that the cache of another processor does not hold the block, and the update frequency value is smaller than a certain value, the cache And the write is reflected in the memory block, the update frequency value is incremented, the state of the cache block in which the write was performed remains in the shared state,
  If the cache block status is shared, the information managed in the memory indicates that the cache of another processor does not hold the block, and the update frequency value matches a certain value, A data consistency maintenance control method characterized by reflecting a write in a cache and memory block, and transitioning the state of the cache block in which the write has been performed to a non-shared state.

Images