JP3684367B2 - Driving device for plasma display panel - Google Patents

Description

  The present invention relates to a plasma display panel driving apparatus.

  As a flat display device, an AC (AC discharge) type plasma display panel (hereinafter referred to as PDP) is known. FIG. 1 is a diagram showing a schematic configuration of a plasma display device including a driving device for driving such an AC type PDP.

In FIG. 1, the PDP 10 includes a row electrode Y _{1 to} Yn and a row electrode X _{1 to} Xn that form a pair of row electrodes corresponding to each row (first to nth rows) of _one screen. Is formed. Further, column electrodes D ₁ to D that form column electrodes corresponding to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space (not shown) perpendicular to the row electrode pairs. D _m is formed. At this time, one discharge cell is formed at the intersection of one row electrode pair (X, Y) and one column electrode D. The driving device 1 converts the supplied video signal into N-bit pixel data for each pixel, converts this into m pixel data pulses for each row in the PDP 10, and converts them into column electrodes D ₁ to D _{1 of the} PDP 10. D _m is applied to each. Further, the driving device 1 performs the reset pulse RP _X , the reset pulse RP _Y , the priming pulse PP, the scan pulse SP, the sustain pulse IP _X , the sustain pulse IP _Y , and the erase pulse EP at the timing as shown in FIG. A row electrode drive signal including each is generated and applied to the row electrode pairs (Y ₁ to Y n, X _{1 to} X n) of the PDP 10.

2, the driving device 1, first, at the same time the reset pulse RP _x of the positive voltage generated is applied it to all the row electrodes X ₁ to X _n, which generates a reset pulse RP _y of negative voltage Is applied to each of the row electrodes Y _{1 to} Y _n (simultaneous reset process). By applying such a reset pulse, all the discharge cells of the PDP 10 are excited to generate charged particles, and after the discharge ends, a predetermined amount of wall charges are uniformly formed in the dielectric layers of all the discharge cells.

Next, the driving device 1 generates pixel data pulses DP _{1 to} DP _m having a positive voltage corresponding to the pixel data for each row, and sequentially applies these to the column electrodes D _{1 to} D _m for each row. Go. Further, the driving device 1 applies the scanning pulse SP having a negative voltage and a relatively small pulse width at the same timing as the application of the pixel data pulses DP _{1 to} DP _m to the column electrodes D _{1 to} D _m. As shown in FIG. 2, this is sequentially applied to the row electrodes Y ₁ to Y _n . At this time, among the discharge cells existing in the row electrode to which the scan pulse SP is applied, discharge occurs in the discharge cell to which the high-voltage pixel data pulse is applied, and most of the wall charges are lost. On the other hand, since no discharge occurs in the discharge cells to which no pixel data pulse is applied, the wall charges remain. That is, whether or not wall charges remain in each discharge cell is determined according to the pixel data pulse applied to the column electrode. This means that pixel data is written to each discharge cell in response to the application of the scan pulse SP. The driving device 1 applies a positive voltage priming pulse PP to the row electrodes Y _{1 to} Y _n as shown in FIG. 2 immediately before applying such a negative voltage scanning pulse SP to each row electrode Y (pixels). Data writing process).

By applying the priming pulse PP, the charged particles obtained by the simultaneous reset operation and decreased with the passage of time are re-formed in the discharge space of the PDP 10. Therefore, pixel data is written by applying the scan pulse SP while such charged particles are present. Next, the driving device 1 continuously applies the positive voltage sustain pulse IP _Y to each of the row electrodes Y _{1 to} Y _n , and the positive voltage at a timing deviated from the application timing of the sustain pulse IP _Y. The sustain pulse IP _X is continuously applied to each of the row electrodes X _{1 to} X _n (sustain discharge stroke).

Over the period in which the sustain pulses IP _X and IP _Y are alternately applied, the discharge cells in which the wall charges remain remain repeatedly emit light and maintain the light emission state. Next, the driving device 1 generates a negative voltage erase pulse EP and applies it to the row electrodes Y _{1 to} Y _n simultaneously to erase the wall charges remaining in each discharge cell ( Wall charge elimination process).

FIG. 3 is a diagram showing a configuration of a pulse drive circuit that generates the reset pulse RP _Y and the sustain pulse IP _Y among the various drive pulses. In FIG. 3, a p-channel MOS (Metal Oxide Semiconductor) transistor Q1 in the sustain pulse generation circuit 102 is turned off when the logic level of the gate signal GT1 supplied to the gate terminal thereof is “1”. . The MOS transistor Q1 is turned on when the logic level of the gate signal GT1 is "0", and applies the positive terminal potential of the DC power supply B1 onto the line 2. The negative terminal of the DC power supply B1 is grounded. Further, the sustain pulse generating circuit 102 is provided with a capacitor C1 whose one end is grounded. The n-channel MOS transistor Q2 is turned off when the logic level of the gate signal GT2 supplied to its gate terminal is “0”, while the logic level of the gate signal GT2 is “1”. In such a case, the potential on the line 2 is applied to the other end of the capacitor C1 via the diode D1 and the coil L1. The n-channel MOS transistor Q3 is turned off when the logic level of the gate signal GT3 supplied to its gate terminal is “0”, while the logic level of the gate signal GT3 is “1”. In this case, the potential generated at the other end of the capacitor C1 is turned on and applied to the line 2 via the diode D2 and the coil L2. The p-channel MOS transistor Q4 is turned off when the logic level of the gate signal GT4 supplied to its gate terminal is “1”, while the logic level of the gate signal GT4 is “0”. In this case, the potential is turned on and the potential on the line 2 is pulled to the ground potential via the diode D3.

The n-channel MOS transistor Q5 in the reset pulse generation circuit 103 is turned off when the logic level of the gate signal GT5 supplied to its gate terminal is “0”. The MOS transistor Q5 is turned on when the logic level of the gate signal GT5 is "1", and applies the negative terminal potential of the DC power supply B2 to the line 2 via the resistor R1. The positive terminal of the DC power supply B2 is grounded. The n-channel MOS transistor Q6 is turned off when the logic level of the gate signal GT6 supplied to its gate terminal is “0”, while the logic level of the gate signal GT6 is “1”. In this case, the potential is turned on and the potential on the line 2 is pulled to the ground potential via the diode D4.

The diodes D1 to D4 are provided to prevent backflow. FIG. 4 is a diagram showing the supply timing of each of the gate signals GT1 to GT6 when generating the reset pulse RPy and the sustain pulse IPy as shown in FIG. As shown in FIG. 4, first, the MOS transistor Q5 is turned on in response to the gate signal GT5 of the logic level “1”. As a result, a negative potential generated at the negative terminal of the DC power supply B2 is applied to the line 2 to generate a reset pulse RPy having a negative voltage as shown in FIG.

Next, as shown in FIG. 4, the logic level of the gate signal GT3 is “0” to “1” to “0”, the logic level of the gate signal GT1 is “1” to “0” to “1”, and When the logic level of the gate signal GT2 is sequentially switched from “0” to “1” to “0”, the positive voltage sustain pulse IPy shown in FIG. 4 is generated. That is, first, the MOS transistor Q3 is turned on in response to the gate signal GT3 having the logic level “1”, and a current corresponding to the electric charge stored in the capacitor C1 passes through the MOS transistor Q3, the diode D2, and the coil L2. To flow onto line 2. As a result, the level of the row electrode drive signal on the line 2 gradually increases as shown in FIG. Next, the MOS transistor Q1 is turned on in response to the gate signal GT1 having the logic level “1”. As a result, the positive potential of the positive terminal of the DC power supply B1 is applied to the line 2, and the sustain pulse IPy having a positive voltage as shown in FIG. 4 is generated. Next, the MOS transistor Q2 is turned on in response to the gate signal GT2 having the logic level “1”. As a result, a current corresponding to the charge charged in the PDP 10 flows into the capacitor C1 via the MOS transistor Q2, the diode D1, and the coil L1. Due to the charging operation of the capacitor C1, the level of the sustain pulse IPy gradually decreases as shown in FIG.

As described above, the reset pulse generation circuit 103 and the sustain pulse generation circuit 102 generate drive pulses (reset pulse RPy, sustain pulse IPy) having different polarities, and apply them to the common line 2 at different timings. It has a configuration. Here, in the configuration shown in FIG. 3, the MOS transistors Q1 and Q5 are connected in series between the positive terminal of the DC power supply B1 and the negative terminal of the DC power supply B2. Further, the MOS transistors Q2 (Q3) and Q5 are connected in series between the capacitor C1 that generates substantially the same potential as the positive terminal of the DC power supply B1 and the negative terminal of the DC power supply B2. Become.

Therefore, as the MOS transistors Q1 to Q3 and Q4 shown in FIG. 3, a high breakdown voltage transistor that can withstand the potential difference between the positive terminal potential of the DC power supply B1 and the negative terminal potential of the DC power supply B2 must be used. There was a problem of not becoming.

  The present invention has been made to solve the above-described problem, and is a plasma display panel drive capable of applying a plurality of drive pulses having different polarities on the same row electrode of a PDP in a transistor having a relatively low breakdown voltage. An object is to provide an apparatus.

  According to a first aspect of the present invention, there is provided a plasma display panel driving apparatus including: a column electrode driving unit that applies pixel data pulses corresponding to pixel data to a plurality of column electrodes arranged in a vertical direction of the plasma display panel; A pulse having a predetermined polarity is applied to a plurality of row electrodes arranged in a horizontal direction intersecting with the electrodes, and a reset pulse having a polarity different from the predetermined polarity for generating charged particles in all discharge cells of the plasma display panel. A device for driving a plasma display panel comprising row electrode driving means, wherein the row electrode driving means includes a first DC power source having a terminal of the same polarity as the predetermined polarity connected to a first line, and the row. A second line for applying a voltage to the electrode, a third line for discharging the voltage applied to the row electrode, one end grounded, and the other end side The capacitor to which the second line and the third line are connected, the first coil provided in the second line, the second coil provided in the third line, and the predetermined polarity are different A second DC power supply having a terminal on the polarity side connected to the fourth line; a first MOS transistor provided on the first line; a second MOS transistor provided on the second line; and a third MOS transistor provided on the third line. A third MOS transistor provided; a fourth MOS transistor provided on the fourth line; and a fifth MOS transistor connecting the first line, the second line, and the third line to the row electrode in an on state. And the second DC power supply and the fourth MOS transistor receive the reset pulse when the fourth MOS transistor is on. When a reset pulse generating means to be applied to the electrode is configured and the first MOS transistor, the second MOS transistor, or the third MOS transistor is set to an on state, the fifth MOS transistor is set to an on state and the first MOS transistor is set to an on state. While the 4MOS transistor is set to an off state, when the reset pulse generating means applies the reset pulse to the row electrode, it has a control circuit for setting the fifth MOS transistor to an off state.

According to a second aspect of the present invention, there is provided a plasma display panel driving apparatus comprising: column electrode driving means for applying pixel data pulses corresponding to pixel data to a plurality of column electrodes arranged in the vertical direction of the plasma display panel; A driving device for a plasma display panel, comprising: a plurality of row electrodes arranged in a horizontal direction intersecting the column electrodes; and a row electrode driving unit that applies a pulse having a predetermined polarity and a pulse having a polarity different from the predetermined polarity. The row electrode driving means includes a first DC power source having a terminal of the same polarity as the predetermined polarity connected to a first line, a second line for applying a voltage to the row electrode, and the row electrode. A third line for discharging the voltage applied to the capacitor, a capacitor having one end grounded and the other end connected to the second line and the third line, and the second line A second coil provided on the third line, a second coil provided on the third line, a second DC power source having a terminal on the polarity side different from the predetermined polarity connected to the fourth line, and the second coil A first MOS transistor provided on one line; a second MOS transistor provided on the second line; a third MOS transistor provided on the third line; a fourth MOS transistor provided on the fourth line; A fifth MOS transistor for connecting the first line, the second line, and the third line to the row electrode in the on state; and a sixth MOS transistor for connecting the fourth line and the row electrode in the on state; And when the first MOS transistor, the second MOS transistor, or the third MOS transistor is set to an ON state, When the fifth MOS transistor is set to an on state and the sixth MOS transistor is set to an off state, when the fourth MOS transistor is set to an on state, the fifth MOS transistor is set to an off state and the sixth MOS transistor is set to an off state. It has a control circuit for setting a transistor to an on state.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 is a diagram showing an overall configuration of a plasma display apparatus including a driving apparatus according to the present invention. In FIG. 5, the A / D converter 11 samples the supplied analog video signal, converts it into N-bit pixel data for each pixel, and supplies this to the memory 13. The panel drive control circuit 12 detects the horizontal synchronization signal and the vertical synchronization signal included in the video signal, generates various signals as described below based on the detection timing, and stores them in the memory 13 and the row electrode. This is supplied to each of the driver 100 and the column electrode driver 200.

The memory 13 sequentially writes the pixel data in accordance with the write signal supplied from the panel drive control circuit 12. Further, the memory 13 reads out the pixel data written as described above for each row of the PDP (plasma display panel) 20 in accordance with the readout signal supplied from the panel drive control circuit 12, and this is read out into the column. The electrode driver 200 is supplied.

The PDP 20 is formed with row electrodes Y _{1 to} Yn and row electrodes X _{1 to} Xn that form row electrode pairs corresponding to each row (first row to nth row) of one screen by a pair of X and Y. Yes. Further, column electrodes D ₁ to D that form column electrodes corresponding to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space (not shown) perpendicular to the row electrode pairs. D _m is formed. At this time, one discharge cell is formed at the intersection of one row electrode pair (X, Y) and one column electrode D.

The column electrode driver 200 generates pixel data pulses DP ₁ to DP _m corresponding to each row of pixel data supplied from the memory 13, and outputs these pixel data pulses DP ₁ to _m supplied from the panel drive control circuit 12. In accordance with the application timing signal, as shown in FIG. 6, it is applied to each of the column electrodes D _{1 to} D _{m of the} PDP 20. The row electrode driver 100 outputs a row electrode X drive signal including a reset pulse RP _X and a sustain pulse IP _X as shown in FIG. 6 according to various timing signals supplied from the panel drive control circuit 12. It is generated and applied simultaneously to each of the row electrodes X _{1 to} X n of the PDP 20. In addition, the row electrode driver 100 responds to various timing signals supplied from the panel drive control circuit 12 as shown in FIG. 6 with the negative voltage reset pulse RP _Y , the positive voltage priming pulse PP, A row electrode Y driving signal including a voltage scanning pulse SP, a positive voltage sustaining pulse IP _Y and a negative voltage erasing pulse EP is generated and applied to each of the row electrodes Y _{1 to} Yn of the PDP 20.

FIG. 7 is a diagram showing a configuration of a pulse driving circuit based on the driving apparatus of the present invention which is used to generate each of the reset pulse RP _Y and the sustain pulse IP _Y from the various driving pulses. The configuration shown in FIG. 7 is provided in the row electrode driver 100. In FIG. 7, the p-channel MOS (Metal Oxide Semiconductor) transistor Q1 in the sustain pulse generation circuit 120 is turned off when the logic level of the gate signal GT1 supplied from the panel drive control circuit 12 is “1”. It becomes a state. On the other hand, when the logic level of the gate signal GT1 is “0”, the MOS transistor Q1 is turned on to apply the positive terminal potential of the DC power supply B1 onto the line 200. The negative terminal of the DC power supply B1 is grounded. Further, the sustain pulse generating circuit 120 is provided with a capacitor C1 whose one end is grounded. The n-channel MOS transistor Q2 is turned off when the logic level of the gate signal GT2 supplied from the panel drive control circuit 12 is "0". On the other hand, when the logic level of the gate signal GT2 is “1”, the MOS transistor Q2 is turned on and the potential on the line 200 is applied to the other end of the capacitor C1 via the diode D1 and the coil L1. Apply to charge it. The n-channel MOS transistor Q3 is turned off when the logic level of the gate signal GT3 supplied from the panel drive control circuit 12 is “0”. On the other hand, when the logic level of the gate signal GT3 is "1", the MOS transistor Q3 is turned on, and the potential discharged from the other end of the capacitor C1 is transferred to the line via the diode D2 and the coil L2. 200 applied. The p-channel MOS transistor Q4 is turned off when the logic level of the gate signal GT4 supplied from the panel drive control circuit 12 is "1", while the logic level of the gate signal GT4 is "0". In the case of "", it is turned on to pull the potential on the line 200 to the ground potential.

The n-channel MOS transistor Q5 in the reset pulse generation circuit 130 is turned off when the logic level of the gate signal GT5 supplied from the panel drive control circuit 12 is “0”. The MOS transistor Q5 is turned on when the logic level of the gate signal GT5 is “1”, and applies the potential of the negative terminal of the DC power supply B2 to the line 300 via the resistor R1. The positive terminal of the DC power supply B2 is grounded.

The p-channel type MOS transistor Q7 as a switching element is turned on when the logic level of the gate signal GT7 supplied from the panel drive control circuit 12 is "0", and between the line 200 and the line 300. Connect. At this time, the row electrode driving signal generated on the line 200 is applied to the row electrodes Y _{1 to} Y _n of the PDP 20 through the line 300. On the other hand, when the logic level of the gate signal GT7 is “1”, the MOS transistor Q7 is turned off, and the connection between the line 200 and the line 300 is cut off. At this time, only the row electrode drive signals generated on the line 300 are applied to the row electrodes Y _{1 to} Y _n of the PDP 20.

FIG. 8 is a diagram showing the timing of each of the gate signals GT1 to GT5 and GT7, and the waveform of the row electrode drive signal generated on the line 300 in accordance with these gate signals GT. FIG. 8 is a diagram showing the supply timing of each of the gate signals GT1 to GT5 and GT7 when generating the reset pulse RPy and the sustain pulse IPy as shown in FIG.

As shown in FIG. 8, first, the MOS transistor Q5 shown in FIG. 7 is turned on in response to the gate signal GT5 of the logic level “1”. As a result, a negative potential generated at the negative terminal of the DC power supply B2 is applied to the line 300 via the resistor R1, and a negative voltage reset pulse RPy as shown in FIG. 8 is applied to the row electrode Y of the PDP 20. Applied. At this time, the waveform of the front edge portion of the reset pulse RPy becomes gentle by the action of the resistor R1. During this time, since the gate signal GT7 of the logic level “1” is supplied to the MOS transistor Q7 shown in FIG. 7, the MOS transistor Q7 is in the off state. Therefore, at least during the period when the reset pulse RPy is generated, the line 200 and the line 300 are disconnected.

Next, as shown in FIG. 8, the logic level of the gate signal GT3 is “0” to “1” to “0”, the logic level of the gate signal GT1 is “1” to “0” to “1”, and When the logic level of the gate signal GT2 is sequentially switched from “0” to “1” to “0”, a sustain pulse IPy having a positive voltage as shown in FIG. 8 is generated. That is, first, the MOS transistor Q3 is turned on in response to the gate signal GT3 having the logic level “1”, and a current corresponding to the electric charge stored in the capacitor C1 passes through the MOS transistor Q3, the diode D2, and the coil L2. Flow into line 200. At this time, as shown in FIG. 8, since the gate signal GT7 of the logic level “0” is supplied to the MOS transistor Q7, the MOS transistor Q7 is in the on state, and the lines 200 and 300 are connected. As a result, the level of the row electrode driving signal on the line 300 gradually increases as shown in FIG. Next, the MOS transistor Q1 is turned on in response to the gate signal GT1 having the logic level “0”. As a result, a positive potential at the positive terminal of the DC power supply B1 is applied to the line 300 via the line 200 and the MOS transistor Q7, and a sustain pulse IPy having a positive voltage as shown in FIG. 8 is generated. Next, the MOS transistor Q2 is turned on in response to the gate signal GT2 having the logic level “1”. As a result, a current corresponding to the charge charged in the PDP 20 flows into the capacitor C1 via the MOS transistor Q2, the diode D1, and the coil L1. By the charging operation of the capacitor C1, the level of the sustain pulse IPy gradually decreases as shown in FIG.

As described above, in the pulse driving circuit shown in FIG. 7, the MOS transistor Q7 that is turned on at least during the period in which the sustain pulse is applied to the row electrode is provided between the sustain pulse generation circuit 120 and the reset pulse generation circuit 130. It was. According to this configuration, the capacitor C1 that generates substantially the same potential as the positive terminal of the DC power supply B1 and the negative terminal of the DC power supply B2 and the negative terminal of the DC power supply B2 are further negatively connected. The number of MOS transistors connected in series with each of the side terminals is increased by one stage by the amount corresponding to the MOS transistor Q7.

Therefore, the breakdown voltage per one MOS transistor can be lowered as compared with the conventional configuration as shown in FIG. Also, the MOS transistor Q7 shown in FIG. 7 is equivalent to a switch SW7 for connecting / disconnecting between the line 200 and the line 300 in accordance with the gate signal GT7 and the line 300 to the line as shown in FIG. It consists of a parasitic diode D17 formed in the forward direction toward 200.

At this time, the parasitic diode D17 prevents a current flowing backward from the ground potential to the negative terminal of the DC power supply B2 of the sustain pulse generating circuit 120 via the parasitic diode of the MOS transistor Q4. That is, the backflow prevention diode D3 employed in the configuration shown in FIG. 3 to perform such a role is not necessary in the configuration shown in FIG.

In the above embodiment, the MOS transistor Q7 which is turned on at least during the period of generating the sustain pulse is provided in the line 200 as the output line of the sustain pulse generating circuit 120 in order to improve the breakdown voltage. A configuration may be employed in which a MOS transistor is provided in each output line of each pulse generation circuit to improve the breakdown voltage.

FIG. 10 is a diagram showing a configuration of a pulse driving circuit made in view of such points. Since sustain pulse generation circuit 120 and MOS transistor Q7 shown in FIG. 10 are the same as those shown in FIG. 7 as described above, description thereof will be omitted. In FIG. 10, the n-channel MOS transistor Q5 in the reset pulse generation circuit 140 is turned off when the logic level of the gate signal GT5 supplied from the panel drive control circuit 12 is “0”. The MOS transistor Q5 is turned on when the logic level of the gate signal GT5 is “1”, and applies the potential of the negative terminal of the DC power supply B2 to the line 400 via the resistor R1. The positive terminal of the DC power supply B2 is grounded. Further, the n-channel MOS transistor Q8 in the reset pulse generation circuit 140 is turned off when the logic level of the gate signal GT8 supplied from the panel drive control circuit 12 is "0". The MOS transistor Q8 is turned on when the logic level of the gate signal GT8 is "1", and pulls the potential on the line 400 to the ground potential via the resistor R2.

The n-channel MOS transistor Q9 as a switching element is turned on when the logic level of the gate signal GT9 supplied from the panel drive control circuit 12 is "1", and is between the line 400 and the line 300. Connect. At this time, the row electrode driving signal generated on the line 400 is applied to the row electrodes Y _{1 to} Y _n of the PDP 20 through the line 300. On the other hand, when the logic level of the gate signal GT9 is “0”, the MOS transistor Q9 is turned off, and the connection between the line 400 and the line 300 is cut off.

FIG. 11 is a diagram showing supply timings of the gate signals GT1 to GT5 and the gate signals GT7 to GT9 for generating the reset pulse RPy and the sustain pulse IPy in the configuration shown in FIG. As shown in FIG. 11, first, the MOS transistor Q5 in the reset pulse generation circuit 140 shown in FIG. 10 is turned on in response to the gate signal GT5 of the logic level “1”. As a result, a negative potential generated at the negative terminal of the DC power supply B2 is applied to the line 400 via the MOS transistor Q5 and the resistor R1. During this time, since the gate signal GT9 of the logic level “1” is supplied to the MOS transistor Q9 shown in FIG. 10, the MOS transistor Q9 is in the ON state. Therefore, the potential applied on 400 is applied to the line 300 via the MOS transistor Q9, and a negative voltage reset pulse RPy as shown in FIG. 11 is applied to the row electrode Y of the PDP 20. . Here, as shown in FIG. 11, when the logic level of the gate signal GT5 is switched from “1” to “0” and the logic level of the gate signal GT8 is switched from “0” to “1”, the MOS transistor Q5 is turned off. The MOS transistor Q8 is turned on. When the MOS transistor Q8 is turned on, the negative voltage reset pulse RPy generated on the line 300 as shown in FIG. 11 is gradually drawn to the ground potential.

During the period when the reset pulse RPy is applied to the row electrode Y of the PDP 20 via the line 400, the MOS transistor Q9, and the line 300, the gate signal GT7 having the logic level “1” is supplied to the MOS transistor Q7. Yes. Therefore, during this time, the lines 200 and 300 as output lines of the sustain pulse generation circuit 120 are disconnected.

Next, as shown in FIG. 11, the logic level of the gate signal GT3 is “0” to “1” to “0”, the logic level of the gate signal GT1 is “1” to “0” to “1”, and When the logic level of the gate signal GT2 is sequentially switched from “0” to “1” to “0”, a sustain pulse IPy having a positive voltage as shown in FIG. 11 is generated. That is, first, the MOS transistor Q3 is turned on in response to the gate signal GT3 having the logic level “1”, and a current corresponding to the electric charge stored in the capacitor C1 passes through the MOS transistor Q3, the diode D2, and the coil L2. Flow into line 200. At this time, as shown in FIG. 11, since the gate signal GT7 of the logic level “0” is supplied to the MOS transistor Q7, the MOS transistor Q7 is in the on state and the lines 200 and 300 are connected. As a result, the level of the row electrode driving signal on the line 300 gradually increases as shown in FIG. Next, the MOS transistor Q1 is turned on in response to the gate signal GT1 having the logic level “0”. As a result, a positive potential at the positive terminal of the DC power supply B1 is applied to the line 300 via the line 200 and the MOS transistor Q7, and a sustain pulse IPy having a positive voltage as shown in FIG. 11 is generated. Next, the MOS transistor Q2 is turned on in response to the gate signal GT2 having the logic level “1”. As a result, a current corresponding to the charge charged in the PDP 20 flows into the capacitor C1 via the MOS transistor Q2, the diode D1, and the coil L1. Due to the charging operation of the capacitor C1, the level of the sustain pulse IPy gradually decreases as shown in FIG. During the period in which the sustain pulse IPy is applied to the row electrode Y of the PDP 20 via the line 200, the MOS transistor Q7, and the line 300, the gate signal GT9 having the logic level “0” is supplied to the MOS transistor Q9. Yes. Therefore, during this time, the line 400 as the output line of the reset pulse generation circuit 140 and the line 300 are disconnected.

In the pulse driving circuit shown in FIG. 10, the MOS transistors (Q7, Q7) that are turned on at least during the period in which each pulse generating circuit generates a driving pulse are connected to each output line of each pulse generating circuit (120, 140). Q9) is provided. Therefore, according to such a configuration, the number of MOS transistors connected in series between the pulse generation circuits is further increased by one (for the MOS transistor Q9), and the breakdown voltage of each MOS transistor is shown in FIG. It becomes possible to set a lower one than the configuration.

It is a figure which shows schematic structure of a plasma display apparatus. It is a figure which shows the timing of the row electrode drive signal by the drive device of FIG. Is a diagram showing a configuration of a conventional pulse drive circuit for generating a reset pulse RP _Y and the sustain pulse IP _Y. It is a figure which shows the timing of each gate signal at the time of generating each of reset pulse RPy and sustain pulse IPy by the conventional pulse drive circuit. It is a figure which shows the whole structure of the plasma display apparatus containing the drive device by this invention. It is a figure which shows the timing of the row electrode drive signal by the drive device of FIG. It is a figure which shows the structure of the pulse drive circuit based on the drive device of this invention. It is a figure which shows the timing of each gate signal at the time of generating each of reset pulse RPy and sustain pulse IPy by the pulse drive circuit shown by FIG. It is a figure which shows the structure of the pulse drive circuit based on this invention which has shown MOS transistor Q7 by the equivalent circuit. It is a figure which shows the other structural example of the pulse drive circuit based on the drive device of this invention. FIG. 11 is a diagram illustrating the timing of each gate signal when the reset pulse RPy and the sustain pulse IPy are generated by the pulse driving circuit shown in FIG. 10.

Explanation of symbols

20 PDP
100 row electrode driver 120 sustain pulse generating circuit 130, 140 reset pulse generating circuit
Q7, Q9 MOS transistor

Claims (5)

Column electrode driving means for applying pixel data pulses corresponding to pixel data to a plurality of column electrodes arranged in the vertical direction of the plasma display panel, and a plurality of row electrodes arranged in a horizontal direction intersecting the column electrodes A driving device for a plasma display panel, comprising: a polarity pulse; and a row electrode driving means for applying a reset pulse having a polarity different from the predetermined polarity for generating charged particles in all discharge cells of the plasma display panel. And
The row electrode driving means includes a first DC power source in which a terminal on the same polarity side as the predetermined polarity is connected to a first line;
A second line for applying a voltage to the row electrode;
A third line for discharging the voltage applied to the row electrode;
A capacitor having one end grounded and the other end connected to the second line and the third line;
A first coil provided in the second line;
A second coil provided in the third line;
A second DC power source in which a terminal on the polarity side different from the predetermined polarity is connected to the fourth line;
A first MOS transistor provided in the first line;
A second MOS transistor provided in the second line;
A third MOS transistor provided in the third line;
A fourth MOS transistor provided in the fourth line;
A fifth MOS transistor that connects the first line, the second line, and the third line and the row electrode in an on state,
The second DC power supply and the fourth MOS transistor constitute reset pulse generating means for applying the reset pulse to the row electrode when the fourth MOS transistor is in an ON state,
When the first MOS transistor, the second MOS transistor, or the third MOS transistor is set to an on state, the fifth MOS transistor is set to an on state and the fourth MOS transistor is set to an off state, while the reset is performed. A plasma display panel driving apparatus comprising: a control circuit for setting the fifth MOS transistor to an off state when the pulse generating means applies the reset pulse to the row electrode. The pulse having the predetermined polarity is a sustain pulse for maintaining a light emission state of a discharge cell of the plasma display panel, and the first DC power source, the capacitor, the first coil, the second coil, the first MOS transistor, the first MOS transistor, 2. The plasma display panel according to claim 1, wherein the 2MOS transistor and the third MOS transistor constitute a sustain pulse generating circuit that applies the sustain pulse to the row electrode when the fifth MOS transistor is in an ON state. Drive device. Column electrode driving means for applying pixel data pulses corresponding to pixel data to a plurality of column electrodes arranged in a vertical direction of the plasma display panel, and a plurality of row electrodes arranged in a horizontal direction intersecting the column electrodes A plasma display panel driving apparatus comprising: a polarity pulse; and a row electrode driving means for applying a pulse having a polarity different from the predetermined polarity.
The row electrode driving means includes a first DC power source in which a terminal on the same polarity side as the predetermined polarity is connected to a first line;
A second line for applying a voltage to the row electrode;
A third line for discharging the voltage applied to the row electrode;
A capacitor having one end grounded and the other end connected to the second line and the third line;
A first coil provided in the second line;
A second coil provided in the third line;
A second DC power source in which a terminal on the polarity side different from the predetermined polarity is connected to the fourth line;
A first MOS transistor provided in the first line;
A second MOS transistor provided in the second line;
A third MOS transistor provided in the third line;
A fourth MOS transistor provided in the fourth line;
A fifth MOS transistor for connecting the first line, the second line, and the third line to the row electrode in an on state;
A sixth MOS transistor for connecting the fourth line and the row electrode in an on state,
When the first MOS transistor, the second MOS transistor, or the third MOS transistor is set to an on state, the fifth MOS transistor is set to an on state and the sixth MOS transistor is set to an off state. A driving device for a plasma display panel, comprising: a control circuit for setting the fifth MOS transistor to an off state and setting the sixth MOS transistor to an on state when the 4MOS transistor is set to an on state. The pulse having a polarity different from the predetermined polarity is a reset pulse for generating charged particles in all discharge cells of the plasma display panel, and the second DC power source and the fourth MOS transistor are in the on state. 4. The driving device of the plasma display panel according to claim 3, wherein reset pulse generating means for applying the reset pulse to the row electrodes is sometimes configured. The pulse having the predetermined polarity is a sustain pulse for maintaining a light emission state of a discharge cell of the plasma display panel, and the first DC power source, the capacitor, the first coil, the second coil, the first MOS transistor, the first MOS transistor, 4. The plasma display panel according to claim 3, wherein the 2MOS transistor and the third MOS transistor constitute a sustain pulse generating circuit that applies the sustain pulse to the row electrode when the fifth MOS transistor is in an ON state. Drive device.

Images