JP3684562B2 - Data receiving apparatus and method - Google Patents

Description

【０１４２】
ここで、Ｐ（Ｓ_j∩Ｒ）は、シンボルＳ_jが送信され、受信信号Ｒが受信される確率を表し、ΣＰ（Ｓ_j∩Ｒ）は、ｉ番目のビットが０であるすべてのシンボルＳ_jについての確率Ｐ（Ｓ_j∩Ｒ）の和を表している。
【０１４３】
一方、Ｐ（Ｓ_k∩Ｒ）は、シンボルＳ_kが送信され、受信信号Ｒが受信される確率を表し、ΣＰ（Ｓ_k∩Ｒ）は、１６ＱＡＭで定義されるすべてのシンボルＳ_kについての確率Ｐ（Ｓ_k∩Ｒ）の和を表している。
【０１４４】
図４の、第１のビットに対するメトリック（Ｐ（ｂ１＝０｜Ｒ））のメトリック計算回路１０２−１において、確率計算回路１１１−１は、Ｐ（Ｓ００００∩Ｒ）、すなわち、１６ＱＡＭの００００に対応するシンボルＳ００００が送信され、受信信号Ｒを受信する確率を計算する。
【０１４５】
確率計算回路１１１−２は、Ｐ（Ｓ０００１∩Ｒ）、すなわち、１６ＱＡＭの０００１に対応するシンボルＳ０００１が送信され、受信信号Ｒを受信する確率を計算する。
【０１４６】
確率計算回路１１１−３は、Ｐ（Ｓ００１０∩Ｒ）、すなわち、１６ＱＡＭの００１０に対応するシンボルＳ００１０が送信され、受信信号Ｒを受信する確率を計算する。
【０１４７】
以下、同様にして、１６ＱＡＭの残りのシンボルに対しても、それぞれ確率を計算し、全部で１６個の確率の計算結果を得る。
【０１４８】
加算回路１１２は、式（８）の分子を計算する回路で、第１のビットが０のシンボル、すなわち、
Ｓ００００、Ｓ０００１、Ｓ００１０、Ｓ００１１、
Ｓ０１００、Ｓ０１０１、Ｓ０１１０、Ｓ０１１１、
に対する確率の和を求める。
【０１４９】
加算回路１１３は、式（８）の分母を計算するブロックで、１６ＱＡＭすべてのシンボル、すなわち、
Ｓ００００、Ｓ０００１、Ｓ００１０、Ｓ００１１、
Ｓ０１００、Ｓ０１０１、Ｓ０１１０、Ｓ０１１１、
Ｓ１０００、Ｓ１００１、Ｓ１０１０、Ｓ１０１１、
Ｓ１１００、Ｓ１１０１、Ｓ１１１０、Ｓ１１１１、
に対する確率の和を求める。
【０１５０】
割算回路１１４は、加算回路１１２の出力を加算回路１１３の出力で割り算する計算器であり、式（８）を計算する。
【０１５１】
第２のビットに対するメトリックの計算も同様に行うことができる。すなわち、第２のビットに対するメトリックは、メトリック計算回路１０２−２において計算される。そこでは、式（８）の分子を計算する加算回路１１２に対応するメトリック計算回路１０２−２の加算回路（図示せず）への入力として、各々のシンボルに対する確率の計算結果の中から、第２のビットが０であるすべてのシンボル、すなわち、
Ｓ００００、Ｓ０００１、Ｓ００１０、Ｓ００１１、
Ｓ１０００、Ｓ１００１、Ｓ１０１０、Ｓ１０１１、
に対する確率の計算結果を選択し、加算を行う。式（８）の分母を計算する加算回路１１３に対応するメトリック計算回路１０２−２の加算回路（図示せず）への入力として、前述の第１のビットに対する場合と同様に、すべてのシンボル、すなわち、
Ｓ００００、Ｓ０００１、Ｓ００１０、Ｓ００１１、
Ｓ０１００、Ｓ０１０１、Ｓ０１１０、Ｓ０１１１、
Ｓ１０００、Ｓ１００１、Ｓ１０１０、Ｓ１０１１、
Ｓ１１００、Ｓ１１０１、Ｓ１１１０、Ｓ１１１１、
に対する確率の計算結果を選択し、加算を行う。
【０１５２】
第３のビットと第４のビットに関しても同様の演算が行われる。
【０１５３】
各々のメトリック計算回路１０２−１乃至１０２−４の演算結果ｕ，ｖ，ｘ，ｙは、ビタビ復号器１０３に供給される。
【０１５４】
図６に示す乗算回路１４１−１では、メトリックｕ，ｖ，ｘ，ｙ（第１乃至第４ビット目が０である確率）の積を計算し、ブランチメトリックＢＭ００００として出力する。このブランチメトリックＢＭ００００は、畳み込み符号化器２の符号出力００００に対応している。
【０１５５】
同様にして、乗算回路１４１−２は、メトリックｕ，ｖ，ｘ（第１乃至第３ビット目が０である確率）と、メトリックｙ’（第４ビット目が１である確率）との積を計算し、ブランチメトリックＢＭ０００１として出力する。このブランチメトリックＢＭ０００１は、畳み込み符号化器２の符号出力０００１に対応している。
【０１５６】
乗算回路１４１−３は、メトリックｕ，ｖ，ｙ（第１ビット目、第２ビット目、第４ビット目が０である確率）と、メトリックｘ’（第３ビット目が１である確率）の積を計算し、ブランチメトリックＢＭ００１０として出力する。このブランチメトリックＢＭ００１０は、畳み込み符号化器２の符号出力００１０に対応している。同様にして、乗算回路１４１−８は、メトリックｕ’，ｖ’，ｘ’，ｙ’（第１ビット目乃至第４ビット目が１である確率）の積を計算し、ブランチメトリックＢＭ１１１１として出力する。このブランチメトリックＢＭ１１１１は、畳み込み符号化器２の符号化出力１１１１に対応している。
【０１５７】
ＡＣＳ回路１４２−１は、畳み込み符号化器２の状態遷移（図３）に従って、次の２つの式の計算を行う。
ＳＭ０００×ＢＭ００００ （９）
ＳＭ００１×ＢＭ１１１１ （１０）
【０１５８】
ここでＳＭ０００は、１単位時間前のステートメトリック記憶装置１４３−１の値、ＳＭ００１は、１単位時間前のステートメトリック記憶装置１４３−２の値、ＢＭ００００は、乗算回路１４１−１の演算結果、ＢＭ１１１１は、乗算回路１４１−８の演算結果をそれぞれ表している。
【０１５９】
そして、ＡＣＳ回路１４２−１は、尤度の大きい方、すなわち、上記（９）式と（１０）式のうち、計算結果の大きい方を選択し、その選択情報ＳＥＬ０００を後段のパスメモリ１４４に出力するとともに、式（９）と式（１０）を計算して得られた結果のうち大きい方を、後段のステートメトリック記憶装置１４３−１に供給し、記憶させる。すなわち式（９）の計算結果の方が大きければ、ＳＥＬ０００＝０とし、式（１０）の計算結果の方が大きければ、ＳＥＬ０００＝１とする。また、前者の場合、ＳＭ０００×ＢＭ００００が、後者の場合、ＳＭ００１×ＢＭ１１１１が、それぞれステートメトリック記憶装置１４３−１に、新たなステートメトリックＳＭ０００として記憶される。
【０１６０】
この計算を図３にそって説明する。状態０００に到達するパスは２本あり、１本目は状態０００で０が入力され、００００を出力するパスで、比較される計算式は式（９）のようになり、２本目は状態００１で０が入力され、１１１１を出力するパスで、比較される計算式は式（１０）のようになる。計算結果のうち大きい方が新たなステートメトリックＳＭ０００としてステートメトリック記憶装置１４３−１に供給される。
【０１６１】
同様の動作が、ＡＣＳ回路１４２−２乃至１４２−８においても行われる。なお、ステートメトリック記憶装置１４３−１乃至１４３−８は、システムが動作する初期段階で０にリセットされる。この制御は図には示していない制御装置から端子６１を介して行われる。
【０１６２】
パスメモリ１４４では、図３の状態遷移図に従って、ＡＣＳ回路１４２−１乃至１４２−８からの選択情報ＳＥＬ０００乃至ＳＥＬ１１１を用いて、入力データすなわち復号データの選択、記憶、伝搬を行う。
【０１６３】
次に、図７を参照して、パスメモリ１４４の動作を説明する。
【０１６４】
ＡＣＳ回路１４２−１乃至１４２−８より出力された選択情報ＳＥＬ０００乃至ＳＥＬ１１１は、端子１５０−１乃至１５０−８に入力され、各列のセレクタに制御信号として供給される。
【０１６５】
第１列目のセレクタ１５１−１乃至１５１−４には、２つの入力として０が入力されており、また、セレクタ１５１−５乃至１５１−８には、２つの入力として１が入力されている。従って、セレクタ１５１−１乃至１５１−４からは、選択情報の状態に拘わらず、０が出力され、また、セレクタ１５１−５乃至１５１−８からは、１が出力される。このような構成は、図３に示すように、状態０００乃至状態０１１に至るパスでは、全て０が入力され、また、状態１００乃至状態１１１に至るパスでは全て１が入力されていることに対応している。
【０１６６】
セレクタ１５１−１乃至１５１−８より出力されたデータは、後段のレジスタ１５２−１乃至１５２−８に供給され、記憶された後、出力される。
【０１６７】
レジスタ１５２−１乃至１５２−８から出力されたデータは、第２列目のセレクタ１５３−１乃至１５３−８に供給される。すなわち、セレクタ１５３−１には、前列のレジスタ１５２−１の出力とレジスタ１５２−２の出力が供給され、セレクタ１５３−２には、レジスタ１５２−３の出力とレジスタ１５２−４の出力が入力され、セレクタ１５３−３には、レジスタ１５２−５の出力とレジスタ１５２−６の出力が入力され、セレクタ１５３−８には、レジスタ１５２−７の出力とレジスタ１５２−８の出力が入力されている。セレクタ１５３−４乃至１５３−７は、前述の通りである。
【０１６８】
各セレクタ１５３−１乃至１５３−８は、選択情報ＳＥＬ０００乃至ＳＥＬ１１１の状態に応じて、２入力のうちの一方を選択し、後段のレジスタ１５４−１乃至１５４−８に出力する。例えば、選択情報ＳＥＬ０００が０である場合には、セレクタ１５３−１は、レジスタ１５２−１の出力を選択し、また、選択情報ＳＥＬ０００が１である場合には、レジスタ１５２−２の出力を選択し、出力する。
【０１６９】
第３列目および最終列のレジスタにおいても同様の処理が施され、選択情報ＳＥＬ０００乃至ＳＥＬ１１１の状態に応じて、前段からの２つの入力のうちの何れかが選択され、後段のレジスタに出力される。
【０１７０】
最終列のレジスタ１５８−１乃至１５８−８から出力されたデータは、セレクタ１５９に入力される。セレクタ１５９は、最小値比較回路１６０からの出力に応じてレジスタ１５８−１乃至１５８−８から出力されるデータの何れかを選択し、出力する。すなわち、最小値比較回路１６０は、図６に示すステートメトリック記憶回路１４３−１乃至１４３−８から出力されるステートメトリックＳＭ０００乃至ＳＭ１１１のうち、最小のステートメトリックを選択し、対応するデータを出力する。たとえば、ステートメトリックＳＭ０００が最小であった場合は、データ０００を出力する。セレクタ１５９は、最小値比較回路１６０から出力されるデータに応じてレジスタ１５８−１乃至１５８−８の何れかの出力を選択して出力する。例えば、最小値比較回路１６０からの出力データが０００であるとき、セレクタ１５９は、レジスタ１５８−１の出力を選択して出力する。出力データが００１乃至１１１の場合は、それぞれ、レジスタ１５８−２乃至１５８−８が選択されることになる。
【０１７１】
換言すると、パスメモリ１４４では、記憶された８つの復号データから、最も尤度の大きいパスに対応するデータが最終的な復号データとして出力される。「最も尤度の大きいパス」とは、８つのステートメトリックＳＭ０００乃至ＳＭ１１１のうち、最小の値を持つものに対応するパスであり、セレクタ１５９で、その時点におけるステートメトリックの最小値に対応するパス、すなわち、最も尤度の大きいパスが選択される。
【０１７２】
なお、図５において、確率計算回路１１１−１乃至１１１−１６における計算方法として、伝送路によって様々な計算法が考えられるが、ガウス伝送路を仮定した場合には、例えば、確率計算回路１１１−１において、以下のように確率を計算することができる。

【０１７３】
ここで、σは伝送路の雑音電力の１／２の平方根を表す。すなわち、２σ²が伝送路の雑音電力を表す。||Ｓ００００−Ｒ||は、シンボルＳ００００とＲとのユークリッド距離である。
【０１７４】
確率計算回路１１１−２乃至１１１−１６においても、同様にして、確率を計算することができる。
【０１７５】
図８は、データ受信装置の第２の実施例を表している。この実施例においては、図４における場合と比較して、ビット逆拡散回路とメトリック計算回路の順序が逆になっている。その他の構成は図４の場合と同様である。
【０１７６】
シンボル逆拡散回路３３より出力された受信信号のＩ’およびＱ’成分は、メトリック計算回路１２０に入力され、メトリックの計算が実行された後、メトリックデータｕ’，ｖ’，ｘ’，ｙ’としてビット逆拡散回路９５−１乃至９５−８にそれぞれ供給される。ビット逆拡散回路９５−１乃至９５−８は、図１に示すビット拡散回路９１−１乃至９１−８における場合と逆の操作を実行し、ビットの逆拡散を行う。
【０１７７】
その他の構成は、図４における場合と同様である。
【０１７８】
次に、その動作について説明する。この実施例においては、シンボル逆拡散回路３３より出力された受信信号のＩ’とＱ’成分は、メトリック計算回路１２０に入力され、それぞれ第１乃至第４のビットに対応するメトリックが計算されるようになされている。
【０１７９】
すなわち、図８のメトリック計算回路１２０は、例えば図９に示すように構成される。この実施例においては、確率計算回路１１１−１乃至１１１−１６に、シンボル逆拡散回路３３より出力されたＩ’とＱ’成分が入力されている。加算回路１１２−１乃至１１２−８は、上記した式（８）の分子を計算する回路であり、加算回路１１２−１は、第１のビットの０のシンボルに対する確率の和を計算し、加算回路１１２−２乃至１１２−８は、それぞれ第２乃至第３のビットの０のシンボルの確率の和を計算する。加算回路１１３は、上記した式の分母を計算する回路であり、１６ＱＡＭすべてのシンボルに対する確率の和を計算する。割算回路１１４−１乃至１１４−８は、それぞれ加算回路１１２−１乃至１１２−８の出力を加算回路１１３の出力で割り算し、それぞれ第１のビット乃至第４のビットに対するメトリックの計算を行い、それぞれ、出力信号ｕ’，ｖ’，ｘ’，ｙ’として出力する。
【０１８０】
メトリック計算回路１２０より出力されたデータ（メトリック）ｕ’，ｖ’，ｘ’，ｙ’は、ビット逆拡散回路９５−１乃至９５−８にそれぞれ供給される。ビット逆拡散回路９５−１乃至９５−８は、メトリック計算回路１２０から出力されたメトリックデータｕ’，ｖ’，ｘ’，ｙ’に対して、図１のビット拡散回路９１−１乃至９１−８における場合と逆の操作によりビット逆拡散を実行し、データｕ，ｖ，ｘ，ｙを出力する。
【０１８１】
図８の実施例のその他の動作は、図４における場合と同様である。
【０１８２】
図１０は、データ受信装置の第３の実施例を表している。この実施例においては、復調回路３２から出力された受信信号のＩ成分とＱ成分は、メトリック計算回路１２０に供給され、メトリックの計算が実行されて得られたメトリックデータｕ’，ｖ’，ｘ’，ｙ’がシンボル逆拡散回路１４０に対して出力される。シンボル逆拡散回路１４０は、図１のシンボル拡散回路７におけるシンボル拡散処理と逆の処理、すなわち、シンボル拡散回路７において入れ替えたシンボルの順番を元の順番に戻す処理を行い、出力データｕ’’，ｖ’’，ｘ’’，ｙ’’を出力する。
【０１８３】
シンボル逆拡散器１４０が出力したデータｕ’’，ｖ’’，ｘ’’，ｙ’’は、ビット逆拡散回路９５−１乃至９５−８に供給され、図１のビット拡散回路９１−１乃至９１−８における場合と逆の処理が実行され、得られたデータｕ，ｖ，ｘ，ｙが出力される。その他の構成は、図８における場合と同様であるので、その説明は省略する。
【０１８４】
次に、その動作について説明する。
【０１８５】
復調器３２から出力された受信信号のＩ成分とＱ成分は、メトリック計算回路１２０に供給される。メトリック計算回路１２０では、入力されたＩ成分とＱ成分から、１６ＱＡＭを構成する第１乃至第４のビットに対するメトリックをそれぞれ計算し、
第１のビットに対するメトリックをｕ’、
第２のビットに対するメトリックをｖ’、
第３のビットに対するメトリックをｘ’、
第４のビットに対するメトリックをｙ’
として出力する。
【０１８６】
このメトリック計算回路１２０は、図８（図９）におけるメトリック計算回路１２０と同様の構成とされている。
【０１８７】
１６ＱＡＭを構成する第１乃至第４のビットに対するメトリックの計算結果ｕ’，ｖ’，ｘ’，ｙ’は、シンボル逆拡散回路１４０に入力される。
【０１８８】
シンボル逆拡散回路１４０では、図１に示すシンボル拡散回路７における場合と逆の操作が実行され、シンボルの逆拡散が行われる。即ち、逆拡散は、Ｓｉ（ｕ’，ｖ’，ｘ’，ｙ’）を１つの組として、図１に示すシンボル拡散回路７に対応する、（Ｎ−１）組のＳｉデータを要素とするベクトル
（Ｓ１，Ｓ２，・・・，Ｓｎ，・・・，ＳＮ−１）から、
Ｓ’ｉ（ｕ’’，ｖ’’，ｘ’’，ｙ’’）を１つの組として、（Ｎ−１）組のＳ’ｉを要素とする逆拡散後のベクトル
（Ｓ’１，Ｓ’２，・・・，Ｓ’ｋ，・・・，Ｓ’Ｎ−１）への置換となる。
【０１８９】
なお、このとき、Ｓｎ＝Ｓ’ｋ（ｎ＝Ｇ＾ｋ ｍｏｄ Ｎ）である。
【０１９０】
そして、得られたデータｕ’’，ｖ’’，ｘ’’，ｙ’’は、ビット逆拡散回路９５−１乃至９５−８にそれぞれ供給される。
【０１９１】
ビット逆拡散回路９５−１乃至９５−８は、図１のビット拡散回路９１−１乃至９１−８の場合と逆の操作により、ビットの逆拡散を行い、得られたデータｕ，ｖ，ｘ，ｙをビタビ復号器１０３に対して出力する。
【０１９２】
その後の処理は、図４における場合と同様である。
【０１９３】
以上のように、いずれの実施例においても、データのビット毎にビットに対するメトリックを計算し、データのビットに対して予め定められている規則に従って、ビット挿入処理を行うようにしたので、誤り訂正符号として畳み込み符号が用いられ、符号系列に対してビット拡散が行われ、かつ、１６ＱＡＭ方式でデータ変調して伝送されたデータを軟判定処理することができ、その結果、受信したデータを座標上最も近いシンボルとして硬判定処理する場合に較べて、正確に復号処理を行うことができる。
【０１９４】
なお、以上の実施例では、ビタビ復号器１０３として、図６に示すように乗算回路１４１−１乃至１４１−８を備える構成を用いたが、これらの乗算回路１４１−１乃至１４１−８を、例えば、入力データのｌｏｇを演算し、得られた値に（−１）を乗算するような構成とすることも可能である。
【０１９５】
上記実施例においては、１６ＱＡＭ方式でデータを変調し、復調するようにしたが、このほか、６４ＱＡＭ、２５６ＱＡＭなどの、Ｉ成分とＱ成分が、それぞれ２以上のビットに対応する多値多位相変調方式を採用する場合においても、本発明は適用することが可能である。
【０１９６】
【発明の効果】
第１の本願発明によれば、多値多位相方式でデジタル変調されて伝送されたデータを確実に復号することができる。
【０１９７】
第２の本願発明によれば、データ受信装置の構成を簡単なものにすることができる。
【図面の簡単な説明】
【図１】データ送信装置の構成例を示すブロック図である。
【図２】図１に示す畳み込み符号化器２の詳細な構成の一例を示すブロック図である。
【図３】図２に示す畳み込み符号化器２の状態の変遷を示す図である。
【図４】本発明のデータ受信装置の第１の実施例の構成を示すブロック図である。
【図５】図４に示すメトリック計算回路の詳細な構成例を示すブロック図である。
【図６】図４に示すビタビ復号器の詳細な構成例を示すブロック図である。
【図７】図６に示すパスメモリ１４４の詳細な構成例を示すブロック図である。
【図８】本発明のデータ受信装置の第２の実施例の構成を示すブロック図である。
【図９】図８に示すメトリック計算回路の詳細な構成例を示すブロック図である。
【図１０】本発明のデータ受信装置の第３の実施例の構成を示すブロック図である。
【図１１】従来のデータ送信装置の構成例を示すブロック図である。
【図１２】図１１の畳み込み符号化器の構成例を示すブロック図である。
【図１３】図１２の畳み込み符号化器の状態遷移を説明する図である。
【図１４】ＱＰＳＫの信号点配置を説明する図である。
【図１５】従来のデータ受信装置の構成例を示すブロック図である。
【図１６】図１５のビタビ復号器の構成例を示すブロック図である。
【図１７】図１６のブランチメトリック演算回路の構成例を示すブロック図である。
【図１８】図１６のパスメモリの構成例を示すブロック図である。
【図１９】１６ＱＡＭを用いた場合のデータ送信装置の構成例を示すブロック図である。
【図２０】１６ＱＡＭの信号点配置を説明する図である。
【図２１】図１９の装置で送信したデータを受信するデータ受信装置の構成例を示す図である。
【図２２】図２１の実施例の動作を説明する図である。
【符号の説明】
３２ 復調器， ３３ シンボル逆拡散回路， ３８ 再生情報， １０１−１乃至１０１−４ ビット逆拡散回路， １０２−１乃至１０２−４ メトリック計算回路， １０３ ビタビ復号器， １１１−１乃至１１１−１６ 確率計算回路， １１２，１１３ 加算回路， １１４ 割算回路[0001]
BACKGROUND OF THE INVENTION
TECHNICAL FIELD The present invention relates to a data receiving apparatus and method, and in particular, a punctured code is used as an error correction code, bit spreading is performed on a code sequence, and digital modulation is performed using a multi-value multiphase system. The present invention relates to a data receiving apparatus and method capable of receiving and decoding received data.
[0002]
[Prior art]
In the United States, digital broadcasting has already started. In Europe, a standardization organization Digital Video Broadcasting (DVB) has been formed to introduce digital television broadcasting, and the standard system is being compiled. This digital broadcasting is introduced, for example, in Nikkei Electronics 1996.1.15 (no. 653) pages 139 to 151 as “Digital broadcasting, Europe will be put into practical use after the United States”.
[0003]
When performing digital broadcasting, it is desirable to reduce the power consumption as much as possible. In such a communication channel with severe power limitation, generally, an error correction code is used to obtain a coding gain to reduce power. In such a system, error correction coding is generally performed on the transmission side, and error correction decoding is performed on the reception side. In particular, a convolutional code is advantageous in a communication channel with a small signal power to noise power ratio (C / N ratio), and this code can easily perform soft decision decoding by using the Viterbi decoding method. Gain can be obtained.
[0004]
Further, there is known a punctured code that can easily realize a plurality of coding rates using the same decoder by thinning out a code output sequence of a convolutional encoder according to a certain rule. Further, by spreading the code output sequence of the punctured encoder for each bit according to a certain rule, it is possible to improve resistance to noise superimposed on the transmission path.
[0005]
FIG. 11 shows a configuration example of a transmission apparatus proposed in the standard DVB-T for DVB terrestrial television broadcasting. In this apparatus, a punctured convolutional code, bit spreading, and a QPSK modulation method are used.
[0006]
In other words, in the example of FIG. 11, the 1-bit serial data output from the information source 1 is input to the convolutional encoder 2 to generate punctured code mother code sequences X and Y. In this example, the coding rate is ½. X and Y each represent a 1-bit code sequence.
[0007]
The code sequences X and Y are input to the bit erasure circuit 3 so that bit erasure processing is performed according to a predetermined rule. The serialized punctured code sequence output from the bit erasure circuit 3 is input to the serial / parallel converter 4 so as to be converted from one series of data to two series of data.
[0008]
The two series of data x and y output from the serial / parallel converter 4 are input to the bit spreading circuits 5-1 and 5-2, respectively, so that bit spreading processing is performed in which the order of bits is spread (interlaced). Has been made. Bit spread data x 'and y' output from the bit spreading circuits 5-1 and 5-2 are input to the signal point assignment circuit 6 and assigned to symbols on the transmission path. The signal point assignment circuit 6 outputs coordinate data I ′ and Q ′ of signal points represented by an in-phase component (I component) and a quadrature component (Q component) that are orthogonal to each other.
[0009]
The symbol spreading circuit 7 executes symbol spreading processing for spreading the order of symbols defined by the coordinate data I ′ and Q ′ output from the signal point assigning circuit 6, and obtains the I and Q components of the spread symbols. Output. The modulator 8 is configured to digitally modulate the I component and the Q component by, for example, an OFDM (Orthogonal Frequency Division Multiplex) method, and output the radio wave via the antenna 9.
[0010]
FIG. 12 illustrates a configuration example of the convolutional encoder 2. However, this configuration example is not defined by DVB-T, and shows a principle configuration for explaining the convolution process. In this example, 1-bit serial data output from the information source 1 is input from the terminal 21, and sequentially delayed by one clock by the delay circuits 22 and 23, and then output to the adder circuits 24 and 25. ing. The adder circuit 24 is also supplied with the output of the terminal 21 and the output of the delay circuit 22. The adder circuit 24 adds these data (exclusive OR operation) and then outputs the data X from the terminal 26. It is designed to output. The adder circuit 25 adds the output of the terminal 21 and the output of the delay circuit 23 (exclusive OR operation) and outputs the result as data Y from the terminal 27.
[0011]
That is, in this embodiment, for a 1-bit input, a 2-bit mother code determined from the internal state of the delay circuits 22 and 23 is output. In this example, the constraint length is 3, the internal delay element is 2, the number of states is 4, and the coding rate is 1/2.
[0012]
FIG. 13 shows a state transition diagram of the convolutional encoder 2. The state transition of the convolutional encoder 2 is as follows.
[0013]
That is, for example, when 0 is input from the terminal 21 in the state 00 (the output of the delay element 22 and the output of the delay element 23 are both 0), (XY) = (00) is output from the terminals 26 and 27. Is output and transitions to state 00. When 1 is input from state 00, (XY) = (11) is output and the state transitions to 10. When 0 is input from state 01, (XY) = (11) is output and the state transitions to state 00. When 1 is input from the state 01, (XY) = (00) is output, and the state transitions to the state 10.
[0014]
Also in other states, as shown in FIG. 13, the illustrated output is output with respect to the input of 0 or 1, and the state transits to the illustrated state.
[0015]
The bit erasing circuit 3 can change the coding rate as a result by erasing data at an appropriate position from the mother code sequence (XY) according to a certain rule. Below, for example,
X: 10
Y: 11
A case where bits are erased according to the erase map as described above will be described.
[0016]
The bit corresponding to 1 in the erasure map is transmitted, and the bit corresponding to 0 is not transmitted (erased). According to the erasure map, the outputs X (= X1) and Y (= Y1) of the convolutional encoder 2 at a certain time are transmitted in the order of X1Y1, and at the next time, the output X of the convolutional encoder 2 is transmitted. (= X2) is erased and not transmitted, and only Y (= Y2) is transmitted. That is, the bits transmitted at these two times are X1Y1Y2. With this operation, the number of bits input to the convolutional encoder 2 is 2 bits, and the number of bits output from the bit erasure circuit 3 is 3 bits, so that the coding rate R is 2/3. This operation is repeated every two unit times.
[0017]
In the serial-parallel converter 4, the input one series of data X1, Y1, Y2,... Is converted into two series of data (x, y).
[0018]
The bit spreading circuits 5-1 and 5-2 spread the bits by changing the order of the input data series x and y according to a predetermined rule. At this time, generally, the spreading methods of the bit spreaders 5-1 and 5-2 are different.
[0019]
An example of bit diffusion is shown below. An M-bit input data is defined as one block, and an appropriate numerical value s is determined. Bit spread is a vector consisting of an M-bit input sequence
From (B0, B1, ..., Bk, ..., BM-1),
Vector consisting of M-bit output sequence after spreading
Meaning substitution to (B′0, B′1,..., B′n,..., B′M−1). At this time, B′n = Bk (n = k + s mod M).
[0020]
By using different s in the bit spreading circuits 5-1 and 5-2, different bit spreading circuits can be configured with the same algorithm.
[0021]
The signal point assignment circuit 6 assigns the input data (x ′, y ′) to symbols on the transmission path. The assignment is performed according to the QPSK method, for example, as shown in FIG. That is,
When (x ′, y ′) = (0, 0), (I ′, Q ′) = (1 / √2, 1 / √2),
When (x ′, y ′) = (0, 1), (I ′, Q ′) = (1 / √2, −1 / √2),
When (x ′, y ′) = (1, 0), (I ′, Q ′) = (− 1 / √2, 1 / √2),
When (x ′, y ′) = (1, 1), (I ′, Q ′) = (− 1 / √2, −1 / √2)
Allocation is performed as follows.
[0022]
The symbol spreading circuit 7 performs symbol spreading by replacing the order of the symbols S ′ represented by (I ′, Q ′) according to a predetermined rule to obtain the symbols S (I, Q). As a result, burst errors received on the transmission line can be diffused.
[0023]
When a specific example (different from DVB-T) is shown, when N−1 symbols are used as a unit block of spreading and a number G that is less than N and relatively prime to N is determined, spreading is performed before spreading. Vector whose elements are symbols
From (S'1, S'2, ..., S'k, ..., S'N-1)
A vector whose elements are the symbols after spreading
It is executed as a replacement to (S1, S2,..., Sn,..., SN-1). At this time, Sn = S′k (n = G ^ k mod N).
[0024]
In the modulator 8, the carrier wave is modulated according to the I component and Q component of the input symbol S and transmitted via the antenna 9.
[0025]
FIG. 15 illustrates a configuration example of a receiving device that receives data transmitted from the transmitting device in FIG. 11. The demodulator 32 demodulates the radio wave received via the antenna 31 and outputs an I component signal and a Q component signal. The symbol despreading circuit 33 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 11, that is, a process of returning the order of the symbols replaced in the symbol spreading circuit 7 to the original order, and the I signal component I ′ And Q signal component Q ′ is output.
[0026]
The bit despreading circuits 34-1 and 34-2 are the bits changed in the bit spreading circuits 5-1 and 5-2 in FIG. 11 with respect to the I ′ signal and the Q ′ signal output from the symbol despreading circuit 33. The process of returning the order to the original order is executed.
[0027]
The data x corresponding to the I ′ signal component output from the bit despreading circuits 34-1 and 34-2 and the data y corresponding to the Q ′ signal component are input to the parallel-serial converter 35, and two series of data (X, y) is converted into one series of data and supplied to the bit insertion circuit 36.
[0028]
In the bit insertion circuit 36, a bit insertion process is performed opposite to the bit erase process in the bit erase circuit 3 of FIG. The bit insertion circuit 36 inputs the bit I data component data x and the Q signal component data y to the Viterbi decoder 37, which is Viterbi decoded and output as reproduction information 38. .
[0029]
Next, the operation will be described.
[0030]
The received signal received by the antenna 31 is demodulated by the demodulator 32 to obtain I component and Q component data of each symbol. The data of the I component and the Q component are input to the symbol despreading circuit 33, where the reverse operation to that in the symbol spreading circuit 7 is performed, and despread data I 'and Q' are obtained.
[0031]
That is, when the despreading operation is expressed using the same values N and G as those used in the symbol spreading circuit 7, a vector whose elements are symbols before despreading
(S1, S2,..., Sn,..., SN-1)
A vector whose elements are symbols after despreading
(S′1, S′2,..., S′k,..., S′N−1). At this time, Sn = S′k (n = G ^ k mod N).
[0032]
The I component data I 'and Q component data Q' supplied from the symbol despreading circuit 33 are supplied to the bit despreading circuits 34-1 and 34-2, respectively.
[0033]
The bit despreading circuits 34-1 and 34-2 correspond to the bit spreading circuits 5-1 and 5-2, respectively, and perform operations reverse to those of the bit spreading circuits 5-1 and 5-2, respectively.
[0034]
That is, M input data is set as one block, an appropriate numerical value s is determined, and a vector composed of M input sequences
(B'0, B'1, ..., B'n, ..., B'M-1)
Vector consisting of M output sequences after despreading
(B0, B1,..., Bk,..., BM-1) are obtained. At this time, B′n = Bk (n = k + s mod M).
[0035]
Here, the numerical value s used in the bit despreading of the bit despreading circuits 34-1 and 34-2 is the same value as the numerical value s used in the bit spreading circuits 5-1 and 5-2, respectively.
[0036]
The data sequence (x, y) that has been bit-despread in this way is supplied to the parallel-to-serial converter 35 of the next stage, where the reverse operation of the serial-to-parallel converter 4 is performed, and two series of data (x, y). To one series of data.
[0037]
In the bit insertion circuit 36, an operation reverse to that of the bit erasure circuit 3 is performed. That is, the erase map in the previous example
X: 10
Y: 11
In response to the processing of the bit erasing circuit 3 using
X1, Y1, Y2 (in this case, x1, y1, y2)
For the data input in this order, arbitrary dummy data (here, 0) is inserted at a position corresponding to the erased data X2 (x2),
As X data, X1 (x1), 0 is
As Y data, Y1 (y1), Y2 (y2) are
Output in this order. Further, an insertion flag indicating the position where the dummy data is inserted is supplied to the Viterbi decoder 37.
[0038]
The Viterbi decoder 37 performs Viterbi decoding according to the state transition of the convolutional encoder 2 (FIG. 13). FIG. 16 shows an example of the Viterbi decoder 37. Data X and Y output from the bit insertion circuit 36 are input to the input terminals 62-1 and 62-2, respectively. These data X and Y are input to the branch metric calculation circuits 63-1 to 63-4. In the branch metric calculation circuit 63-1, the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) shown in FIG. 14 is calculated as a branch metric. Similarly, in the branch metric calculation circuits 63-2 to 63-4, input data (X, Y) and coordinate points (1 / √2, −1 / √2), (−1 / √2, 1 / √). 2) or (−1 / √2, −1 / √2) is calculated.
[0039]
The outputs (branch metrics) BM00 of the branch metric calculation circuits 63-1 and 63-4 are input to an ACS (Add Compare Select) circuit 64-1. Similarly, the output (branch metric) BM01 of the branch metric calculation circuit 63-2 and the output (branch metric) BM10 of the branch metric calculation circuit 63-3 are input to the ACS circuit 64-2, and the branch metric calculation circuit 63-1. Output (branch metric) BM00 and the output (branch metric) BM11 of the branch metric calculation circuit 63-4 are input to the ACS circuit 64-3, and the output (branch metric) BM01 and branch metric of the branch metric calculation circuit 63-2 The output (branch metric) BM10 of the arithmetic circuit 63-3 is input to the ACS circuit 64-4.
[0040]
The ACS circuit 64-1 is also supplied with the output (state metric) SM00 of the state metric storage device 66-1 and the output (state metric) SM01 of the state metric storage device 66-2. The output (state metric) SM10 of the state metric storage device 66-3 and the output (state metric) SM11 of the state metric storage device 66-4 are input. Similarly, the output (state metric) SM00 of the state metric storage device 66-1 and the output (state metric) SM01 of the state metric storage device 66-2 are input to the ACS circuit 64-3, and the ACS circuit 64- 4, the output (state metric) SM10 of the state metric storage device 66-3 and the output (state metric) SM11 of the state metric storage device 66-4 are input.
[0041]
The ACS circuits 64-1 to 64-4 add one input branch metric BM and the corresponding state metric SM, and add the other branch metric BM and the corresponding state metric SM. Then, the two addition results are compared, and the smaller addition value corresponding to the comparison result is output to the state metric storage devices 66-1 to 66-4 as a new state metric SM, and the selection result Are output to the path memory 65. State metrics SM00 to SM11 stored in the state metric storage devices 66-1 to 66-4 are also input to the path memory 65.
[0042]
The state metric storage devices 66-1 to 66-4 are reset by a signal input from the terminal 61. The path memory 65 is configured to output a decoding result from a terminal 67.
[0043]
Next, the operation will be described.
[0044]
In the branch metric calculation circuit 63-1, the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) is calculated as the branch metric BM00. Similarly, in the branch metric calculation circuit 63-2, the distance between the input data (X, Y) and the coordinate point (1 / √2, −1 / √2), and in the branch metric calculation circuit 63-3, the input data (X, Y). ) And the coordinate point (−1 / √2, 1 / √2), the branch metric calculation circuit 63-4 uses the input data (X, Y) and the coordinate point (−1 / √2, −1 / √2). ) Are calculated as branch metrics BM01, BM10, and BM11, respectively. Here, the distance calculation for the inserted dummy data is omitted according to the insertion flag supplied from the bit insertion circuit 36 at the preceding stage. That is, the distance between the inserted bit and the coordinate to be compared is all the same (for example, 0).
[0045]
The ACS circuit 64-1 calculates the following two expressions according to the state transition of the convolutional encoder 2, and selects the one with the highest likelihood, that is, the one with the smaller calculation result. In 65, the calculation result SM is supplied to the state metric storage device 66-1.
[0046]
SM00 + BM00 (1)
SM01 + BM11 (2)
[0047]
Here, SM00 is a value of the state metric storage device 66-1 one unit time ago, SM01 is a value of the state metric storage device 66-2 one unit time ago, and BM00 is a value of the branch metric calculation circuit 63-1. The calculation result, BM11, represents the calculation result of the branch metric calculation circuit 63-4.
[0048]
If the calculation result of Expression (1) is smaller, SEL00 = 0 is supplied to the subsequent path memory 65, and if the calculation result of Expression (2) is smaller, SEL00 = 1 is supplied. In the former case, SM00 + BM00 is stored, and in the latter case, SM01 + BM11 is stored as a new state metric SM00 in the state metric storage device 66-1.
[0049]
This calculation will be described with reference to FIG. There are two paths that reach state 00. The first is a path that receives 0 in state 00 and outputs 00, and the calculation expression to be compared is as shown in equation (1), and the second is in state 01. In a path in which 0 is input and 11 is output, a calculation expression to be compared is as shown in Expression (2). The smaller of the calculation results is supplied as new state metric SM00 to state metric storage device 66-1.
[0050]
Similar operations are performed in the ACS circuits 64-2 to 64-4. Note that the state metric storage devices 66-1 to 66-4 are reset to 0 at the initial stage when the system operates. This control is performed via a terminal 61 from a control device (not shown).
[0051]
The path memory 65 selects, stores, and propagates input data, that is, decoded data, using selection information SEL00 to SEL11 from the ACS circuits 64-1 to 64-4 according to the state transition diagram of FIG.
[0052]
FIG. 17 illustrates a configuration example of the branch metric calculation circuit 63-1. Data X input from the terminal 62-1 is input to the subtraction circuit 51, and 1 / √2 output from the generation circuit 52 is subtracted. The output of the subtracting circuit 51 is branched and input to the multiplying circuit 53 and is multiplied (that is, squared). The selector 203 receives the output of the multiplication circuit 53 and the output of the generation circuit 202, and selects 0 generated by the generation circuit 202 when a dummy flag for X is input from the bit insertion circuit 36 via the terminal 201. In other cases, the output of the multiplier circuit 53 is selected and output to the adder circuit 54.
[0053]
Similarly, the data Y input from the terminal 62-2 is input to the subtraction circuit 55, and 1 / √2 output from the generation circuit 56 is subtracted. The output of the subtracting circuit 55 is branched and input to the multiplying circuit 57, and is multiplied (squared). The selector 206 receives the output of the multiplication circuit 57 and the output of the generation circuit 205, and selects 0 generated by the generation circuit 205 when a dummy flag for Y is input from the bit insertion circuit 36 through the terminal 204. At other times, the output of the multiplication circuit 57 is selected and output to the addition circuit 54. The adder circuit 54 adds the output of the selector 203 and the output of the selector 206 and outputs the result as a branch metric BM00.
[0054]
That is, in this example, when the flag is not input, the subtracting circuit 51 outputs X−1 / √2, which is squared by the multiplying circuit 53, and from the multiplying circuit 53 (X−1 / √2).²Is output. Similarly, the subtraction circuit 55 outputs Y−1 / √2, and this value is squared by the multiplication circuit 57, and the multiplication circuit 57 is (Y−1 / √2).²Is output. The adder circuit 54 is an addition value (X−1 / √2) of the output of the multiplier circuit 53 and the output of the multiplier circuit 57.²+ (Y-1 / √2)²Is output as the branch metric BM00. On the other hand, when the X dummy flag is input, the selector 203 outputs 0, so the output of the adder circuit 54 is (Y-1 / √2).²When the dummy data of Y is input, the selector 206 outputs 0, so that the output of the adder circuit 54 is (X−1 / √2)²It becomes.
[0055]
In the branch metric calculation circuits 63-2 to 63-4, the same calculation is performed by a circuit having the same configuration as that shown in FIG. However, in the branch metric calculation circuit 63-2, the output of the generation circuit 52 is 1 / √2, and the output of the generation circuit 56 is −1 / √2. In the branch metric calculation circuit 63-3, the outputs of the generation circuits 52 and 56 are -1 / √2 and 1 / √2, respectively. In the branch metric calculation circuit 63-4, -1 / √√ respectively. 2 and -1 / √2.
[0056]
FIG. 18 shows a block diagram of the path memory 65. The selection information SEL00 to SEL11 output from the ACS circuits 64-1 to 64-4 is input to the terminals 71-1 to 71-4. These selection information SEL00 to SEL11 are input as control signals to the two-input one-output selectors 73-1 to 73-4, respectively. The selector 73-1 receives fixed data 0 from the terminal 72-1 as two inputs. Similarly, fixed data 0, 1 or 1 is input to the selectors 73-2 to 73-4 as two inputs from the terminals 72-2 to 72-4, respectively.
[0057]
The selectors 73-1 to 73-4 select one of the two inputs corresponding to the selection information SEL00 to SEL11 and output the selected input to the subsequent registers 81-1 to 81-4. However, since the same data is input to the first column selectors 73-1 to 73-4 as two inputs from the terminals 72-1 to 72-4 as described above, the register 81-1 Through 81-4, 0, 0, 1 or 1 is stored, respectively.
[0058]
Similarly, a configuration including selectors and registers of n columns (four columns in the case of FIG. 18) is provided. That is, in the second column, selectors 74-1 to 74-4 and registers 82-1 to 82-4 are provided. The selector 74-1 is supplied with the output of the register 81-1 and the output of the register 81-2 in the previous row. The selector 74-2 receives the output of the register 81-3 and the output of the register 81-4. The selector 74-3 receives the output of the register 81-1 and the output of the register 81-2. -4 receives the output of the register 81-3 and the output of the register 81-4. Then, the selectors 74-1 to 74-4 select one of the two inputs corresponding to the values of the selection information SEL00 to SEL11, and perform processing to output to the subsequent registers 82-1 to 82-4. . For example, the register 74-1 selects the output of the register 81-1 when the selection information SEL00 is 0, and selects and outputs the output of the register 81-2 when the selection information SEL00 is 1. Has been made.
[0059]
The outputs of the registers 84-1 to 84-4 in the final column are input to the selector 85 having four inputs and one output.
[0060]
State metrics SM00 to SM11 output from the state metric storage devices 66-1 to 66-4 in FIG. 16 are input to the minimum value comparison circuit 88 from terminals 87-1 to 87-4. The minimum value comparison circuit 88 compares the sizes of the four state metrics and selects the smallest one. When the state metric SM00 is minimum, the data 00 is output. When the state metric SM01 is minimum, the data 01 is output. When the state metric SM10 is minimum, the data 10 is output. When the state metric SM11 is minimum, the data 11 is output. The selector 85 selects the output of the register 84-1 when the input from the minimum value comparison circuit 88 is 00, selects the output of the register 84-2 when it is 01, and selects the register 84 when it is 10. -3 is selected. When the output is 11, the output of the register 84-4 is selected and output from the terminal 86 as a decoding result. The fixed values of the terminals 72-1 to 72-4 mean the decoding information corresponding to each state.
[0061]
Such connection of the path memory 65 is based on the state transition diagram of FIG. In the configuration of the path memory 65, the top row corresponds to the state 00, the second row corresponds to the state 01, the third row corresponds to the state 10, and the bottom row corresponds to the state 11. In the first column, decoding information is fetched. According to FIG. 13, there are two paths from state 00 and state 01 to reach state 00. The input bit corresponding to each path, that is, the decoding information is 0 in all cases. Therefore, in the first column in the state 00 (top row), the input terminal of the selector 73-1 is wired so that the corresponding decoding information 0 is selected by the selection information SEL00.
[0062]
In the first column, connection is made in the same manner for the state 01, the state 10 and the state 11.
[0063]
In the second and subsequent columns, selection, propagation, and storage of decoded sequences are performed. According to FIG. 13, there are two paths from state 00 and state 01 to reach state 00. Therefore, in the second column in the state 00, the input terminal of the selector 74-1 is wired so that the data from the corresponding state is selected by the selection information SEL00.
[0064]
In the second column to the third row, the state 01, the state 10, and the state 11 in the second column are connected in the same manner.
[0065]
In the last column of the path memory 65, data corresponding to the path with the highest likelihood is output as final decoded data from the four stored decoded data. The “maximum likelihood path” is a path corresponding to the one having the minimum value among the four state metrics SM00 to SM11. The selector 85 uses the path corresponding to the minimum value of the state metric at that time. That is, the path with the highest likelihood is selected.
[0066]
[Problems to be solved by the invention]
By the way, in recent years, while high-speed (high bit rate) transmission is screamed, it is conceivable to expand the modulation method of the digital data transmission system from QPSK to 16QAM, 64QAM, 256QAM, and the like. In this way, the number of bits that can be transmitted is 4 bits, 6 bits, or 8 bits for 2 bits of QPSK, respectively, and increases 2 times, 3 times, and 6 times that of QPSK.
[0067]
FIG. 19 shows a block diagram of a 16QAM data transmission apparatus. 19, parts corresponding to those in FIG. 11 are denoted by the same reference numerals. That is, in this example, the serial / parallel converter 4 converts the serial data output from the bit erasure circuit 3 into data u, v, x, y in units of 4 bits. Then, bit diffusion processing is performed for each data in the bit diffusion circuits 91-1 to 91-4, and the data is supplied to the signal point assignment circuit 6 as data u ′, v ′, x ′, y ′. Has been made. Other configurations are the same as those in FIG.
[0068]
That is, in this example, in the serial-parallel converter 4, one series of data is converted into four series of data (u, v, x, y) corresponding to 16QAM, and the respective bit spreading circuits 91-1 to 91 are used. In -4, bit diffusion processing is performed by changing the order of bits according to a predetermined rule. The processing is the same as the processing in the bit spreading circuits 5-1 and 5-2 in FIG. 11, and different bit spreading processing is executed using different numerical values s.
[0069]
The signal point assignment circuit 6 assigns the input 4-bit data (u ′, v ′, x ′, y ′) to the symbols on the transmission path. The assignment is performed according to FIG. 20, for example. That is, for example,
When (u ′, v ′, x ′, y ′) = (0, 0, 0, 0),
(I ', Q') = (3 / √10, 3 / √10),
When (u ′, v ′, x ′, y ′) = (0, 0, 0, 1),
(I ', Q') = (3 / √10, 1 / √10),
Allocation is performed as follows.
[0070]
Similar assignments are made for other inputs.
[0071]
Thereafter, the same processing as in FIG. 11 is performed, and data is transmitted.
[0072]
When the transmitting apparatus shown in FIG. 19 performs signal point assignment by the 16QAM system as shown in FIG. 20 and receives the transmitted data, the receiving apparatus is configured as shown in FIG. 21 corresponding to FIG. It is possible. However, actually, it cannot be configured as shown in FIG.
[0073]
That is, as described above, the components I and Q of the data (I and Q) input from the demodulator 32 to the symbol despreading circuit 33 each represent 1 bit in the case of the QPSK system. In the case of the 16QAM system, each represents 2 bits. For example, in the signal point arrangement shown in FIG. 20, I includes information on the first bit and the third bit, and Q includes information on the second bit and the fourth bit. For example, I is one value such as 1 / √10, 3 / √10, and Q is also one value. Therefore, as shown in FIG. 21, it cannot be divided into u 'and v' or divided into x 'and y'. As a result, the data receiving apparatus in the case of the 16QAM system is also configured as shown in FIG.
[0074]
As a result, the processing performed in the bit insertion circuit 36 in FIG. 15 is as follows.
[0075]
That is, if data is input to the bit insertion circuit 36 as shown in FIG. 22A, as shown in FIG. 22A, x1, y1, x2, y2, x3, y3,. , X1 and y1 are output as data X1 and Y1, then dummy data d is output as data X2, and data x2 is output as data Y2. Similarly, after data y2 and x3 are output as data X3 and Y3, dummy data d is output as data X4, and then data y3 is output as data Y4.
[0076]
However, this process does not execute the reverse process of the process in the bit erasing circuit 3 of FIG. That is, the bit erasure (bit operation) processing performed in the bit erasure circuit 3 is performed in units of 1 bit. On the other hand, the data x1, y2, etc. shown in FIG. 22B each correspond to 2-bit data, after which 1-bit dummy data d is inserted, and then When 2-bit data x2 is output, a data array that is completely different from the original data array is output.
[0077]
As a result, when the output of the bit insertion circuit 36 is Viterbi-decoded by the Viterbi decoder 37, the decoding result is not such that performance is slightly degraded, and decoding is impossible at all.
[0078]
On the other hand, if a hard decision is made in the symbol despreading circuit 33 of the data receiving apparatus shown in FIG. 21, for example, from (I, Q), u ′, v ′, x ′ and y ′ can be generated. That is, in this case, the distance between the coordinates of (I, Q) and each signal point shown in FIG. 20 is calculated, and (I, Q) corresponds to the signal point with the shortest distance. It is possible to generate u ′, v ′, x ′, and y ′. However, if such a hard decision is made, accurate data decoding becomes difficult.
[0079]
The present invention has been made in view of such a situation. Even when punctured error correction decoding is transmitted by multi-level multi-phase modulation schemes such as 16QAM, 64QAM, and 256QAM, the data is accurately decoded. It is something that can be done.
[0080]
[Means for Solving the Problems]
  The first data receiving apparatus of the present invention reverses information associated with a symbol of transmission data that is digitally modulated and transmitted by the multi-level / multi-phase method in accordance with a rule opposite to the rule corresponding to the bits constituting the symbol.diffusionReversediffusionMeans and vice versadiffusionReverse by meansdiffusionFrom the information accompanying the generated symbol to the bits making up the symbolThe conditional posterior probability for the bitCorresponding metricAsMetric calculation means for calculating and metric calculation meansThe decryption process on the output ofAnd a decoding means.
[0081]
  Symbol despreading means for despreading the data symbols may be further provided.
[0082]
  The second data receiving apparatus of the present invention provides a value 0 for each bit of data.Conditional posterior probabilityOr for value 1Conditional posterior probabilityOnly one ofAs a metricFrom one value and a given reference value,MetricsA metric calculation means for calculating the metric, a bit despreading means for despreading the metric calculated by the metric calculation means, and a decoding means for decoding the data obtained as a result of the despreading by the bit despreading means It is characterized by that.
[0083]
  Symbol despreading means for despreading the data symbols may be further provided.
[0084]
  According to the first receiving method of the present invention, information associated with a symbol of transmission data that is digitally modulated and transmitted by the multi-value / multi-phase method is reversed according to a rule opposite to a rule corresponding to a bit constituting the symbol.diffusionReversediffusionStep and reversediffusionReverse each step processingdiffusionFrom the information accompanying the generated symbol to the bits making up the symbolThe conditional posterior probability for that bitCorresponding metricAsMetric calculation step to calculate and metric calculation stepPerform decryption on the processing resultA decoding step.
[0085]
  In the second data receiving method of the present invention, for each bit of data, a value of 0 is obtained.Conditional posterior probabilityOr for value 1Conditional posterior probabilityOnly one ofAs a metricFrom one value and a given reference value,MetricsThe metric calculation step for calculating the metric, the metric calculated in the metric calculation step processing, the bit despreading step for despreading, and the decoding processing of the data obtained as a result of the despreading in the bit despreading step processing A decoding step.
[0086]
  In the first receiving apparatus and method of the present invention, the information attached to the symbol of the transmission data that is digitally modulated and transmitted by the multi-value / multi-phase method is in accordance with the reverse rule of the rule corresponding to the bits constituting the symbol. Reverse eachdiffusionAnd reverse eachdiffusionFrom the information accompanying the generated symbol to the bits making up the symbolThe conditional posterior probability for the bitCorresponding metricAsCalculated and calculated metricDecryption processingIs done.
[0087]
  In the second data receiving apparatus and method of the present invention, for each bit of data, the value 0Conditional posterior probabilityOr for value 1Conditional posterior probabilityOnly one ofAs a metricFrom one value and a predetermined reference value,MetricsAre calculated, the calculated metric is despread, and the data obtained as a result of the despreading is decoded.
[0088]
DETAILED DESCRIPTION OF THE INVENTION
In the data transmission device of FIG. 11 (19), bit erasure is performed, but it is also possible to transmit data without performing bit erasure. FIG. 1 is a block diagram showing an example of the configuration of the data transmission apparatus in such a case. In this figure, the same parts as those in FIG. 11 (19) are denoted by the same reference numerals, and the description thereof is omitted. In this embodiment, the bit erasing circuit 3 and the serial-parallel converter 4 are excluded. Further, the output of the convolutional encoder 2 is changed from 2 series (X, Y) to 4 series (u, v, x, y). Other configurations are the same as those in the case of FIG. 11 (19).
[0089]
FIG. 2 is a block diagram showing an example of a detailed configuration of the convolutional encoder 2 shown in FIG. The convolutional encoder 2 delays input data by one clock and outputs the delay circuits 92-1 to 92-3, and addition circuits 93-1 to 93-1 that calculate exclusive OR of the input data. 93-4.
[0090]
Data I input from the information source 1 is input to the delay circuit 92-1 and the adder circuits 93-1 to 93-4, respectively. The output of the delay circuit 92-1 is input to the delay circuit 92-2 and the adder circuits 93-1, 93-2. The output of the delay circuit 92-2 is input to the delay circuit 92-3 and the adder circuits 93-1, 93-3. The delay circuit 92-3 is input to the adder circuits 93-1 to 93-4. The outputs of the adder circuits 93-1 to 93-4 are output as four series of data (u, v, x, y).
[0091]
Next, the operation of the embodiment of FIG. 2 will be described with reference to FIG.
[0092]
FIG. 3 shows a state transition diagram of the convolutional encoder 2. The state transition of the convolutional encoder 2 is as follows.
[0093]
That is, for example, when 0 is input in state 000 (the states of delay circuits 92-1 to 92-3 are all 0), (uvxy) = (0000) from addition circuits 93-1 to 93-4. ) Is output, and the state transitions to state 000. When 1 is input from the state 000, (uvxy) = (1111) is output, and the state transitions to the state 100. When 0 is input from the state 001, (uvxy) = (1111) is output, and the state transitions to the state 000. When 1 is input from the state 001, (uvxy) = (0000) is output, and the state transitions to the state 100.
[0094]
Also in other states, as shown in FIG. 3, the illustrated signal is output in response to an input of 0 or 1, and the state transits to the illustrated state. Therefore, the convolutional encoder 2 shown in FIG. 2 outputs four series of data (u, v, x, y) corresponding to the information output from the information source 1.
[0095]
The four sequences of data output from the convolutional encoder 2 are subjected to bit spreading processing by the bit spreading circuits 91-1 to 91-4 changing the order of bits according to a predetermined rule. The processing is the same as the processing in the bit spreading circuits 5-1 and 5-2 in FIG. 11, and each of the bit spreading circuits 91-1 to 91-4 performs bit spreading using a different numerical value s.
[0096]
As described with reference to FIG. 11, the signal point assignment circuit 6 assigns four series of input data (u ′, v ′, x ′, y ′) to symbols on the transmission path. Other operations are the same as those in FIG.
[0097]
FIG. 4 is a block diagram showing the configuration of the first embodiment of the data receiving apparatus of the present invention, which receives data transmitted from the data transmitting apparatus shown in FIG. In this figure, portions corresponding to those in FIG. 15 are denoted by the same reference numerals, and description thereof is omitted.
[0098]
The symbol despreading circuit 33 performs symbol despreading by the reverse operation of the symbol spreading circuit 7 shown in FIG. 1, and converts the I component and Q component of the received signal into an I ′ component and a Q ′ component, respectively. It has been made to convert.
[0099]
The bit despreading circuits 101-1 to 101-4 are configured to perform bit despreading processing on the I ′ signal and Q ′ signal output from the symbol despreading circuit 33. The bit despreading circuit 101-1 performs despreading processing on the first bit of the symbol defined by the I ′ signal and the Q ′ signal, and the bit despreading circuits 101-2 through 101-4 respectively perform the second through A fourth bit despreading process is performed.
[0100]
The I signal component and Q signal component of the first bit to the fourth bit output from the bit despreading circuits 101-1 to 101-4 are input to the corresponding metric calculation circuits 102-1 to 102-4, respectively. , Metrics corresponding to the first to fourth bits are calculated. Data (metric) u, v, x, and y output from the metric calculation circuits 102-1 to 102-4 are input to the Viterbi decoder 103. The Viterbi decoder 103 decodes input data (metric) and outputs reproduction information 38.
[0101]
The metric calculation circuit 102-1 is configured as shown in FIG.
[0102]
That is, the I ′ signal and the Q ′ signal output from the bit despreading circuit 101-1 in FIG. 4 are input to n probability calculation circuits 111-1 to 111-n. In this case, as shown in FIG. 20, since signal point allocation processing is performed with 16QAM, n is set to 16. Probability calculation circuit 111-1 transmits symbol S0000 corresponding to 0000 of 16QAM shown in FIG. 20 and calculates probability P (S0000０R) of receiving reception signal R. Similarly, in the probability calculation circuit 111-2, the probability P (S0001∩R) that the symbol S0001 corresponding to 0001 of 16QAM is transmitted and the received signal R is received is calculated, and the probability calculation circuit 111-3. , The probability P (S0010∩R) that the symbol S0010 corresponding to 0010 of 16QAM is transmitted and the received signal R is received is calculated. Then, the probability calculation circuit 111-16 transmits a symbol S1111 corresponding to 16QAM 1111 and calculates a probability P (S1111∩R) that the received signal R is received.
[0103]
The adder circuit 112 receives an input of an output of a probability calculation circuit 111-i that calculates a probability for a symbol whose first bit is 0, that is, S0000, S0001, S0010, S0011, S0100, S0101, S0110, and S0111. Calculate the sum. On the other hand, the adder circuit 113 receives the input of the output of the probability calculation circuit 111-i for calculating the probabilities for all symbols of 16QAM, that is, S0000 to S1111 and calculates the sum thereof. The division circuit 114 divides the output of the addition circuit 112 by the output of the addition circuit 113.
[0104]
The metric calculation circuits 102-2 to 102-4 are basically configured in the same manner as the metric calculation circuit 102-1, but the addition circuit 112 in FIG. The sum of probabilities for a certain symbol is calculated.
[0105]
FIG. 6 is a block diagram illustrating an exemplary configuration of the Viterbi decoder 103.
[0106]
Data u, v, x, and y output from the metric calculation circuits 102-1 to 102-4 shown in FIG. 4 are input to the input terminals 62-1 to 62-4, respectively. The inverting circuits 140-1 to 140-4 invert all the bits of the input data and output them. The multiplication circuits 141-1 to 141-16 multiply the predetermined data among the data output from the input terminals 62-1 to 62-4 and the inverting circuits 140-1 to 140-4, respectively, BM0000 to BM1111. As output.
[0107]
The ACS circuits 142-1 through 142-8 multiply one input branch metric BM by the corresponding state metric SM, and multiply the other branch metric BM by the corresponding state metric SM. Then, the two addition results are compared, and the larger multiplication value corresponding to the comparison result is output to the state metric storage devices 143-1 to 143-8 as a new state metric SM, and the selection result The signals SEL000 through SEL111 representing the above are output to the path memory 144. State metrics SM000 to SM111 stored in the state metric storage devices 143-1 to 143-8 are also input to the path memory 144.
[0108]
The state metric storage devices 143-1 to 143-8 are reset by a signal input from the terminal 61. The path memory 144 is configured to output the decoding result from the terminal 145.
[0109]
The multiplier circuit 141-1 multiplies the metrics u, v, x, and y input from the input terminals 62-1 to 62-4, and outputs the calculation result as a branch metric BM0000. The multiplier circuit 141-2 multiplies the metrics u, v, and x input from the input terminals 62-1 to 62-3 and the metric y inverted by the inverter circuit 140-4, and the operation result is the branch metric BM0001. As output. Similarly, the multiplier circuit 141-3 multiplies the metrics u, v, and y input from the input terminals 62-1, 62-2, and 62-4 and the inverted metric x output from the inverter circuit 140-3. Then, the calculation result is output as the branch metric BM0010, and the multiplication circuit 141-16 multiplies the inverted metrics u, v, x, and y output from the inverting circuits 140-1 to 140-4, and the calculation result. Is output as a branch metric BM1111.
[0110]
That is, assuming that the data output from the inverting circuits 140-1 to 140-4 is (u ′, v ′, x ′, y ′), the outputs BM0000 to BM1111 from the multiplying circuits 141-1 to 141-8, The relationship between the data input from the input terminals 62-1 to 62-4 and the data output from the inverting circuits 140-1 to 140-4 is as follows.
[0111]
BM0000 = u, v, x, y
BM0001 = u, v, x, y '
BM0010 = u ・ v ・ x ′ ・ y
:
:
BM1111 = u ', v', x ', y'
[0112]
An output (branch metric) BM0000 of the multiplication circuit 141-1 and an output (branch metric) BM1111 of the multiplication circuit 141-16 are input to an ACS (Accumulate Compare Select) circuit 142-1. Similarly, the ACS circuit 142-2 receives the output BM0101 of the multiplication circuit 141-6 and the output BM1010 of the multiplication circuit 141-11. Further, the output BM0011 of the multiplication circuit 141-4 and the BM1100 output from the multiplication circuit 141-13 are input to the ACS circuit 142-3. Further, the output BM1001 of the multiplication circuit 141-10 and the output BM0110 of the multiplication circuit 141-7 are input to the ACS circuit 142-8.
[0113]
The ACS circuit 142-1 also receives the output (state metric) SM000 of the state metric storage device 143-1 and the output (state metric) SM001 of the state metric storage device 143-2. The output (state metric) SM010 of the state metric storage device 143-3 and the output (state metric) SM011 of the state metric storage device 143-4 are input. Similarly, an output (state metric) SM100 of the state metric storage device 143-5 and an output (state metric) SM101 of the state metric storage device 143-6 are input to the ACS circuit 142-3, and the ACS circuit 142- 8, the output (state metric) SM110 of the state metric storage device 143-7 and the output (state metric) SM111 of the state metric storage device 143-8 are input.
[0114]
The ACS circuits 142-1 through 142-8 multiply one input branch metric BM by the corresponding state metric SM, and multiply the other branch metric BM by the corresponding state metric SM. Then, the two addition results are compared, and the larger multiplication value corresponding to the comparison result is output to the state metric storage devices 143-1 to 143-8 as a new state metric SM, and the selection result The signals SEL000 to SEL1111 representing the above are output to the path memory 144. State metrics SM000 to SM111 stored in the state metric storage devices 143-1 to 143-8 are also input to the path memory 144.
[0115]
The state metric storage devices 143-1 to 143-8 are reset by a signal (RST) input from the terminal 61. The path memory 144 is configured to output the decoding result from the terminal 145.
[0116]
FIG. 7 is a block diagram illustrating a detailed configuration example of the path memory 144.
[0117]
Selection information SEL000 through SEL111 output from the ACS circuits 142-1 through 142-8 are input to the input terminals 150-1 through 150-8, respectively. These selection information SEL000 to SEL111 are input as control signals to the 2-input 1-output selectors 151-1 to 151-8, respectively. The selector 151-1 receives the fixed data 0 from the terminal 161-1 as two inputs. Similarly, fixed data 0 is input to the selectors 151-2 to 151-4 from the terminals 161-2 to 161-4 as two inputs, respectively, and to the selectors 151-5 to 151-8. The fixed data 1 is input as two inputs from the terminals 161-5 to 161-8.
[0118]
The selectors 151-1 to 151-8 select one of the two inputs corresponding to the selection information SEL000 to SEL111, and output the selected input to the subsequent registers 152-1 to 152-8. However, since the same data is input to the selectors 151-1 to 151-8 in the first column as two inputs from the terminals 161-1 to 161-8 as described above, the register 152-1 Through 152 to 8 are stored 0, 0, 1 or 1, respectively.
[0119]
Hereinafter, similarly, a configuration including selectors and registers of n columns (four columns in the example of FIG. 7) is provided. That is, in the second column, selectors 153-1 to 153-8 and registers 154-1 to 154-8 are provided. The selector 153-1 is supplied with the output of the register 152-1 in the previous row and the output of the register 152-2. The selector 153-2 receives the output of the register 152-3 and the output of the register 152-4. The selector 153-3 receives the output of the register 152-5 and the output of the register 152-6. The selector 153 The output of the register 152-7 and the output of the register 152-8 are input to -8. Then, the selectors 153-1 to 153-8 select one of the two inputs corresponding to the values of the selection information SEL000 to SEL111, and output them to the subsequent registers 154-1 to 154-8. For example, the register 153-1 selects the output of the register 152-1 when the selection information SEL000 is 0, and selects and outputs the output of the register 152-2 when the selection information SEL000 is 1. Has been made.
[0120]
The outputs of the registers 158-1 to 158-8 in the last column are input to the 8-input 1-output selector 159.
[0121]
State metrics SM000 to SM111 output from the state metric storage devices 143-1 to 143-8 in FIG. 6 are input to the minimum value comparison circuit (CMP) 160 via the terminals 162-1 to 162-8. Yes. The minimum value comparison circuit 160 (CMP) compares the magnitudes of the eight state metrics and selects the smallest one. For example, if the state metric SM000 is minimum, data 000 is output. If the state metric SM001 is minimum, data 001 is output. If the state metric SM010 is minimum, data 010 is output. If the state metric SM111 is minimum, the data 111 is output. The selector 159 selects the output of the register 158-1 when the input from the minimum value comparison circuit 160 is 000, selects the output of the register 158-2 when it is 001, and selects the register 158 when it is 010. -3 output is selected. When the output is 111, the output of the register 158-8 is selected and output from the terminal 163 as a decoding result. The same applies when the output of the minimum value comparison circuit 160 is 011 to 110. The fixed values of the input terminals 161-1 to 161-8 mean the decoding information corresponding to each state.
[0122]
Such connection of the path memory 144 is based on the state transition diagram of FIG. That is, in the configuration of the path memory 144, the top row corresponds to the state 000, the second row corresponds to the state 001, the third row corresponds to the state 010, and the bottom row corresponds to the state 111. In the first column, decoding information is fetched. According to FIG. 3, there are two paths from state 000 and state 001 to reach state 000. The input bit corresponding to each path, that is, the decoding information is 0 in all cases. Therefore, in the first column in the state 000 (top row), the input terminal of the selector 151-1 is wired so that the corresponding decoding information 0 is selected by the selection information SEL000.
[0123]
The first row, state 001, state 010,..., State 111, are similarly connected.
[0124]
In the second and subsequent columns, selection, propagation, and storage of decoded sequences are performed. According to FIG. 3, there are two paths from state 000 and state 001 to reach state 000. Therefore, in the second column in the state 000, the input terminal of the selector 153-1 is wired so that the data from the corresponding state is selected by the selection information SEL000.
[0125]
In the second column, state 001, state 010,...
[0126]
In the final column of the path memory 144, data corresponding to the path with the highest likelihood is output as final decoded data from the eight stored decoded data. The “maximum likelihood path” is a path corresponding to the one having the minimum value among the eight state metrics SM000 to SM111, and the selector 159 corresponds to the path corresponding to the minimum value of the state metric at that time. That is, the path with the highest likelihood is selected.
[0127]
Next, the operation will be described.
[0128]
The received signal received by the antenna 31 is demodulated by the demodulator 32 to obtain I component and Q component data of the symbol. The I component and Q component data is despread in the symbol despreading circuit 33 by performing an operation reverse to that of the symbol spreading circuit 7 in FIG. 1 (processing for returning the order of the rearranged symbols to the original order). I 'and Q' signals are obtained.
[0129]
This symbol despreading operation is performed using vectors N and G having the same values as those of the symbol spreading circuit 7 and using symbols before despreading as elements.
(S1, S2,..., Sn,..., SN-1)
A vector whose elements are symbols after despreading
(S′1, S′2,..., S′k,..., S′N−1). At this time, Sn = S′k (n = G ^ k mod N).
[0130]
The I ′ signal and Q ′ signal supplied from the symbol despreading circuit 33 are supplied to the bit despreading circuits 101-1 to 101-4, respectively.
[0131]
The bit despreading circuit 101-1 for the first bit performs the reverse operation of the bit spreading circuit 91-1 for the first bit in FIG. 1 while retaining the coordinates (a combination of I ′ and Q ′) as a symbol. Is done. That is, B′i (I ′, Q ′) is a set, and a vector having M sets of B′i data corresponding to the bit spreading circuit 91-1 in FIG.
(B'0, B'1, ..., B'n, ..., B'M-1)
Bi (I, Q) as one set and M sets of Bi as elements
(B0, B1,..., Bk,..., BM-1).
[0132]
At this time, B′n = Bk (n = k + s mod M), and s is set to the same value as that used in the bit spreading circuit 91-1.
[0133]
Similarly, in the other bit despreading circuits 101-2 to 101-4, bit despreading processing relating to the second to fourth bits is performed while retaining the symbol coordinates. At this time, the numerical value s used in the bit despreading of the bit despreading circuits 101-2 to 101-4 is the same value as the numerical value s used in the bit spreading circuits 91-2 to 91-4, respectively.
[0134]
The bit despread data sequences (I′u, Q′u), (I′v, Q′v), (I′x, Q ′) output from the bit despreading circuits 101-1 to 101-4 in this way. x) and (I′y, Q′y) are supplied to the metric calculation circuits 102-1 to 102-4, respectively.
[0135]
Next, the metric calculation in the metric calculation circuits 102-1 to 102-4 will be described. The metric here means a conditional posterior probability with respect to the bits constituting the received signal when a predetermined received signal is received, which is defined by the following equation.
P (bi = 0 | R) = P (bi = 0∩R) / P (R) (3)
[0136]
Here, P (bi = 0 | R) is the received signal R (Ir, Qr) (Ir = I'u, I'v, I'x, or I'y: Qr = Q'u, Q'v , Q′x, or Q′y), the conditional posterior probability that the i-th bit of the transmission symbol is 0, and P (R) is the probability of receiving the received signal R (Ir, Qr). , P (bi = 0∩R) represents the probability that the symbol whose i-th bit is 0 is transmitted and the received signal R (Ir, Qr) is received, respectively.
[0137]
Similarly, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained when the reception signal R (Ir, Qr) is received by the following equation (4).
P (bi = 1 | R) = P (bi = 1∩R) / P (R) (4)
[0138]
Here, P (bi = 1 | R) is the conditional posterior probability that the i-th bit of the transmission symbol is 1 when the received signal R (Ir, Qr) is received, and P (R) is the received signal. The probability of receiving R (Ir, Qr), P (bi = 1∩R), is the probability that the symbol whose i-th bit is 1 is transmitted and the received signal R (Ir, Qr) is received, respectively. Represents.
[0139]
Also according to the following equation (5), when the received signal R (Ir, Qr) is received, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained.
P (bi = 1 | R) = 1-P (bi = 0 | R) (5)
[0140]
The metric calculation circuits 102-1 to 102-4 calculate metrics for the first to fourth bits constituting 16QAM from the input I component Ir and Q component Qr, respectively.
The metric P (b1 = 0 | R) for the first bit is u,
The metric P (b2 = 0 | R) for the second bit is v,
The metric P (b3 = 0 | R) for the third bit is x,
The metric P (b4 = 0 | R) for the fourth bit is y
Output as.
[0141]
The calculation of each metric is performed according to the above-described equation (3). That is,

[0142]
Where P (S_j∩R) is the symbol S_jRepresents the probability that the received signal R is received and ΣP (S_j∩R) means all symbols S whose i-th bit is 0_jThe probability P (S_jRepresents the sum of (R).
[0143]
On the other hand, P (S_k∩R) is the symbol S_kRepresents the probability that the received signal R is received and ΣP (S_k∩R) means all symbols S defined in 16QAM_kThe probability P (S_kRepresents the sum of (R).
[0144]
In the metric calculation circuit 102-1 of the metric (P (b1 = 0 | R)) for the first bit in FIG. 4, the probability calculation circuit 111-1 sets P (S0000∩R), that is, 0000 of 16QAM. The probability that the corresponding symbol S0000 is transmitted and the received signal R is received is calculated.
[0145]
The probability calculation circuit 111-2 calculates a probability that a symbol S0001 corresponding to P (S0001∩R), that is, 0001 of 16QAM is transmitted and the reception signal R is received.
[0146]
The probability calculation circuit 111-3 calculates a probability that a symbol S0010 corresponding to P (S0010∩R), that is, 0010 of 16QAM is transmitted and the reception signal R is received.
[0147]
Similarly, the probabilities are calculated for the remaining 16QAM symbols, and a total of 16 probability calculation results are obtained.
[0148]
The adder circuit 112 is a circuit that calculates the numerator of Expression (8), and a symbol whose first bit is 0, that is,
S0000, S0001, S0010, S0011,
S0100, S0101, S0110, S0111,
Find the sum of the probabilities for.
[0149]
The adder circuit 113 is a block for calculating the denominator of the equation (8), and all 16QAM symbols, that is,
S0000, S0001, S0010, S0011,
S0100, S0101, S0110, S0111,
S1000, S1001, S1010, S1011,
S1100, S1101, S1110, S1111,
Find the sum of the probabilities for.
[0150]
The division circuit 114 is a calculator that divides the output of the addition circuit 112 by the output of the addition circuit 113, and calculates Expression (8).
[0151]
The calculation of the metric for the second bit can be performed similarly. That is, the metric for the second bit is calculated in the metric calculation circuit 102-2. There, as an input to the adder circuit (not shown) of the metric calculation circuit 102-2 corresponding to the adder circuit 112 that calculates the numerator of equation (8), the probability calculation result for each symbol is All symbols whose 2 bits are 0, ie,
S0000, S0001, S0010, S0011,
S1000, S1001, S1010, S1011,
Select the calculation result of the probability for and add. As an input to the adder circuit (not shown) of the metric calculation circuit 102-2 corresponding to the adder circuit 113 that calculates the denominator of Equation (8), all symbols, That is,
S0000, S0001, S0010, S0011,
S0100, S0101, S0110, S0111,
S1000, S1001, S1010, S1011,
S1100, S1101, S1110, S1111,
Select the calculation result of the probability for and add.
[0152]
Similar operations are performed for the third bit and the fourth bit.
[0153]
The operation results u, v, x, and y of the metric calculation circuits 102-1 to 102-4 are supplied to the Viterbi decoder 103.
[0154]
In the multiplication circuit 141-1 shown in FIG. 6, a product of metrics u, v, x, and y (probability that the first to fourth bits are 0) is calculated and output as a branch metric BM0000. This branch metric BM0000 corresponds to the code output 0000 of the convolutional encoder 2.
[0155]
Similarly, the multiplier circuit 141-2 calculates the product of the metrics u, v, and x (probability that the first to third bits are 0) and the metric y ′ (probability that the fourth bit is 1). And is output as the branch metric BM0001. This branch metric BM0001 corresponds to the code output 0001 of the convolutional encoder 2.
[0156]
The multiplier circuit 141-3 includes metrics u, v, and y (probability that the first bit, second bit, and fourth bit are 0) and metric x ′ (probability that the third bit is 1). And outputs as branch metric BM0010. This branch metric BM0010 corresponds to the code output 0010 of the convolutional encoder 2. Similarly, the multiplication circuit 141-8 calculates a product of metrics u ′, v ′, x ′, y ′ (probability that the first to fourth bits are 1), and outputs the product as branch metric BM1111. To do. The branch metric BM1111 corresponds to the encoded output 1111 of the convolutional encoder 2.
[0157]
The ACS circuit 142-1 calculates the following two expressions according to the state transition of the convolutional encoder 2 (FIG. 3).
SM000 × BM0000 (9)
SM001 × BM1111 (10)
[0158]
Here, SM000 is the value of the state metric storage device 143-1 one unit time ago, SM001 is the value of the state metric storage device 143-2 one unit time ago, BM0000 is the operation result of the multiplication circuit 141-1, BM1111 represents the calculation result of the multiplication circuit 141-8.
[0159]
Then, the ACS circuit 142-1 selects the one with the higher likelihood, that is, the one with the larger calculation result from the above equations (9) and (10), and sends the selection information SEL 000 to the path memory 144 in the subsequent stage. In addition to outputting, the larger one of the results obtained by calculating Expression (9) and Expression (10) is supplied to the subsequent state metric storage device 143-1 and stored therein. That is, if the calculation result of Expression (9) is larger, SEL000 = 0, and if the calculation result of Expression (10) is larger, SEL000 = 1. In the former case, SM000 × BM0000 is stored, and in the latter case, SM001 × BM1111 is stored in the state metric storage device 143-1 as a new state metric SM000.
[0160]
This calculation will be described with reference to FIG. There are two paths that reach the state 000, and the first is a path in which 0 is input in the state 000 and outputs 0000. The calculation expression to be compared is as shown in Equation (9), and the second is in the state 001. In a path in which 0 is input and 1111 is output, a calculation expression to be compared is as shown in Expression (10). The larger one of the calculation results is supplied to the state metric storage device 143-1 as a new state metric SM000.
[0161]
A similar operation is performed in the ACS circuits 142-2 to 142-8. Note that the state metric storage devices 143-1 to 143-8 are reset to 0 at the initial stage when the system operates. This control is performed via a terminal 61 from a control device (not shown).
[0162]
The path memory 144 selects, stores, and propagates input data, that is, decoded data, using selection information SEL000 to SEL111 from the ACS circuits 142-1 to 142-8 according to the state transition diagram of FIG.
[0163]
Next, the operation of the path memory 144 will be described with reference to FIG.
[0164]
The selection information SEL000 through SEL111 output from the ACS circuits 142-1 through 142-8 are input to terminals 150-1 through 150-8 and supplied as control signals to the selectors in each column.
[0165]
The selectors 151-1 to 151-4 in the first column receive 0 as two inputs, and the selectors 151-5 to 151-8 receive 1 as two inputs. . Accordingly, 0 is output from the selectors 151-1 to 151-4 regardless of the state of the selection information, and 1 is output from the selectors 151-5 to 151-8. As shown in FIG. 3, such a configuration corresponds to all 0s being input in the paths from state 000 to state 011 and all 1s being input in the paths to state 100 to state 111. doing.
[0166]
Data output from the selectors 151-1 to 151-8 is supplied to and stored in the subsequent registers 152-1 to 152-8.
[0167]
The data output from the registers 152-1 to 152-8 is supplied to the selectors 153-1 to 153-8 in the second column. That is, the selector 153-1 is supplied with the output of the register 152-1 and the register 152-2 in the previous row, and the selector 153-2 is supplied with the output of the register 152-3 and the output of the register 152-4. The selector 153-3 receives the output of the register 152-5 and the output of the register 152-6, and the selector 153-8 receives the output of the register 152-7 and the output of the register 152-8. Yes. The selectors 153-4 to 153-7 are as described above.
[0168]
Each of the selectors 153-1 to 153-8 selects one of the two inputs according to the state of the selection information SEL000 to SEL111, and outputs the selected one to the subsequent registers 154-1 to 154-8. For example, when the selection information SEL000 is 0, the selector 153-1 selects the output of the register 152-1, and when the selection information SEL000 is 1, the selector 152-2 selects the output of the register 152-2. And output.
[0169]
The same processing is applied to the registers in the third column and the last column, and either one of the two inputs from the previous stage is selected and output to the subsequent stage register according to the state of the selection information SEL000 to SEL111. The
[0170]
Data output from the registers 158-1 to 158-8 in the last column is input to the selector 159. The selector 159 selects any one of the data output from the registers 158-1 to 158-8 according to the output from the minimum value comparison circuit 160, and outputs the selected data. That is, the minimum value comparison circuit 160 selects the minimum state metric from the state metrics SM000 to SM111 output from the state metric storage circuits 143-1 to 143-8 shown in FIG. 6, and outputs the corresponding data. . For example, when the state metric SM000 is minimum, data 000 is output. The selector 159 selects and outputs one of the outputs of the registers 158-1 to 158-8 according to the data output from the minimum value comparison circuit 160. For example, when the output data from the minimum value comparison circuit 160 is 000, the selector 159 selects and outputs the output of the register 158-1. When the output data is 001 to 111, the registers 158-2 to 158-8 are selected, respectively.
[0171]
In other words, in the path memory 144, data corresponding to the path with the highest likelihood is output as final decoded data from the eight stored decoded data. The “maximum likelihood path” is a path corresponding to the one having the minimum value among the eight state metrics SM000 to SM111, and the selector 159 corresponds to the path corresponding to the minimum value of the state metric at that time. That is, the path with the highest likelihood is selected.
[0172]
In FIG. 5, various calculation methods are conceivable as calculation methods in the probability calculation circuits 111-1 to 111-16 depending on the transmission path. For example, when a Gaussian transmission path is assumed, for example, the probability calculation circuit 111- In 1, the probability can be calculated as follows.

[0173]
Here, σ represents the square root of ½ of the noise power of the transmission line. That is, 2σ²Represents the noise power of the transmission line. || S0000-R || is the Euclidean distance between the symbols S0000 and R.
[0174]
The probability calculation circuits 111-2 to 111-16 can similarly calculate the probability.
[0175]
FIG. 8 shows a second embodiment of the data receiving apparatus. In this embodiment, the order of the bit despreading circuit and the metric calculation circuit is reversed compared to the case in FIG. Other configurations are the same as those in FIG.
[0176]
The I ′ and Q ′ components of the received signal output from the symbol despreading circuit 33 are input to the metric calculation circuit 120, and after the metric calculation is performed, the metric data u ′, v ′, x ′, y ′. Are supplied to the bit despreading circuits 95-1 to 95-8, respectively. The bit despreading circuits 95-1 to 95-8 perform the reverse operation to that in the bit spreading circuits 91-1 to 91-8 shown in FIG.
[0177]
Other configurations are the same as those in FIG.
[0178]
Next, the operation will be described. In this embodiment, the I ′ and Q ′ components of the received signal output from the symbol despreading circuit 33 are input to the metric calculation circuit 120, and the metrics corresponding to the first to fourth bits are calculated. It is made like that.
[0179]
That is, the metric calculation circuit 120 in FIG. 8 is configured as shown in FIG. 9, for example. In this embodiment, the I ′ and Q ′ components output from the symbol despreading circuit 33 are input to the probability calculation circuits 111-1 to 111-16. The adder circuits 112-1 to 112-8 are circuits that calculate the numerator of the above equation (8), and the adder circuit 112-1 calculates the sum of the probabilities for the 0 symbol of the first bit and adds them. The circuits 112-2 to 112-8 calculate the sum of the probabilities of 0 symbols of the second to third bits, respectively. The adder circuit 113 is a circuit that calculates the denominator of the above equation, and calculates the sum of probabilities for all symbols of 16QAM. The division circuits 114-1 to 114-8 divide the outputs of the addition circuits 112-1 to 112-8 by the outputs of the addition circuit 113, respectively, and calculate the metrics for the first bit to the fourth bit, respectively. , And output as output signals u ′, v ′, x ′, and y ′, respectively.
[0180]
Data (metric) u ′, v ′, x ′, y ′ output from the metric calculation circuit 120 is supplied to the bit despreading circuits 95-1 to 95-8, respectively. The bit despreading circuits 95-1 to 95-8 operate on the metric data u ′, v ′, x ′, y ′ output from the metric calculation circuit 120 for the bit spreading circuits 91-1 to 91- of FIG. The bit despreading is executed by the reverse operation to that in the case of 8, and data u, v, x, y are output.
[0181]
Other operations in the embodiment of FIG. 8 are the same as those in FIG.
[0182]
FIG. 10 shows a third embodiment of the data receiving apparatus. In this embodiment, the I component and the Q component of the reception signal output from the demodulation circuit 32 are supplied to the metric calculation circuit 120, and the metric data u ′, v ′, x obtained by executing the metric calculation. ', Y' is output to the symbol despreading circuit 140. The symbol despreading circuit 140 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 1, that is, a process for returning the order of the symbols replaced in the symbol spreading circuit 7 to the original order, and outputs the data u ″. , V ″, x ″, y ″.
[0183]
The data u ″, v ″, x ″, y ″ output from the symbol despreader 140 are supplied to the bit despreading circuits 95-1 to 95-8, and the bit spreading circuit 91-1 in FIG. Processes opposite to those in 91 to 8 are executed, and the obtained data u, v, x, and y are output. The other configuration is the same as that in FIG. 8, and the description thereof is omitted.
[0184]
Next, the operation will be described.
[0185]
The I component and Q component of the reception signal output from the demodulator 32 are supplied to the metric calculation circuit 120. The metric calculation circuit 120 calculates metrics for the first to fourth bits constituting 16QAM from the input I component and Q component,
The metric for the first bit is u ',
The metric for the second bit is v ',
The metric for the third bit is x ',
The metric for the fourth bit is y '
Output as.
[0186]
The metric calculation circuit 120 has the same configuration as the metric calculation circuit 120 in FIG. 8 (FIG. 9).
[0187]
The metric calculation results u ′, v ′, x ′, y ′ for the first to fourth bits constituting 16QAM are input to the symbol despreading circuit 140.
[0188]
In the symbol despreading circuit 140, an operation reverse to that in the symbol spreading circuit 7 shown in FIG. 1 is performed, and the symbol despreading is performed. In other words, despreading uses Si (u ′, v ′, x ′, y ′) as one set, and (N−1) sets of Si data corresponding to the symbol diffusion circuit 7 shown in FIG. Vector to
From (S1, S2, ..., Sn, ..., SN-1),
Despreading vector with S′i (u ″, v ″, x ″, y ″) as one set and (N−1) sets of S′i as elements.
(S′1, S′2,..., S′k,..., S′N−1).
[0189]
At this time, Sn = S′k (n = G ^ k mod N).
[0190]
The obtained data u ″, v ″, x ″, y ″ are supplied to the bit despreading circuits 95-1 to 95-8, respectively.
[0191]
The bit despreading circuits 95-1 to 95-8 perform bit despreading by the reverse operation of the case of the bit spreading circuits 91-1 to 91-8 in FIG. , Y are output to the Viterbi decoder 103.
[0192]
The subsequent processing is the same as in FIG.
[0193]
As described above, in any of the embodiments, a bit metric is calculated for each bit of data, and bit insertion processing is performed according to a predetermined rule for the data bit. A convolutional code is used as the code, bit spreading is performed on the code sequence, and data transmitted after data modulation in the 16QAM system can be subjected to soft decision processing. Compared with the case where the hard decision processing is performed as the closest symbol, the decoding processing can be performed accurately.
[0194]
In the above embodiment, as the Viterbi decoder 103, the configuration including the multiplication circuits 141-1 to 141-8 as shown in FIG. 6 is used, but these multiplication circuits 141-1 to 141-8 are For example, it is possible to calculate the input data log and multiply the obtained value by (−1).
[0195]
In the above embodiment, the data is modulated and demodulated by the 16QAM system. In addition to this, multilevel multiphase modulation in which the I component and the Q component each correspond to two or more bits such as 64QAM and 256QAM. Even when the method is adopted, the present invention can be applied.
[0196]
【The invention's effect】
  According to the first invention of the present application, it is possible to reliably decode data transmitted after being digitally modulated by the multi-value multi-phase method.
[0197]
According to the second invention of the present application, the configuration of the data receiving apparatus can be simplified.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a data transmission device.
FIG. 2 is a block diagram showing an example of a detailed configuration of a convolutional encoder 2 shown in FIG.
FIG. 3 is a diagram showing transition of the state of the convolutional encoder 2 shown in FIG. 2;
FIG. 4 is a block diagram showing a configuration of a first embodiment of a data receiving apparatus of the present invention.
5 is a block diagram illustrating a detailed configuration example of a metric calculation circuit illustrated in FIG. 4;
6 is a block diagram showing a detailed configuration example of the Viterbi decoder shown in FIG. 4;
7 is a block diagram showing a detailed configuration example of a path memory 144 shown in FIG. 6. FIG.
FIG. 8 is a block diagram showing a configuration of a second embodiment of the data receiving apparatus of the present invention.
FIG. 9 is a block diagram illustrating a detailed configuration example of the metric calculation circuit illustrated in FIG. 8;
FIG. 10 is a block diagram showing a configuration of a third embodiment of the data receiving apparatus of the present invention.
FIG. 11 is a block diagram illustrating a configuration example of a conventional data transmission apparatus.
12 is a block diagram illustrating a configuration example of a convolutional encoder in FIG. 11. FIG.
FIG. 13 is a diagram for explaining state transition of the convolutional encoder in FIG. 12;
FIG. 14 is a diagram for explaining signal point arrangement of QPSK;
FIG. 15 is a block diagram illustrating a configuration example of a conventional data receiving apparatus.
16 is a block diagram illustrating a configuration example of the Viterbi decoder of FIG. 15;
17 is a block diagram illustrating a configuration example of a branch metric calculation circuit in FIG. 16;
18 is a block diagram illustrating a configuration example of the path memory in FIG. 16;
FIG. 19 is a block diagram illustrating a configuration example of a data transmission apparatus when 16QAM is used.
FIG. 20 is a diagram for explaining 16QAM signal point arrangement;
FIG. 21 is a diagram illustrating a configuration example of a data receiving apparatus that receives data transmitted by the apparatus in FIG. 19;
22 is a diagram for explaining the operation of the embodiment of FIG. 21;
[Explanation of symbols]
32 demodulator, 33 symbol despreading circuit, 38 reproduction information, 101-1 to 101-4 bit despreading circuit, 102-1 to 102-4 metric calculation circuit, 103 Viterbi decoder, 111-1 to 111-16 probability Calculation circuit, 112, 113 addition circuit, 114 division circuit

Claims (6)

A convolutional code is used as the error correction code, and a bit spreading process is performed on the code sequence to perform bit spreading on each of the data corresponding to the bits constituting the symbol according to a rule according to the bit constituting the corresponding symbol. In a data receiving apparatus for receiving data transmitted by being digitally modulated by a multi-value multi-phase method,
The information associated with the symbols of the data, and despreading means for despreading each according opposite rule of the rule corresponding to the bits constituting the symbol,
And metric calculating means for calculating from the information associated with the symbol despread respectively, the conditional posterior probability against the bits constituting the symbol, as the metric corresponding to the bit by the despreading means,
A data receiving apparatus comprising: a decoding unit that performs a decoding process on an output of the metric calculation unit. The data receiving apparatus according to claim 1, further comprising symbol despreading means for despreading the data symbols. A convolutional code is used as the error correction code, and a bit spreading process is performed on the code sequence to perform bit spreading on each of the data corresponding to the bits constituting the symbol according to a rule according to the bit constituting the corresponding symbol. In a data receiving apparatus for receiving data transmitted by being digitally modulated by a multi-value multi-phase method,
For each bit of the data, conditional posterior probability for the value 0 or one of the conditional posterior probability for the values 1 only calculated as metric, from one value and a predetermined reference value above and the other metrics A metric calculation means for calculating,
Bit despreading means for despreading the metric calculated by the metric calculation means;
A data receiving apparatus comprising: decoding means for decoding data obtained as a result of despreading by the bit despreading means. The data receiving apparatus according to claim 3, further comprising symbol despreading means for despreading the data symbols. A convolutional code is used as the error correction code, and a bit spreading process is performed on the code sequence to perform bit spreading on each of the data corresponding to the bits constituting the symbol according to a rule according to the bit constituting the corresponding symbol. In a data reception method for receiving transmission data transmitted by being digitally modulated by a multi-value multi-phase method,
Despreading step that the information associated with the symbols of the data, despread each according opposite rule of the rule corresponding to the bits constituting the symbol,
The information associated with the symbol despread each in the process of the despreading step, a metric calculation step of calculating the conditional posterior probability against the bits constituting the symbol, as the metric corresponding to the bit,
And a decoding step of performing a decoding process on the processing result of the metric calculation step. A convolutional code is used as the error correction code, and a bit spreading process is performed on the code sequence to perform bit spreading on each of the data corresponding to the bits constituting the symbol according to a rule according to the bit constituting the corresponding symbol. In a data reception method for receiving data transmitted by being digitally modulated by a multi-value multi-phase method,
For each bit of the data, conditional posterior probability for the value 0 or one of the conditional posterior probability for the values 1 only calculated as metric, from one value and a predetermined reference value above and the other metrics A metric calculation step to calculate,
A bit despreading step for despreading the metric calculated in the processing of the metric calculation step;
And a decoding step for decoding the data obtained as a result of the despreading in the bit despreading step.

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