JP3685564B2 - Method for manufacturing printed circuit board for semiconductor package - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a printed wiring board for a semiconductor package comprising two conductor layers, and more particularly to a method for manufacturing a printed wiring board by build-up having a layer having a via hole by a laser and a photo via using a photosensitive resin. Is.
[0002]
[Prior art]
In recent years, with the advancement of electronic technology, high-density mounting is progressing for electronic devices such as personal computers and mobile phones. Even under such circumstances, even small packages such as QFP and TSOP that have been developed for surface mounting are facing limitations in the trend of increasing the number of pins and narrowing the pitch. Bare chip mounting is attracting attention as the ultimate form of downsizing, but bare chip can reduce package cost, but KGD (known-good-die) compensation method, inspection cost and bare chip repairability (Repairability) and handling are not accelerated. Therefore, research and development of a chip scale package (hereinafter referred to as CSP) that packages a chip to approximately the same size as the chip is particularly active and attracts attention.
[0003]
In order to realize the CSP, it is necessary to shorten the wiring from the flip chip electrode to the board mounting surface of the motherboard, and to secure a lattice pitch that can be connected to the motherboard by reflow connection. That is, there is a demand for a technique for expanding the minimum-sized lattice pitch realized by flip chip with the most efficient wiring until it can be mounted on a printed wiring board. In addition, it is an indispensable condition that a glass base epoxy resin printed wiring board can be used as a mother board to be mounted in consideration of application to general consumer equipment.
[Problems to be solved by the invention]
[0004]
Unlike the technique of wire bonding of the fine gold wires conventionally used in QFP and TSOP when connecting the flip chip electrode and the package side electrode, the flip chip side electrode is used to shorten the wiring length as described above. It is necessary to wire to the package side by vertical wiring. For this purpose, the mounting reliability of the flip chip must be considered, and the package side electrode must be parallel and at the same height with respect to the flip chip electrode, that is, coplanarity is required. However, it is difficult to make uniform bumps with high yield by using the solder, indium alloy, silver, and gold bumps that have been proposed so far. There are many problems such as up. In addition, this joint may be subjected to thermal stress due to temperature and humidity conditions due to the difference in thermal expansion coefficient between the flip chip and the mother board, which may cause distortion, cracking, and disconnection.
[0005]
In the present invention, since the package side electrode is formed by etching a metal foil such as a copper foil, the fillet shape caused by the etching factor as shown in FIG. 1 can absorb the thermal stress. Moreover, since metal foil itself, such as copper foil, becomes an electrode, the thickness is very uniform and coplanarity can be sufficiently satisfied. Also, by using an anisotropic conductive film or anisotropic conductive paste for connection to LSI electrodes, it is possible to connect together without creating electrode bumps using gold as in the past, and underfill injected after connection Since no agent is required, the cost can be reduced. The underfill agent is an adhesive for connecting the chip and the substrate, and has a role of maintaining mechanical strength and improving reliability. In the present invention, the binder resin used in the anisotropic conductive film or anisotropic conductive paste used for connection serves as the underfill. Therefore, the anisotropic conductive film or anisotropic conductive paste to be used is preferably a low-temperature curable or photo-curable low stress type.
[0006]
[Means for Solving the Problems]
The present invention relates to a first conductive layer made of a metal body existing in and on a via hole of an insulating resin layer provided with a via hole, and a photosensitive insulating layer formed on the surface opposite to the metal body of the insulating resin layer. A second conductive layer formed by electroless plating on a photo via provided in the conductive resin layer, and an anisotropic conductive film provided on the insulating resin layer and the first conductive layer. A method for manufacturing a printed circuit board for a semiconductor package is provided.
[0007]
A process for manufacturing the printed circuit board for a semiconductor package of the present invention will be described below.
First, an insulating resin capable of forming via holes by laser is applied to the metal foil so as to have a thickness of 10 to 200 μm, and the via holes are formed by laser. As the metal foil, electrolytic copper foil, aluminum foil and the like having good electrical conductivity can be used, and the thickness is 10 to 100 μm, preferably 35 to 70 μm. If the thickness is less than 10 μm, the strength is weak, and there are drawbacks in handling such as the formation of wrinkles when forming an insulating resin. If it exceeds 100 μm, it cannot be thinned. An excimer laser, a carbon dioxide laser, plasma, or the like can be used as a laser for forming the via hole. As described above, by using the laser system, the first layer of the insulating resin material has a wide range of material choices for the heat resistant resin including the epoxy resin.
[0008]
Next, a plating resist is attached to the metal foil side, and copper is grown to the thickness of the insulating layer in the laser via hole prepared earlier by electrolytic plating. In this case, not only copper but also gold, solder alloy, tin, and the like are possible, but electrolytic copper plating is preferable from the viewpoint of cost and electrical reliability.
[0009]
And the photosensitive resin layer used as a 2nd conductor layer is formed on this insulating layer. In order to increase the adhesion, the surface of the insulating resin layer is polished. The polishing method may be any of mechanical methods such as buffling polishing and belt sander, or micro-roughening with chemicals.
[0010]
As a method for forming the photosensitive resin, screen printing, curtain coater, roll coater, dip coater or the like can be used. Alternatively, a film-like photosensitive resin can be formed by a laminate method. However, the photosensitive resin used in the present invention is preferably developable with an aqueous alkaline solution, and can be roughened with permanganic acid for electroless plating, and further electroless plated. Such materials are described in Japanese Patent Application No. 6-291729, Japanese Patent Application No. 6-293517, and the like.
[0011]
Next, the photosensitive resin layer is exposed to light using a pattern film and developed to form a via hole. Next, after roughening the surface, a second conductor layer is formed by electroless plating, thereby obtaining electrical connection with the first conductor layer. This plating is not limited to electroless plating, and efficiency can be improved by combining electrolytic plating. Here, the plating resist attached to the metal foil of the first layer is peeled off, and an etching resist is formed to form circuit patterns on both surfaces. Then, a circuit is formed by etching. Finally, an anisotropic conductive film is formed on the first layer circuit formed from the metal foil. Solder resist is screen-printed on the second circuit layer side, and solder balls are formed at predetermined positions. The semiconductor package substrate thus obtained has a simple structure and simple processes. Further, since the second circuit layer is formed by the additive method, a high number of layers can be achieved.
[0012]
FIG. 1 is a schematic sectional view showing a use state of a printed circuit board for a semiconductor package according to the present invention, wherein 11 is an anisotropic conductive film, 20 is a solder resist, 21 is an electrode formed by etching a metal foil, and 22 is formed thereon. It is the formed insulating resin. 23 is an electrode of the LSI chip, 25 is electrolytic plated copper, 26 is a photosensitive resin, and 28 is electroless plated copper.
[0013]
2 (1) to (13) are manufacturing process diagrams of the semiconductor package printed circuit board. An example of the present invention will be described in the order of the manufacturing process. (1) Using 35 μm electrolytic copper foil 1 as the metal foil, applying an epoxy resin varnish as insulating resin 2 to the anti-gloss surface using a comma coater so that the thickness after drying is 50 μm, and drying and curing did. (2) A 50 μm via hole 3 was formed by an excimer laser. Thereafter, a dry film-like plating resist 4 was pasted on the glossy surface of the electrolytic copper foil, leaving only a portion to be an electrode for electrolytic plating. (3) Copper 5 having the same thickness as the insulating resin layer was deposited by electrolytic plating. (4) After polishing the surface once with baffle, the photosensitive resin 6 was printed by screen printing to a thickness of 30 μm and heated at 80 ° C. for 15 minutes to make it tack free.
[0014]
(5) Next, it exposed by irradiating 1000mJ UV light using the pattern film. Next, development was performed with a 1% aqueous sodium hydroxide solution to form via holes 7 having a diameter of 75 μm. (6) The surface of the photosensitive resin layer 6 in which the via hole was formed in this way was dipped in a 5% permanganate aqueous solution adjusted to be alkaline with 2.5% sodium hydroxide and subjected to chemical roughening. The liquid temperature at this time was 60 degreeC. After washing with water, a palladium catalyst was attached, and after activation with an accelerator, electroless copper plating was performed to obtain a 3 μm-thick circuit, and an 18 μm conductor was obtained thereon by electrolytic copper plating. (7) Here, the plating resist 4 formed in the step (2) was peeled off. (8) Next, a photocurable liquid type etching resist 9 was formed on both surfaces, and exposed and developed using a pattern film. (9) A circuit was created by etching. The first layer side electrode 1a was wired at a pitch of 0.5 mm, and the second layer side electrode 8a was wired at a pitch of 1.0 mm. The etching resist was peeled off, washed with water and dried. (10) Thereafter, the thermosetting solder resist 10 was printed and cured on one side by screen printing to form a resist layer on both sides. (11) The anisotropic conductive film 11 was temporarily pressure-bonded to the circuit side of the first layer formed by etching in order to connect the electrode part obtained on the first layer side to the semiconductor chip. An anisotropic conductive paste may be applied instead of the anisotropic conductive film. (12) The LSI electrode 23 and the first layer circuit electrode 1a were electrically connected through the anisotropic conductive film 11. (13) The second layer 8a on the opposite surface was formed with bumps of solder balls 12 (192 pieces) at a predetermined position by an existing method.
[0015]
The printed circuit board for a semiconductor package thus obtained can provide a 7 mm square semiconductor chip having a 192 pin electrode with a pitch of 0.5 mm as a 14 mm square package.
[0016]
【The invention's effect】
Even small packages such as QFP and TSOP are facing limitations in the trend toward higher pin count and narrow pitch. Bare chip mounting is attracting attention as the ultimate form of miniaturization, but bare chip can reduce the cost of the package, but bare chip from the viewpoint of KGD compensation method and its inspection cost, bare chip repairability and handling The transition to is difficult. According to the present invention, it is possible to use a CSP that packages a chip in substantially the same size as the chip. According to the printed circuit board for a semiconductor package and the manufacturing method thereof according to the present invention, it is possible to reduce the size of a 192-pin package with a size of 14 mm square.
[0017]
By using both the laser via method and the photo via method, the insulating resin material of the first layer can be selected from a wide range of materials such as epoxy resin and heat resistant resin. In the present invention, since the package side electrode is formed by etching the copper foil of the copper clad laminate as the core material, the fillet shape caused by the etching factor can absorb the thermal stress. Further, since the copper foil itself of the copper clad laminate is an electrode, the thickness is very uniform, and the coplanarity is sufficiently satisfied.
[0018]
Also, by using an anisotropic conductive film or anisotropic conductive paste for connection to LSI electrodes, it is possible to connect together without creating electrode bumps using gold as in the past, and underfill injected after connection Since no agent is required, the cost can be reduced. The underfill agent is an adhesive for connecting the chip and the substrate, and has a role of maintaining mechanical strength and improving reliability. In the present invention, the binder resin used in the anisotropic conductive film or anisotropic conductive paste used for connection serves as the underfill. Therefore, the anisotropic conductive film or anisotropic conductive paste to be used is preferably a low-temperature curable or photo-curable low stress type.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a usage state of a printed circuit board for a semiconductor package. FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the printed circuit board for a semiconductor package.
DESCRIPTION OF SYMBOLS 1 Copper foil 1a 1st conductor circuit 2 Insulating resin 3 Laser via 4 Plating resist 5 Electrolytic plating copper 6 Photosensitive resin 7 Photo via 8 Electroless plating copper 8a Second conductive circuit 9 Etching resist 10 Solder resist 11 Anisotropic conductive Film or anisotropic conductive paste 12 Solder ball 20 Solder resist 21 Fillet electrode 22 Insulating resin 23 LSI electrode 25 Electrolytic plating copper 26 Photosensitive resin 28 Electroless plating copper

Claims (1)

(1) a step of forming a via in the insulating resin layer formed on the metal foil by laser; (2) a step of applying a plating resist on the surface of the metal foil where the resin layer is not formed; (3) step (1 (4) forming a conductor by plating in the via formed in (4), and (4) photosensitive insulating property capable of photovia on the first conductor layer made of the metal foil and the conductor formed by plating formed in the above step. A step of forming a resin, (5) a step of forming a photo via in the photosensitive resin layer, (6) a step of roughening the photosensitive resin layer, and (7) a second conductivity by plating on the photosensitive resin layer. A step of connecting and forming the body layer with the first conductor layer formed in step (3), (8) a step of peeling off the plating resist layer formed in step ( 2 ), and (9) in this way. Etching resist on both sides of the formed structure (10) a step of forming a circuit by etching on both surfaces, (11) a step of forming a solder resist layer on the second conductor layer formed by etching, (12) a second step of forming by etching Forming an anisotropic conductive film on one conductor layer; (13) joining the circuit of the first conductor layer and the electrode of the LSI chip so as to be electrically connected via the anisotropic conductive film; And (14) forming a solder ball on the circuit of the second conductor layer formed by etching, and a method of manufacturing a printed circuit board for a semiconductor package.

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