JP3686396B2 - Stream processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a stream processing apparatus that handles a plurality of streams.
[0002]
[Prior art]
  In recent years, video, audio, and data are often broadcasted, transmitted, and stored as digital data. For example, in digital TV broadcasts, DVDs, digital VTRs, digital video cameras, IEEE 1394, etc., data such as video signals, audio signals, data broadcasts, and EPGs are broadcasted, transmitted, processed, and stored as a stream. There are various data formats for these streams. For example, in digital TV broadcasting and digital VTR, a transport stream defined in the MPEG system standard is used. In DVD, a program stream defined in the MPEG system standard is used. The DV format is used when recording data of a digital video camera is transmitted on the IEEE 1394 bus. A unique process is required for each of these data formats.
[0003]
  Under such circumstances, digital AV devices have appeared that have not only a single function but also a plurality of functions. For example, in a digital TV receiver having an IEEE 1394 interface, “receive and display a broadcast program”, “receive a broadcast program and record it on an external storage device connected via the IEEE 1394 bus” ”,“ Reproduce and display a program from an external storage device connected via the IEEE 1394 bus ”. The stream input to the digital TV receiver is “broadcast program stream” and “program stream played from an external storage device connected via the IEEE1394 bus” and is output. The stream is “a stream of a program to be recorded on an external storage device connected via the IEEE 1394 bus”. In this way, a plurality of streams are input / output.
[0004]
[Problems to be solved by the invention]
  The digital TV receiver is provided with a transport decoder as an LSI for processing a stream. A stream input / output interface LSI (for example, IEEE 1394 interface LSI) that supplies a stream input from the outside to the transport decoder and outputs the stream processed by the transport decoder to the outside is different from the transport decoder. It is provided as an LSI. The connection between these LSIs on the printed board is optimized according to the application system. However, it is impossible to envisage all future usage methods, and the future application range is limited by assumptions at the time of system design.
[0005]
  Recently, integration of LSIs has progressed, and it has become possible to mount a transport decoder and a stream input / output interface in one LSI. For this reason, it has become necessary to assume the application range of the LSI in which the LSI continues to be used and the functions realized in the system using the LSI when designing the LSI.
[0006]
  On the other hand, with the progress of video / audio digitization and networking, the types of stream input / output interfaces have increased and the number of streams that must be processed simultaneously has also increased. In addition, the processing content of the stream has been diversified.
[0007]
  An object of the present invention is to provide a stream processing apparatus capable of improving the degree of freedom of the configuration of an apparatus having a function of processing a plurality of streams.
[0008]
[Means for Solving the Problems]
  The stream processing apparatus according to the present invention comprises selection means and first to fifth processing means. The selecting means associates a plurality of inputs with a plurality of outputs according to external control, and provides a stream given to each of the plurality of inputs to the corresponding output. The first processing means gives the first stream to the first input among the plurality of inputs. The second processing means gives the second stream to the second input among the plurality of inputs. The third processing means receives a stream from the first output among the plurality of outputs. The fourth processing means receives a stream from the second output among the plurality of outputs. The fifth processing means receives a stream from the third output among the plurality of outputs, performs a predetermined process on the received stream, and selects the stream subjected to the process from the plurality of inputs. To the third input.The selection means multiplexes at least two of the plurality of outputs into a new output.
[0009]
  Preferably, the selection unit associates the plurality of inputs with the plurality of outputs on a one-to-one basis.
[0010]
  In the stream processing apparatus, by controlling the selection means, the stream from the first processing means is supplied to one of the third and fourth processing means, and the stream from the second processing means is supplied to the third and fourth streams. To the other of the processing means. Further, by controlling the selection means, a stream from one of the first and second processing means is given to one of the third and fourth processing means, and from the other of the first and second processing means. The stream after being provided to the fifth processing means and processed by the fifth processing means may be provided to the other of the third and fourth processing means.It is also possible to output a plurality of streams from one system output.As described above, since the assignment between the stream input to the selection means and the third to fifth processing means can be freely changed, the degree of freedom of the configuration of the apparatus having the function of processing a plurality of streams is improved. Can be made.
[0011]
  Preferably, the selection means associates one of the plurality of inputs with two of the plurality of outputs.
[0012]
  In the stream processing apparatus, by controlling the selection means, the stream from the first processing means is given to one of the third and fourth processing means and the fifth processing means, and the processing is performed by the fifth processing means. Can be provided to the other of the third and fourth processing means. The stream from the first processing means can also be provided to the third and fourth processing means.
[0013]
  Preferably, the fifth processing means extracts desired information from the received stream to generate a partial stream, and provides the generated partial stream to a third input of the plurality of inputs.
[0014]
  Preferably, at least one of the third processing unit and the fourth processing unit converts the received stream and outputs the converted stream.
[0015]
  Preferably, at least one of the first stream and the second stream includes video data and / or audio data. At least one of the third processing unit and the fourth processing unit decodes video data and / or audio data included in the received stream.
[0016]
  Preferably, the fifth processing means extracts desired video data and / or audio data from the received stream, and supplies the extracted video data and / or audio data to a third input of the plurality of inputs. .
[0017]
  Preferably, at least one of the first stream and the second stream is encrypted. The fifth processing means releases the encryption applied to the received stream.
[0018]
  Preferably, the fifth processing means encrypts the received stream.
[0019]
  Another stream processing apparatus according to the present invention comprises selection means and first to sixth processing means. The selecting means associates a plurality of inputs with a plurality of outputs according to external control, and provides a stream given to each of the plurality of inputs to the corresponding output. The first processing means gives a first stream to a first input of the plurality of inputs. The second processing means gives a second stream to a second input of the plurality of inputs. The third processing means receives a stream from the first output among the plurality of outputs. The fourth processing means receives a stream from a second output among the plurality of outputs. The fifth processing means is the above-mentioned A stream from a third output of the plurality of outputs is received, a predetermined process is performed on the received stream, and the stream subjected to the process is given to a third input of the plurality of inputs. At least one of the first stream and the second stream is encrypted by a first encryption method. The fifth processing means releases the encryption applied to the received stream. The sixth processing means receives the stream from the fourth output of the plurality of outputs, encrypts the received stream by the second encryption method, and encrypts the encrypted stream in the plurality of inputs. Give to 4 input.
[0020]
  Yet another stream processing apparatus according to the present invention comprises selection means, first to fifth processing means, and storage means. The selecting means associates a plurality of inputs with a plurality of outputs according to external control, and provides a stream given to each of the plurality of inputs to the corresponding output. The first processing means gives a first stream to a first input of the plurality of inputs. The second processing means gives a second stream to a second input of the plurality of inputs. The third processing means receives a stream from the first output among the plurality of outputs. The fourth processing means receives a stream from a second output among the plurality of outputs. The fifth processing means receives a stream from the third output among the plurality of outputs, performs a predetermined process on the received stream, and selects the stream subjected to the process from the plurality of inputs. To the third input. At least one of the third processing means and the fourth processing means writes the received stream to the storage means, and stores the write position in the storage means of the stream written to the storage means. At least one of the first processing means and the second processing means reads the stream from the storage means, stores the read position in the storage means of the stream read from the storage means, and gives the read stream to the corresponding input .
[0021]
  Preferably, at least one of the first processing means and the second processing means streams from the storage means with reference to a write position stored in at least one of the third processing means and the fourth processing means. Is read.
[0022]
  Preferably, at least one of the third processing means and the fourth processing means refers to a read position stored in at least one of the first processing means and the second processing means, and stores in the storage means. The stream is written in an area other than the area where the stream that has not been read yet is stored.
[0023]
  Yet another stream processing apparatus according to the present invention comprises selection means, first to fifth processing means, and storage means. The selecting means associates a plurality of inputs with a plurality of outputs according to external control, and provides a stream given to each of the plurality of inputs to the corresponding output. The first processing means gives a first stream to a first input of the plurality of inputs. The second processing means gives a second stream to a second input of the plurality of inputs. The third processing means receives a stream from the first output among the plurality of outputs. The fourth processing means receives a stream from a second output among the plurality of outputs. The fifth processing means receives a stream from the third output among the plurality of outputs, performs a predetermined process on the received stream, and selects the stream subjected to the process from the plurality of inputs. To the third input. At least one of the third processing unit and the fourth processing unit writes the received stream in the storage unit. At least one of the first processing means and the second processing means reads the stream from the storage means and applies the read stream to the corresponding input. At least one of the first stream and the second stream includes a plurality of packets. Each of the plurality of packets includes identification information for selecting necessity. The fifth processing means generates a first partial stream by extracting a desired packet from the plurality of packets included in the received stream with reference to the identification information, and generates the first partial stream as the plurality of the plurality of packets. To the third input. Third processing means and fourth processing hand At least one of the stages writes the received first partial stream to the storage means. At least one of the first processing means and the second processing means reads the first partial stream from the storage means and applies it to the corresponding input as the second partial stream. At least one of the third processing unit and the fourth processing unit extracts desired information from the received second partial stream.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
[0025]
  (First embodiment)
                      <Overall system configuration>
  FIG. 1 is a block diagram showing the overall configuration of a digital TV receiver system according to a first embodiment of the present invention. The system shown in FIG. 1 includes a digital TV receiver 100, an AVHDD 112, and a digital VTR 113.
[0026]
  The digital TV receiver 100 includes a stream processing device 101, a memory 106, a CPU 107, an AV decoder 108, and a hard disk device 109.
[0027]
  The stream processing apparatus 101 includes tuners 110 and 111, a matrix switch 102, an IEEE 1394 interface 103, a demultiplexer 104, and an HDD interface 105. Tuners 110 and 111 are tuners for receiving digital TV broadcasts, and output received broadcast streams to the matrix switch 102. The stream processing apparatus 101 receives a broadcast stream from the digital TV tuners 110 and 111, a stream from the IEEE 1394 bus B2, and a reproduction stream from the hard disk apparatus 109. The input stream is processed and stored in the memory 106 or output as a processed stream. In addition, the input stream may be output as it is. The stream is output from the stream processing apparatus 101 to the IEEE 1394 bus B2, the hard disk device 109, and the AV decoder 108.
[0028]
  A memory 106 is a main memory of the digital TV receiver 100. The memory 106 is used when the software is executed by the CPU 107 or used for storing data. The memory 106 stores a stream processed by the stream processing apparatus 101.
[0029]
  The AV decoder 108 decompresses and outputs AV data received and reproduced by the digital TV receiver 100.
[0030]
  The hard disk device 109 records a stream output from the stream processing device 101 and outputs an accumulated stream to the stream processing device 101.
[0031]
  The AVHDD 112 is a hard disk device having a function of recording / reproducing a digital AV stream. The AVHDD 112 has an interface with the bus B2, and records a stream input from the bus B2 and outputs a playback stream to the bus B2.
[0032]
  The digital VTR 113 is a VTR device having a digital AV stream recording / reproducing function. The digital VTR 113 records a stream input from the bus B2 and outputs a playback stream to the bus B2.
[0033]
              <Internal configuration of stream processing apparatus 101>
  FIG. 2 is a block diagram showing in detail the configuration of the stream processing apparatus 101 shown in FIG.
[0034]
                  <Matrix switch 102>
  Referring to FIG. 2, matrix switch 102 includes input terminals T0-T7, T20, output terminals T10-T18, switch group 200-208, and switch control register 209.
[0035]
  Input terminals T0 and T1 receive streams from tuners 110 and 111. Input terminals T2 and T3 receive streams from output ports OUT0 and OUT1 of demultiplexer 104. Input terminals T 4 to T 6 receive streams from the output ports OUT 0 to OUT 2 of the IEEE 1394 interface 103. The input terminal T7 receives a stream from the output port OUT0 of the HDD interface 105. The input terminal T20 receives a control signal from the CPU bus B1.
[0036]
  The switch group 200-208 includes switches (00-70)-(08-78). When the switches (00-70)-(08-78) are in the ON state, the streams supplied to the input terminals T0-T7 are supplied to the output terminals T10-T18.
[0037]
  The switch control register 209 gives a control signal to the switch group 200-208 in response to a control signal given from the CPU 107 to the input terminal T20 via the bus B1. The control signal given to the switch group 200-208 is a signal that designates which switch among the switches included in the switch group is to be turned on. Each of the switch groups 200-208 turns on one of the corresponding switches (00-70)-(08-78) in response to a control signal from the switch control register 209. That is, each of the switch groups 200 to 208 selects one of the streams supplied to the input terminals T0 to T7 in response to a control signal from the switch control register 209 and outputs the selected stream to the output terminals T10 to T18.
[0038]
  In the matrix switch 102 configured as described above, each of the output terminals T10 to T18 is associated with one of the input terminals T0 to T7 in accordance with the control signal from the switch control register 209. A stream applied to the input terminal is output from each of the output terminals T10 to T18. That is, each of the eight input streams applied to the input terminals T0 to T7 can be output to any of the nine output terminals T10 to T18.
[0039]
              <IEEE1394 interface 103>
  The IEEE 1394 interface 103 includes three input ports IN0-IN2 and three output ports OUT0-OUT2. Streams from the output terminals T10 to T12 of the matrix switch 102 are given to the input ports IN0 to IN2 of the IEEE1394 interface 103. A stream from the output ports OUT0 to OUT2 of the IEEE1394 interface 103 is supplied to the input terminals T4 to T6 of the matrix switch 102. The IEEE 1394 interface 103 converts the interface format of the stream from the bus B2 and outputs it from the output ports OUT0-OUT2, and converts the stream supplied to the input ports IN0-IN2 to the bus B2 after converting the interface format. .
[0040]
                  <HDD interface 105>
  The HDD interface 105 includes two input ports IN0 and IN1 and one output port OUT0. Streams from the output terminals T18 and T17 of the matrix switch 102 are applied to the input ports IN0 and IN1 of the HDD interface 105. The stream from the output terminal OUT0 of the HDD interface 105 is given to the input terminal T7 of the matrix switch 102. The HDD interface 105 converts the interface format of the stream from the hard disk device 109 and outputs it from the output port OUT0, converts the stream given to the input ports IN0 and IN1 to the hard disk device 109 after converting the interface format. .
[0041]
                    <Demultiplexer 104>
  The demultiplexer 104 includes four input ports IN0 to IN3 and two output ports OUT0 and OUT1. Streams from the output terminals T13 to T16 of the matrix switch 102 are given to the input ports IN0 to IN3 of the demultiplexer 104. Streams from the output ports OUT0 and OUT1 of the demultiplexer 104 are supplied to the input terminals T2 and T3 of the matrix switch 102. The demultiplexer 104 can simultaneously process four streams provided to the input ports IN0 to IN3. The demultiplexer 104 outputs the processed stream from the output ports OUT0 and OUT1. Also, the data resulting from the demultiplexing process (data extracting process from the stream) is recorded in the memory 106 via the bus B1 or output to the AV decoder 108.
[0042]
                    <Perform multiple processes simultaneously>
  Next, it will be sequentially described that various processes and outputs for various streams can be simultaneously performed in the system configured as described above.
[0043]
                            <Process 1>
  A process (process 1) for temporarily storing the received program in the AVHDD 112 and reproducing / displaying it with a time difference will be described with reference to FIGS. 1, 2, and 3A.
[0044]
  First, a process of extracting a desired program stream from the broadcast stream and storing it in the AVHDD 112 will be described.
[0045]
  A control signal instructing to turn on the switch 03 of the switch group 203 and the switch 20 of the switch group 200 (a stream passes) is supplied from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switches 03 and 20 to the switch groups 203 and 200. In response to this, the switches 03 and 20 are turned on.
[0046]
  The broadcast stream (encrypted stream) received by the tuner 110 is applied to the input terminal T0 of the matrix switch 102, passes through the switch 03, is output from the output terminal T13, and is input to the input port IN0 of the demultiplexer 104. .
[0047]
  The demultiplexer 104 is preset by the CPU 107 so as to decrypt the stream input to the input port IN0 and take out the stream constituting the desired program. The demultiplexer 104 decrypts the encryption of the broadcast stream input to the input port IN0, takes out the stream constituting the desired program, and outputs it from the output port OUT0. The stream output from the output port OUT0 of the demultiplexer 104 is given to the input terminal T2 of the matrix switch 102. The stream input to the input terminal T2 passes through the switch 20, is output from the output terminal T10, and is given to the input port IN0 of the IEEE 1394 interface 103. The IEEE 1394 interface 103 sends this stream to the AVHDD 112 via the bus B2. The AVHDD 112 stores this stream.
[0048]
  Next, a process for sequentially reading out program streams stored in the AVHDD 112 and performing a time difference reproduction of received programs will be described.
[0049]
  In addition to the switch 03 of the switch group 203 and the switch 20 of the switch group 200, a control signal for instructing to turn on the switch 44 of the switch group 204 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switch 44 to the switch group 204 in addition to the switches 03 and 20. In response to this, the switch 44 is turned on in addition to the switches 03 and 20.
[0050]
  In addition to the above settings, the demultiplexer 104 is further set by the CPU 107 to extract AV data from the stream input from the input port IN1 and output it to the AV decoder 108.
[0051]
  Thereafter, the program stream stored in the AVHDD 112 is sequentially read out and supplied from the output port OUT0 of the IEEE1394 interface 103 to the input terminal T4 of the matrix switch 102. The stream supplied to the input terminal T4 passes through the switch 44, is output from the output terminal T14, and is input to the input port IN1 of the demultiplexer 104. The demultiplexer 104 extracts AV data constituting the program and supplies it to the AV decoder 108. In this way, AV playback of the playback program is performed. As described above, the received program is temporarily stored in the AVHDD 112 and is played back / displayed with a time difference.
[0052]
                            <Process 2>
  Next, a process (process 2) for dubbing a program stream from the digital VTR 113 to the external hard disk device 109 will be described with reference to FIGS. 1, 2, and 3B. Process 2 is performed in parallel with process 1 described above.
[0053]
  A control signal instructing to turn on the switch 58 of the switch group 208 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switch 58 to the switch group 208. In response to this, the switch 58 is turned on. In addition, the IEEE 1394 interface 103 is set so that a playback stream from the digital VTR 113 is output from the output port OUT1. Further, the HDD interface 105 is set so that the stream given to the input port IN0 is stored in the hard disk device 109.
[0054]
  When the digital VTR 113 is reproduced after the above setting, the reproduced stream is given from the output port OUT1 of the IEEE1394 interface 103 to the input terminal T5 of the matrix switch 102 and passes through the switch 58 as shown in FIG. Then, it is given from the output terminal T 18 to the input terminal IN 0 of the HDD interface 105 and stored in the hard disk device 109.
[0055]
  Since the passage route in the matrix switch 102 of the stream in the process 2 is different from the passage route in the process 1, the process 2 can be performed simultaneously with the process 1.
[0056]
                            <Process 3>
  Next, a process of extracting a program stream from another received broadcast and recording it on the hard disk device 109 (Process 3) will be described with reference to FIGS. 1, 2 and 3C. Process 3 is performed in parallel with the first and process 2 described above.
[0057]
  A control signal instructing to turn on the switch 15 of the switch group 205 and the switch 37 of the switch group 207 is supplied from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switches 15 and 37 to the switch groups 205 and 207. In response, switches 15 and 37 are turned on.
[0058]
  The broadcast stream received by the tuner 111 is applied to the input terminal T1 of the matrix switch 102, passes through the switch 15, is output from the output terminal T15, and is input to the input port IN2 of the demultiplexer 104.
[0059]
  The demultiplexer 104 is set in advance by the CPU 107 so as to extract a stream constituting a desired program. The demultiplexer 104 extracts a stream constituting a desired program from the broadcast stream input to the input port IN2, and outputs it from the output port OUT1. The stream output from the output port OUT1 of the demultiplexer 104 is supplied to the input terminal T3 of the matrix switch 102. The stream input to the input terminal T3 passes through the switch 37, is output from the output terminal T17, and is given to the input port IN1 of the HDD interface 105. The HDD interface 105 stores this stream in the hard disk device 109.
[0060]
  Since the passage route in the matrix switch 102 of the stream in the processing 3 is different from the passage routes in the processing 1 and the processing 2 described above, the processing 3 can be performed simultaneously with the first and processing 2.
[0061]
                            <Process 4>
  Next, a case where the data broadcast information stored in the hard disk device 109 is taken out, placed in the memory 106 and processed by the CPU 107 (processing 4) will be described with reference to FIGS. 1, 2, and 3D. . Process 4 is performed in parallel with the first to third processes described above.
[0062]
  A control signal instructing to turn on the switch 76 of the switch group 206 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switch 76 to the switch group 206. In response to this, the switch 76 is turned on. Further, the demultiplexer 104 is set by the CPU 107 so that the data broadcast information is extracted from the stream supplied to the input port IN3 and stored in the memory 106.
[0063]
  The HDD interface 105 takes out data broadcast information stored in advance in the hard disk device 109 and supplies it from the output port OUT0 to the input terminal T7 of the matrix switch 102. The stream supplied to the input terminal T7 passes through the switch 76 and is supplied from the output terminal T16 to the input port IN3 of the demultiplexer 104. The demultiplexer 104 extracts the data broadcast information from the stream supplied to the input port IN3 according to the setting and stores it in the memory 106. Thereby, the CPU 107 can refer to and process the data broadcast information stored in the memory 106.
[0064]
  Since the passage route in the matrix switch 102 of the stream in the process 4 is different from the passage route in the process 1 to the process 3 described above, the process 4 can be performed simultaneously with the process 1 to the process 3.
[0065]
            <Multiple processes for one stream>
  Next, it will be described that a plurality of processes and outputs can be performed on one stream in the system shown in FIG.
[0066]
                          <Case 1>
  First, a case (case 1) in which AV playback processing of a broadcast program and processing of storing audio data of the program in the memory 106 are performed at the same time will be described with reference to FIGS. 1, 2, and 4A.
[0067]
  A control signal instructing to turn on the switch 03 of the switch group 203 and the switch 04 of the switch group 204 is supplied from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switches 03 and 04 to the switch groups 203 and 204. In response to this, the switches 03 and 04 are turned on. Further, the demultiplexer 104 is set by the CPU 107 so that AV data of the program to be viewed is extracted from the stream supplied to the input port IN0 in the PES packet format and output to the AV decoder 108. Further, the demultiplexer 104 is set so that the audio data of the program to be viewed is taken out as an elementary stream from the stream supplied to the input port IN1 and stored in the memory 106.
[0068]
  The broadcast stream from the tuner 110 is given to the input terminal T0 of the matrix switch 102. This stream passes through the switch 03 and is given from the output terminal T13 to the input port IN0 of the demultiplexer 104. The demultiplexer 104 extracts AV data to be viewed from this stream in the PES packet format and outputs it to the AV decoder 108. On the other hand, the broadcast stream from the tuner 110 passes through the switch 04 of the matrix switch 102 and is also supplied from the output terminal T14 to the input port IN1 of the demultiplexer 104. The demultiplexer 104 extracts the audio data of the viewing target program from this stream in the elementary stream format and stores it in the memory 106.
[0069]
  In this way, one stream can be branched and a plurality of types of processing can be performed simultaneously.
[0070]
                          <Case 2>
  Next, a case where the same program is recorded on the AVHDD 112 in the transport stream format simultaneously with the AV reproduction of the broadcast program stream will be described with reference to FIGS. 1, 2, and 4B.
[0071]
  A control signal instructing to turn on the switch 03 of the switch group 203, the switch 04 of the switch group 204, and the switch 20 of the switch group 200 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switches 03, 04, 20 to the switch groups 203, 204, 200. In response to this, the switches 03, 04, and 20 are turned on. Further, the demultiplexer 104 is set by the CPU 107 so that AV data of the program to be viewed is extracted from the stream supplied to the input port IN0 in the PES packet format and output to the AV decoder 108. Further, the demultiplexer 104 is set so that the program stream to be viewed is extracted from the stream supplied to the input port IN1 and is output from the output port OUT0 in the transport stream format. Further, the IEEE 1394 interface 103 is set so as to record the stream given to the input port IN0 in the AVHDD 112.
[0072]
  The broadcast stream from the tuner 110 is given to the input terminal T0 of the matrix switch 102. This stream passes through the switch 03 and is given from the output terminal T13 to the input port IN0 of the demultiplexer 104. The demultiplexer 104 extracts AV data to be viewed from this stream in the PES packet format and outputs it to the AV decoder 108. On the other hand, the broadcast stream from the tuner 110 passes through the stream switch 04 of the matrix switch 102 and is input from the output terminal T15 to the input port IN1 of the demultiplexer 104. The demultiplexer 104 extracts the viewing target program from this stream as a transport stream and outputs it from the output port OUT0. The stream output from the output port OUT0 of the demultiplexer 104 is supplied to the input terminal T2 of the matrix switch 102, passes through the switch 20, and is supplied from the output terminal T10 to the input port IN0 of the IEEE1394 interface 103. The IEEE 1394 interface 103 records this stream in the AVHDD 112 via the bus B2.
[0073]
  In this way, a plurality of types of processing can be performed simultaneously by branching one input stream.
[0074]
                          <Other processing>
  Next, a process for extracting a program stream from the received broadcast, releasing the broadcast encryption applied to the program stream, applying the encryption for hard disk recording, and recording it on the hard disk device 109 will be described with reference to FIG. This will be described with reference to FIGS.
[0075]
  A control signal instructing to turn on the switch 15 of the switch group 205, the switch 26 of the switch group 206, and the switch 37 of the switch group 207 is given from the CPU 107 to the switch control register 209 of the matrix switch 102. In response to this, the switch control register 209 gives a control signal for turning on the switches 15, 26 and 37 to the switch groups 205, 206 and 207. In response to this, the switches 15, 26 and 37 are turned on. The broadcast stream received by the tuner 111 is applied to the input terminal T1 of the matrix switch 102, passes through the switch 15, is output from the output terminal T15, and is input to the input port IN2 of the demultiplexer 104.
[0076]
  The demultiplexer 104 takes out the stream constituting the program to be recorded from the stream input from the input port IN2 and releases the broadcast encryption, and records the hard disk on the stream input from the input port IN3. Is set in advance by the CPU 107 so as to be encrypted.
[0077]
  The demultiplexer 104 extracts a stream constituting a desired program from the broadcast stream input to the input port IN2, releases the broadcast encryption applied to the stream, and outputs it from the output port OUT0.
[0078]
  The stream output from the output port OUT0 of the demultiplexer 104 is given to the input terminal T2 of the matrix switch 102. The stream input to the input terminal T2 passes through the switch 26, is output from the output terminal T16, and is input to the input port IN3 of the demultiplexer 104.
[0079]
  The demultiplexer 104 applies encryption for hard disk recording to the stream input to the input port IN3 and outputs it from the output port OUT1.
[0080]
  The stream output from the output port OUT1 of the demultiplexer 104 is supplied to the input terminal T3 of the matrix switch 102. The stream input to the input terminal T3 passes through the switch 37, is output from the output terminal T17, and is given to the input port IN1 of the HDD interface 105. The HDD interface 105 stores this stream in the hard disk device 109.
[0081]
  In this manner, the input stream is de-broadcasted by the demultiplexer 104 and input to the demultiplexer 104 again via the matrix switch 102. Then, the hard disk recording encryption process is performed in the demultiplexer 104 and is again stored in the hard disk device 109 from the hard disk interface 105 via the matrix switch 102.
[0082]
                              <Effect>
  As described above, in the system according to the first embodiment, a plurality of streams can be processed in parallel, or input streams can be directly output. In addition, the system configuration can be freely changed according to the switch settings in the matrix switch 102.
[0083]
  Note that the number of input / output ports of the matrix switch 102, the IEEE 1394 interface 103, and the HDD interface 105 is not limited to the above-described number, and can be freely set according to a required system configuration. In addition, other types of stream input / output interfaces and stream processing circuits are not excluded.
[0084]
  (Second Embodiment)
                      <Overall system configuration>
  FIG. 6 is a block diagram showing the overall configuration of a digital TV receiver system according to the second embodiment of the present invention. The system shown in FIG. 6 includes a digital TV receiver 500, an AVHDD 112, and a digital video camera 508.
[0085]
  The digital TV receiver 500 includes a stream processing device 501, a memory 106, a CPU 107, an Ethernet (R) interface 507, and a DVD drive device 509.
[0086]
  The stream processing device 501 includes a tuner 111, a matrix switch 502, an IEEE 1394 interface 503, a demultiplexer 504, an AV decoder 505, an HDD interface 105, and a DMA circuit 506. The stream processing device 501 receives a broadcast stream from the tuner 111, a stream from the bus B2, and a reproduction stream from the DVD drive device 509. The input stream is processed and stored in the memory 106 or output as a processed stream. In addition, the input stream may be output as it is. Further, the stream can be accumulated in the memory 106, or the stream can be read from the memory 106 and input. The stream is output from the stream processing device 501 to the bus B2 / DVD drive device 509.
[0087]
  The DVD drive device 509 records a stream output from the stream processing device 501 and outputs an accumulated stream to the stream processing device 501.
[0088]
  The Ethernet (R) interface 507 accumulates data received via the Ethernet (R) in the memory 106 and transmits data in the memory 106 to the Ethernet (R).
[0089]
  The digital video camera 508 reproduces the recorded AV stream via the bus B2, and records the AV stream input via the bus B2.
[0090]
            <Internal configuration of stream processing apparatus 501>
  FIG. 7 is a block diagram showing in detail the configuration of the stream processing apparatus 501 shown in FIG.
[0091]
                  <Matrix switch 502>
  Referring to FIG. 7, matrix switch 502 includes input terminals T30-T37, T50, output terminals T40-T48, a group of switches 600-608, and a switch control register 609.
[0092]
  The input terminal T30 receives a stream from the output port OUT0 of the DMA circuit 506. The input terminal T31 receives a stream from the tuner 111. Input terminals T32 and T33 receive streams from output ports OUT0 and OUT1 of demultiplexer 504. Input terminals T34 to T36 receive streams from the output ports OUT0 to OUT2 of the IEEE1394 interface 503. The input terminal T37 receives a stream from the output port OUT0 of the HDD interface 105. Input terminal T50 receives a control signal from bus B1.
[0093]
  The switch group 600 includes switches 00-30 and 70. When the switches 00-30 and 70 are in the ON state, the streams supplied to the input terminals T30 to T33 and T37 are supplied to the output terminal T40. The switch group 601 includes switches 01-31 and 71. When the switches 01-31 and 71 are in the ON state, the streams supplied to the input terminals T30 to T33 and T37 are supplied to the output terminal T41. Switch group 602 includes switches 02-72. When the switch 02-72 is in the ON state, the stream supplied to the input terminals T30 to T37 is supplied to the output terminal T42. Switch group 603 includes switches 13-73. When the switch 13-73 is in the ON state, the switch 13-73 supplies the stream supplied to the input terminals T31-T37 to the output terminal T43. The switch group 604 includes switches 04, 14, and 44-74. When the switches 04, 14, and 44-74 are in the ON state, the streams supplied to the input terminals T30, T31, and T34 to T37 are applied to the output terminal T44. The switch group 605 includes switches 05, 15, and 45-75. When the switches 05, 15, and 45-75 are in the ON state, the streams supplied to the input terminals T30, T31, and T34 to T37 are supplied to the output terminal T45. The switch group 606 includes switches 06, 16, and 46-76. When the switches 06, 16, and 46-76 are in the ON state, the streams provided to the input terminals T30, T31, and T34 to T37 are applied to the output terminal T46. Switch group 607 includes switches 07-67. When the switches 07-67 are in the ON state, the streams supplied to the input terminals T30-T36 are supplied to the output terminal T47. Switch group 608 includes switches 08-68. When the switches 08-68 are in the ON state, the streams supplied to the input terminals T30 to T36 are supplied to the output terminal T48.
[0094]
  In the switch group 600-608 shown in FIG. 7, some switches are omitted as compared to the switch group 200-208 shown in FIG. This is because a switch that does not allow a stream to pass through such as outputting a stream input from the IEEE 1394 interface 503 to the IEEE 1394 interface 503 is omitted.
[0095]
  The switch control register 609 gives a control signal to the switch group 600-608 in response to a control signal given from the CPU 107 to the input terminal T50 via the bus B1. The control signal given to the switch group 600-608 is a signal that designates which switch among the switches included in the switch group is to be turned on. The switch group 600-608 turns on one of the switches in response to a control signal from the switch control register 609. That is, the switch group 600-608 selects one of the streams given to the input terminals T30-T37 and outputs it to the output terminals T40-T48.
[0096]
  In the matrix switch 502 configured as described above, eight input streams given to the input terminals T30 to T37 can be output to designated ones of the nine output terminals T40 to T48, respectively.
[0097]
            <IEEE1394 interface 503>
  The IEEE 1394 interface 503 includes two input ports IN0 and IN1 and three output ports OUT0 to OUT2. Streams from the output terminals T40 and T41 of the matrix switch 502 are applied to the input ports IN0 and IN1 of the IEEE1394 interface 103. A stream from the output ports OUT0 to OUT2 of the IEEE1394 interface 503 is supplied to input terminals T34 to T36 of the matrix switch 502. The IEEE 1394 interface 503 converts the interface format of the stream from the bus B2 and outputs the stream from the output ports OUT0 to OUT2, and converts the stream supplied to the input ports IN0 and IN1 to the bus B2 after converting the interface format. .
[0098]
                  <HDD interface 105>
  The HDD interface 105 includes two input ports IN0 and IN1 and one output port OUT0. Streams from the output terminals T48 and T47 of the matrix switch 502 are given to the input ports IN0 and IN1 of the HDD interface 105. The stream from the output terminal OUT0 of the HDD interface 105 is given to the input terminal T37 of the matrix switch 502. The HDD interface 105 converts the interface format of the stream from the DVD drive device 509 and outputs it from the output port OUT0, converts the stream given to the input ports IN0 and IN1 to the DVD drive device 509 by converting the interface format. Output.
[0099]
                    <Demultiplexer 504>
  The demultiplexer 504 includes three input ports IN1-IN3 and two output ports OUT0 and OUT1. A stream from the output terminals T44 to T46 of the matrix switch 502 is supplied to the input ports IN1 to IN3 of the demultiplexer 504. Streams from the output ports OUT0 and OUT1 of the demultiplexer 504 are applied to the input terminals T32 and T33 of the matrix switch 502. The demultiplexer 504 can simultaneously process three streams provided to the input ports IN1-IN3. The demultiplexer 504 outputs the processed stream from the output ports OUT0 and OUT1. Further, data resulting from the demultiplexing process (data extracting process from the stream) is recorded in the memory 106 via the bus B1.
[0100]
                        <DMA circuit 506>
  The DMA circuit 506 includes an input port IN0 and an output port OUT0. A stream from the output terminal T43 of the matrix switch 502 is applied to the input port IN0 of the DMA circuit 506. The stream from the output port OUT0 of the DMA circuit 506 is given to the input terminal T30 of the matrix switch 502. The DMA circuit 506 writes the stream supplied to the input port IN0 to the memory 106 via the bus B1, and stores the write position of the stream in the memory 106, and the stream written to the memory 106 via the bus B1. The data is read out and output from the output port OUT0, and the read position of the stream in the memory 106 is stored.
[0101]
                          <Various processing>
  Next, a case where various processes are performed on various streams in the system illustrated in FIG. 6 will be described.
[0102]
                            <Process 1>
  First, the case where video / audio reproduced from the digital video camera 508 is decoded and reproduced by the AV decoder 505 will be described with reference to FIGS. 6, 7 and 8A.
[0103]
  A control signal instructing to turn on the switch 53 of the switch group 603 and the switch 02 of the switch group 602 is supplied from the CPU 107 to the switch control register 609. In response to this, the switch control register 609 gives a control signal for turning on the switches 53 and 02 to the switch groups 603 and 602. In response to this, the switches 53 and 02 are turned on. Further, the address of the data storage area in the memory 106 is set in the DMA circuit 506, and the stream is read from the data storage area in response to a data request from the AV decoder 505 while storing the input stream in this data storage area. The DMA circuit 506 is set in the above.
[0104]
  The video / audio stream output from the digital video camera 508 to the bus B2 is input to the IEEE 1394 interface 503, and is input from the output port OUT1 to the input terminal T35 of the matrix switch 502. This stream passes through the switch 53 and is input from the output terminal T43 to the input port IN0 of the DMA circuit 506. The DMA circuit 506 writes this stream into the data storage area in the memory 106. At this time, the DMA circuit 506 refers to the read position of the stream in the memory 106 so that the stream is not written in the area where the stream that has not yet been read is stored. That is, the stream is written to an area other than the area in the memory 106 where the stream that has not been read is stored.
[0105]
  When a data request is issued from the AV decoder 505, the DMA circuit 506 reads the stream accumulated in the data accumulation area in the memory 106 and applies it from the output port OUT0 to the input terminal T30 of the matrix switch 502. At this time, the DMA circuit 506 refers to the stream write position in the memory 106 and reads the stream from the area where the stream is already stored. This stream passes through the stream switch 02, is transferred from the output terminal T42 to the input port IN0 of the AV decoder 505, and is subjected to AV decoding processing by the AV decoder 505 to be displayed and reproduced.
[0106]
                            <Process 2>
  Next, a case where demultiplex processing is performed on a stream received via Ethernet (R) and taken out by the CPU 107 will be described with reference to FIGS. 6, 7, and 8 (b).
[0107]
  A control signal instructing to turn on the switch 04 of the switch group 604 is given from the CPU 107 to the switch control register 609. In response to this, the switch control register 609 gives a control signal for turning on the switch 04 to the switch group 604. In response to this, the switch 04 is turned on. Further, the demultiplexer 504 is set so that the demultiplex processing is performed on the stream supplied to the input port IN 1 and the processing result is accumulated in the memory 106. Further, the DMA circuit 506 is set so that the stream is read from the reception stream accumulation area in the memory 106 and output from the output port OUT0.
[0108]
  Packets received by the Ethernet (R) interface 507 are stored in the Ethernet (R) data receiving area of the memory 106 via the bus B1. The CPU 107 processes this Ethernet (R) packet, extracts a desired stream from the packet, and stores it in the received stream storage area of the memory 106.
[0109]
  The DMA circuit 506 reads the stream accumulated in the reception stream accumulation area of the memory 106 and inputs the stream from the output port OUT0 to the input terminal T30 of the matrix switch 502. This stream passes through the switch 04 and is input from the output terminal T44 to the input port IN1 of the demultiplexer 504. The demultiplexer 504 performs demultiplex processing on the input stream and accumulates the resultant data in the memory 106.
[0110]
  In this way, a stream received by an interface such as Ethernet (R) that is not a normal stream interface can be demultiplexed.
[0111]
                            <Process 3>
  Next, FIG. 6, FIG. 7 and FIG. 8 (c) show processing for extracting the program table processed by the software of the digital TV receiver 500 and the decryption key data from the broadcast stream (transport stream) received by the tuner 111. ) Will be described.
[0112]
  First, the data format of the transport stream and the demultiplexing process for this will be described. The transport stream is composed of a series of transport stream packets. The transport stream packet is a packet having a length of 188 bytes and stores various digital broadcast data. Data stored in the transport packet is mainly divided into PES (Packetized Elementary Stream) packets and section data. The PES packet stores video and audio data (elementary data) constituting a broadcast program. The section data stores a program table to be processed by software of the digital TV receiver, decryption key data, and the like. Each transport stream packet is given a packet identifier (PID). The packet identifier (PID) indicates the type of data stored, that is, whether it is video, audio or program guide. Furthermore, header information is at the head of the section data. In the header information, information such as a more detailed type and content update status regarding the content of the section data is embedded.
[0113]
  The demultiplexer 504 identifies the PID of the input transport stream packet, determines whether it is the elementary stream of the program to be received or the section data to be received, and selects in units of transport stream packets (PID filter processing) is performed. Next, a PES packet and section data are extracted from the transport stream packet. The extracted section data is further subjected to a sorting process (section filter process) based on the header information of the section data. The general processing content of the section filter processing is to compare the 16-byte header portion of the section data with 32 types of condition data to determine whether there is a match. The selected PES packets and section data are temporarily stored in the memory 106 for each type, and then the PES packets, that is, video and audio data are decompressed by the AV decoder 505 and reproduced. On the other hand, the section data is processed by software, the program guide is extracted and the decryption key data is extracted, and the operation of the digital TV receiver 500 is controlled based on this.
[0114]
  In general, the data rate of a transport stream in digital TV broadcasting is about 30 Mbps (20000 packets / second), and it is necessary to execute demultiplex processing in real time at this data rate. In particular, the section filtering process needs to be executed a maximum of 10 times for one transport stream packet. That is, it is necessary to perform comparison processing of 32 types × 16 bytes (comparison processing of a total of 100 Mbytes or more) for (20,000 packets × 10) section data per second.
[0115]
  In the second embodiment, the PID filter processing and the section filter processing of the demultiplex processing are performed in two steps instead of being performed in real time.
[0116]
  First, the demultiplexer 504 retrieves elementary data to be received by PID filter processing and stores it in the memory 106. On the other hand, the demultiplexer 504 generates a partial transport stream in which only the transport stream packet having the PID of the section data to be received is left out of the input transport stream, and temporarily stores it in the memory 106. The partial transport stream temporarily stored is sequentially taken out from the memory 106 and input to the demultiplexer 504 again, and section filtering is performed at this time.
[0117]
  Generally, a data rate of 30 Mbps of a transport stream of digital TV broadcasting is configured such that 1-2 Mbps is section data and the rest is elementary data. That is, the average data rate of the partial transport stream composed of only the section data to be received extracted by the PID filter processing is at most 1 to 2 Mbps. As a result, the capacity of the comparison processing required for the section filter processing is reduced to 1/30 to 1/15 compared with the case where the transport stream received as described above is processed in real time. As a result, the circuit scale is reduced, and section filtering by software becomes possible.
[0118]
  Hereinafter, the operation of the above-described two-stage demultiplex processing will be specifically described. Here, the average data rate of the section data to be received in the transport stream received from the broadcast is 1 Mbps.
[0119]
  A control signal instructing to turn on the switch 15 of the switch group 605, the switch 23 of the switch group 603, and the switch 04 of the switch group 604 is supplied from the CPU 107 to the switch control register 609. In response to this, the switch control register 609 gives a control signal for turning on the switches 15, 23 and 04 to the switch group 604. In response to this, the switches 15, 23 and 04 are turned on. For the stream input from the input port IN2, only the packet including the section data to be received is extracted by the PID filter processing, a partial transport stream including only this packet is generated, and this is output from the output port OUT0. Thus, the demultiplexer circuit 504 is set. In addition, the demultiplexer 504 is set so that the section data is selected and stored in the memory 106 for the stream input from the input port IN1. Also, the address of the data storage area in the memory 106 is set in the DMA circuit 506, the stream applied to the input port IN0 is stored in this area, and this stored data is read at a low speed (1 Mbps) and output from the output port OUT0. Thus, the DMA circuit 506 is set.
[0120]
  The stream received by the tuner 111 is input to the input terminal T31 of the matrix switch 502, passes through the switch 15, and is input from the output terminal T45 to the input port IN2 of the demultiplexer 504. The demultiplexer 504 extracts only packets including section data from this stream by PID filter processing, generates a partial transport stream including only section data, and outputs this from the output port OUT0. Since the average data rate of the section data to be received is 1 Mbps, the data rate of this partial stream is an average of 1 Mbps. This partial stream is given to the input terminal T32 of the matrix switch 502, passes through the switch 23, and is inputted from the output terminal T43 to the input port IN0 of the DMA circuit 506. The DMA circuit 506 temporarily stores the input partial stream in a data storage area in the memory 106. At the same time, when a stream is accumulated in the data accumulation area, the DMA circuit 506 reads this stream at a low speed (1 Mbps) and outputs it from the output port OUT0. This stream passes through the switch 04 of the matrix switch 502 and is input from the output terminal T44 to the input port IN1 of the demultiplexer 504. The demultiplexer 504 performs section data extraction and section filtering on the stream input to the input port IN1, and records the processing result data in a predetermined area of the memory 106.
[0121]
  Thus, after temporarily storing a stream in order to perform section filter processing that does not require real-time processing, it can be processed again as a low-speed stream.
[0122]
  Since demultiplex processing is performed in two stages as described above, the circuit scale of a circuit that performs section filter processing can be reduced, and section filter processing by software can be performed.
[0123]
  Here, the partial transport stream stored in the memory 106 is read out by the DMA circuit 506 at a low speed. Instead, the demultiplexer 504 issues a data request, and the DMA circuit 506 responds accordingly by the DMA circuit 506. Alternatively, the partial transport stream may be read from the internal data storage area and supplied to the demultiplexer 504. That is, an input of a data request signal is provided corresponding to each output terminal of the matrix switch 502, and the data request signal traces the connection of the matrix switch 502 in the opposite direction to the data and sets the input port associated with the output terminal. To the stream supplier. In the above example, a data request signal is output from the input port IN 1 of the demultiplexer 504, and this is input to the DMA circuit 506 from the output port OUT 0 of the DMA circuit 506 via the matrix switch 502. The DMA circuit 506 reads the partial stream stored in the memory 106 in response to the data request signal. The read partial stream is supplied to the input port IN1 of the demultiplexer 504 via the matrix switch 502. By supplying data in response to the data request in this way, it is possible to flexibly perform demultiplex processing even when the data rate of the partial stream to be processed fluctuates.
[0124]
                            <Effect>
  As described above, in the second embodiment, since the DMA circuit 506 that can read and write a stream to and from the memory 106 is provided, data is temporarily accumulated during stream processing, and data processed by the CPU 107 is processed as a stream. And the degree of freedom of system configuration is further improved.
[0125]
  In addition, since the stream is supplied according to the data request signal, the degree of freedom of operation and the types of input / output / processing means that can be combined increase.
[0126]
  The number of input and output ports shown in this embodiment is merely an example, and the present invention is not limited to this. Further, the example in which the data request signal is transferred from the demultiplexer 504 to the DMA circuit 506 has been described. However, the present invention is not limited to this, and can be transferred from all stream supply destinations to the stream supply sources according to the setting of the matrix switch. It is. Furthermore, not only the data request signal but also other control signals can be passed in the same manner.
[0127]
  (Third embodiment)
  In the first and second embodiments, the switch group of the matrix switch selects and outputs one stream from the streams input from the eight input terminals. The switch group of the matrix switch in the third embodiment is characterized in that a plurality of streams can be multiplexed and output.
[0128]
                      <Configuration of switch group>
  FIG. 9 is a block diagram illustrating a configuration of a switch group according to the third embodiment. The configuration other than the switch group is the same as the configuration of the system shown in FIGS. Referring to FIG. 9, each of input streams 0-7 is taken into respective registers 800-807 each time data enable signal 0-7 indicating that there is a valid data input becomes active. The data enable signal 0-7 is input to the multiplex control circuit 808, and the multiplex control circuit 808 manages which register of the registers 800-807 stores data. The multiplex control circuit 808 controls the selector 809 to sequentially select the data stored in the registers 800-807, and outputs an output data enable signal and an output data selection signal. However, an output selection signal is input from the switch control register 609, and it is controlled whether or not multiple outputs are performed for each input. The output data enable signal and the output data selection signal are also input to the output destination instruction circuit 810. In the output destination instruction circuit 810, the correspondence between the input to the switch group and the output destination is designated by the switch control register 609. Based on this correspondence, the output destination instruction circuit 810 outputs an output destination instruction signal. The output destination instruction signal indicates an output destination to which the input signal indicated by the output data selection signal is to be output. As described above, the switch group can multiplex and output the designated one of the plurality of input data, and at the same time, can identify each multiplexed data and output a signal indicating the output destination. In a circuit to which multiplexed output data and an output destination instruction signal are input, the original data is separated from the multiplexed output data with reference to the output destination instruction signal, and individual processing is performed on each data. can do.
[0129]
                        <Operation of switch group>
  An example of an operation timing chart of this switch group is shown in FIG. In this example, data 0, 1, 2, 3 are input, and it is assumed that the switch control register 609 instructs to output data 0, 1, 2 in a multiplexed manner. Also, assume that the switch control register 609 is designated to output data 0 to output destination 1, data 1 to output destination 0, and data 2 to output destination 3. First, when data 0 is input, it is stored in the register 800. At the next clock, the selector 809 selects and outputs data 0. At the same time, the output destination instruction circuit 810 outputs an output destination instruction signal indicating the output destination 1. Next, data 1, 2 and 3 are input simultaneously and written in registers 801-803, respectively. In response to an instruction from the multiplex control circuit 808, these data are output at the same time as the data 1 is output at the next clock and at the same time the data 2 is output at the next clock. An output destination instruction signal indicating the output destination 3 is output. However, data 3 is not output because there is no output instruction from the switch control register 609. By realizing the switch group operating in this way, a plurality of stream inputs can be multiplexed and input as one stream to the AV decoder 505 or the like.
[0130]
  Another example of the operation timing chart of this switch group is shown in FIG. In this example, data 0, 1, 2, 3 are input, and it is assumed that the switch control register 609 instructs to output multiple data 0, 1 among them. In addition, it is assumed that the switch control register 609 is designated so as to branch and output data 0 to output destination 1 and data 1 to output destination 0 and output destination 3. First, when data 0 is input, it is stored in the register 800. At the next clock, the selector 809 selects and outputs data 0. At the same time, the output destination instruction circuit 810 outputs an output destination instruction signal indicating the output destination 1. Next, data 1, 2 and 3 are input simultaneously and written in registers 801-803, respectively. In response to an instruction from the multiplex control circuit 808, data 1 is output at the next clock, and at the same time, an output destination instruction signal indicating the output destination 0 and an output destination instruction signal indicating the output destination 3 are output. However, data 2 and data 3 are not output because there is no output instruction from the switch control register 609. By realizing a switch group that operates in this way, a plurality of stream inputs can be multiplexed to form one stream, and this one stream can be input to an AV decoder 505 that performs individual processing on each of the plurality of streams. Also, two of the three streams input to the AV decoder 505 can be the same stream. That is, branching one stream and executing two types of processing described in the first embodiment can be realized even using a switch group that multiplexes and outputs output data.
[0131]
                  <Functions that can be realized in the system>
  By providing the switch group as described above, the following functions can be realized in the systems shown in FIGS. Here, it is assumed that the AV decoder 505 is capable of receiving an input stream in which a plurality of streams are multiplexed, extracting each of the multiplexed data based on an output destination instruction signal, and decoding it as another AV data.
[0132]
  Explanation will be given on a case where two videos of a playback stream from the digital video camera 508 connected to the bus B2 and a playback stream from the DVD drive device 509 connected to the HDD interface 105 are simultaneously decoded and displayed by the AV decoder 505. To do.
[0133]
  A switch group 609 is set by the CPU 107 and the switch control register 609 so that the switches 42 and 72 are turned on and the stream input from the input terminal T34 and the stream input from the input terminal T37 are multiplexed and output. Further, the IEEE 1394 interface 503 is set so that a playback stream from the digital video camera 508 is output from the output port OUT0. Further, the HDD interface 105 is set so that a playback stream from the DVD drive device 509 is output from the output port OUT0.
[0134]
  The playback stream from the digital video camera 508 is input to the switch 42 from the output port OUT0 of the IEEE1394 interface 503. On the other hand, the playback stream from the DVD drive device 509 is input to the switch 72 from the output port OUT 0 of the HDD interface 105. These two streams are multiplexed by the switch group 602 and input to the input port IN0 of the AV decoder 505. The AV decoder 505 decodes each of the two multiplexed streams and displays both videos.
[0135]
  By configuring and operating as described above, a plurality of streams can be freely connected with only one stream connection as a circuit scale.
[0136]
【The invention's effect】
  As described above, according to the stream processing apparatus of the present invention, the degree of freedom of the configuration of the apparatus having the function of processing a plurality of streams can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a system according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing in detail the configuration of the stream processing apparatus shown in FIG. 1;
FIG. 3A is a diagram for explaining processing for extracting a stream of a desired program from a broadcast stream and storing it in an AVHDD connected to the IEEE 1394 bus. (B) is a diagram for explaining a process of dubbing a program stream from a digital VTR to an external hard disk device. (C) is a figure for demonstrating the process which takes out the program stream from another received broadcast, and records this on a hard-disk device. (D) is a diagram for explaining a case in which data broadcast information stored in a hard disk device is taken out, placed in a memory, and processed by a CPU.
FIG. 4A is a diagram for explaining a case where AV playback of a broadcast program and processing for storing audio data of the program in the memory 106 are performed simultaneously. (B) is a figure for demonstrating the case where the same program is recorded on AVHDD112 with a transport stream format simultaneously with AV reproduction of a broadcast program stream.
FIG. 5: Extracts a program stream from a received broadcast, releases the broadcast encryption applied to the program stream, applies the encryption for recording the hard disk to the program stream, and records it on the hard disk device It is a figure for demonstrating the process to perform.
FIG. 6 is a block diagram showing an overall configuration of a system according to a second embodiment of the present invention.
7 is a block diagram showing in detail the configuration of the stream processing apparatus shown in FIG. 6;
FIG. 8A is a diagram for explaining processing for decoding and reproducing video / audio reproduced from a digital video camera using an AV decoder; (B) is a figure for demonstrating the case where a demultiplex process is performed with respect to the stream which received via Ethernet (R) and taken out by CPU. (C) is a figure for demonstrating the process which takes out the program schedule, the descrambling key data, etc. which the software of a digital TV receiver processes from the broadcast stream which the tuner received.
FIG. 9 is a block diagram showing a configuration of a switch group according to a third embodiment of the present invention.
10 is a timing chart for explaining the operation of the switch group shown in FIG. 9;
11 is a timing chart for explaining the operation of the switch group shown in FIG. 9;
[Explanation of symbols]
101, 501 Stream processing device, 102, 502 Matrix switch, 103, 503 IEEE 1394 interface, 104, 504 Demultiplexer, 105 HDD interface, 106 Memory, 107 CPU, 108, 505 AV decoder, 110, 111 tuner, 200-208, 600-608 switch group, 209, 609 switch control register, 506 DMA circuit, 507 Ethernet (R) interface, 800-807 register, 808 multiple control circuit, 809 data selection circuit.

Claims (14)

Selecting means for associating a plurality of inputs and a plurality of outputs according to control from the outside, and providing a stream provided to each of the plurality of inputs to the corresponding output;
First processing means for providing a first stream to a first input of the plurality of inputs;
Second processing means for providing a second stream to a second input of the plurality of inputs;
Third processing means for receiving a stream from a first output of the plurality of outputs;
Fourth processing means for receiving a stream from a second output of the plurality of outputs;
A stream from a third output of the plurality of outputs is received, a predetermined process is performed on the received stream, and the stream subjected to the process is given to a third input of the plurality of inputs A fifth processing means ,
The selection means includes
A stream processing apparatus, wherein at least two of the plurality of inputs are multiplexed to form one new output . In claim 1,
The selection means includes
A stream processing apparatus, wherein the plurality of inputs and the plurality of outputs are associated one-to-one. In claim 1,
The selection means includes
A stream processing apparatus that associates one of the plurality of inputs with two of the plurality of outputs. In claim 1,
The fifth processing means includes
A stream processing apparatus, wherein desired stream information is extracted from a received stream to generate a partial stream, and the generated partial stream is provided to a third input of the plurality of inputs. In claim 1,
At least one of the third processing means and the fourth processing means is:
A stream processing apparatus, wherein the received stream is converted in its interface format and output. In claim 1,
At least one of the first stream and the second stream is
Including video data and / or audio data,
At least one of the third processing means and the fourth processing means is
A stream processing apparatus that decodes video data and / or audio data included in a received stream. In claim 6 ,
The fifth processing means includes
A stream processing apparatus, wherein desired video data and / or audio data is extracted from a received stream, and the extracted video data and / or audio data is provided to a third input of the plurality of inputs. In claim 1,
At least one of the first stream and the second stream is encrypted;
The fifth processing means includes
A stream processing apparatus for canceling a cipher applied to a received stream. In claim 1,
The fifth processing means includes
A stream processing apparatus for encrypting a received stream. Selection means for associating a plurality of inputs and a plurality of outputs according to control from the outside, and providing a stream given to each of the plurality of inputs to the corresponding output;
First processing means for providing a first stream to a first input of the plurality of inputs;
Second processing means for providing a second stream to a second input of the plurality of inputs;
Third processing means for receiving a stream from a first output of the plurality of outputs;
Fourth processing means for receiving a stream from a second output of the plurality of outputs;
A stream from a third output of the plurality of outputs is received, a predetermined process is performed on the received stream, and the stream subjected to the process is provided to a third input of the plurality of inputs A fifth processing means,
At least one of the first stream and the second stream is encrypted by a first encryption method;
The fifth processing means includes
Remove the encryption applied to the received stream,
The stream processing device includes:
Further comprising sixth processing means,
The sixth processing means includes:
Receiving a stream from a fourth output of the plurality of outputs, encrypting the received stream by a second encryption method, and providing the encrypted stream to a fourth input of the plurality of inputs A characteristic stream processing apparatus. Selection means for associating a plurality of inputs and a plurality of outputs according to control from the outside, and providing a stream given to each of the plurality of inputs to the corresponding output;
First processing means for providing a first stream to a first input of the plurality of inputs;
Second processing means for providing a second stream to a second input of the plurality of inputs;
Third processing means for receiving a stream from a first output of the plurality of outputs;
Fourth processing means for receiving a stream from a second output of the plurality of outputs;
A stream from a third output of the plurality of outputs is received, a predetermined process is performed on the received stream, and the stream subjected to the process is given to a third input of the plurality of inputs Fifth processing means;
Storage means,
At least one of the third processing means and the fourth processing means is:
Write the received stream to the storage means, store the write position in the storage means of the stream written to the storage means,
At least one of the first processing means and the second processing means is:
It reads a stream from the storage unit, stores the read position in said storage means of a stream read from the storage unit, the stream processing apparatus according to claim <br/> providing the read stream to the corresponding input. In claim 11 ,
At least one of the first processing means and the second processing means is:
A stream processing apparatus, wherein a stream is read from the storage unit with reference to a write position stored in at least one of the third processing unit and the fourth processing unit. In claim 11 ,
At least one of the third processing means and the fourth processing means is:
Reference is made to a read position stored in at least one of the first processing means and the second processing means, and an area other than an area in the storage means that is not yet read is stored. A stream processing apparatus for writing a stream. Selection means for associating a plurality of inputs and a plurality of outputs according to control from the outside, and providing a stream given to each of the plurality of inputs to the corresponding output;
First processing means for providing a first stream to a first input of the plurality of inputs;
Second processing means for providing a second stream to a second input of the plurality of inputs;
Third processing means for receiving a stream from a first output of the plurality of outputs;
Fourth processing means for receiving a stream from a second output of the plurality of outputs;
A stream from a third output of the plurality of outputs is received, a predetermined process is performed on the received stream, and the stream subjected to the process is given to a third input of the plurality of inputs Fifth processing means;
Storage means,
At least one of the third processing unit and the fourth processing unit is
Write the received stream to the storage means,
At least one of the first processing means and the second processing means is:
Reads a stream from the storage means, gives the read stream to the corresponding input,
At least one of the first stream and the second stream includes a plurality of packets;
Each of the plurality of packets includes identification information for selecting necessity,
The fifth processing means includes
A desired packet among a plurality of packets included in the received stream is extracted with reference to the identification information to generate a first partial stream, and the first partial stream is extracted from the plurality of inputs. 3 input,
At least one of the third processing means and the fourth processing means is:
Writing the received first partial stream to the storage means;
At least one of the first processing means and the second processing means is:
Reading the first partial stream from the storage means and applying it to the corresponding input as a second partial stream;
At least one of the third processing means and the fourth processing means is:
A stream processing apparatus that extracts desired information from the received second partial stream.

Images