JP3687482B2 - Power-on reset circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power-on reset circuit used for a circuit that needs to be initialized when power is turned on, such as a register that controls the operation of a nonvolatile memory, and more particularly, is incorporated in a semiconductor integrated circuit (IC). The present invention relates to a power-on reset circuit.
[0002]
[Prior art]
In general, a power-on reset circuit is used to output a power-on reset signal for a predetermined period when a device or IC is powered on. This power-on reset signal may be active at a high level or may be active at a low level. Hereinafter, a case where a power-on reset signal that becomes active at a low level is generated in order to initialize the register will be described.
[0003]
An example of a conventional power-on reset circuit is shown in FIG. The source of the P-channel MOS transistor MP11 is connected to the power supply voltage V _CC , and a resistor R11 is connected between the gate and drain (node N11) of the transistor MP11 and the ground potential. The resistor R11 is a leak path for stabilizing the potential V _{N11 of the} node N11. The node N11 is connected to the input terminal of the inverter circuit INV11, and the output terminal of the inverter circuit INV11 is connected to the input terminal of the inverter circuit INV12.
[0004]
The operation of the circuit of FIG. 6 will be described with reference to FIG. Immediately after power-on, the power-on reset signal POR is at a low level, and the register is in a power-on reset state. When the power supply voltage V _CC rises from 0 V after the power is turned on, the potential V _{N11 of the} node N11 starts to rise from the time when the power supply voltage V _CC exceeds the threshold voltage Vt of the transistor MP11. However, the input level of the inverter circuit INV11 is still at a low level. Here, the potential V _N11 of the node N11 has a value that is a voltage drop from the power supply voltage V _{CC by} the threshold voltage Vt of the transistor MP11 (V _N11 = V _CC −Vt). When the potential V _{N11 of the} node N11 exceeds the threshold voltage of the inverter circuit INV11, the outputs of the two inverter circuits INV11 and INV12 are inverted, the power-on reset signal POR becomes high level, and the power-on reset period Ends.
[0005]
[Problems to be solved by the invention]
However, in the conventional power-on reset circuit shown in FIG. 6, if the value of the resistor R11 is increased, the time required to discharge the charge accumulated in the parasitic capacitance of the node N11 to the ground potential becomes longer. When the operation is repeated, the power-on reset period is shortened, and an appropriate power-on reset operation may not be performed. On the other hand, when the value of the resistor R11 is decreased, the length of the power-on reset period is stabilized, but the steady consumption current increases.
[0006]
By the way, Japanese Patent Application Publication No. 5-291915 discloses a power-on reset system that can minimize an increase in LSI chip area and ensure a sufficiently long reset period. . However, since this power-on reset system incorporates the one-shot pulse generator 10 and the timer 14 whose time constant is determined by a resistor and a capacitor, the circuit area and current consumption increase.
[0007]
Japanese Patent Laid-Open No. 8-111089 discloses a power-on reset signal generation circuit capable of obtaining a power-on reset signal having a pulse having a sufficiently long period regardless of the rising speed of an external power supply in an SDRAM. . However, since this power-on reset signal generation circuit also incorporates capacitors C1, 11, 12 and timer T1, the circuit area and current consumption also increase.
[0008]
Accordingly, in view of the above points, the present invention provides a power-on reset circuit that does not use an element with a large area such as a capacitor, has a small steady-state current consumption, and a stable power-on reset period. With the goal.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a power-on reset circuit according to the present invention includes a first signal generation circuit that generates a first output signal in response to a power supply voltage exceeding a first potential, and the power supply A second output signal is generated in response to the power supply voltage exceeding a second potential higher than the first potential, and is connected between a node generating a voltage and a ground potential, and the second output signal is generated. A second signal generation circuit including switch means for turning on / off the output signal, and a power-on reset that inputs the first output signal and the second output signal and outputs a power-on reset signal A signal generation circuit that activates the power-on reset signal as the power supply voltage rises, and is in an active state until the second output signal is generated after the first output signal is generated; Maintain A power-on reset signal generation circuit for making the power-on reset signal inactive after the second output signal is generated and turning off the switch means, and by turning off the switch means, The second signal generation circuit is controlled to open between a node that generates the power supply voltage and a ground potential.
[0010]
According to the present invention, the power-on reset release timing can be determined by the response speed of the second signal generation circuit without using an element having a large area such as a capacitor. Here, in order to stabilize the power-on reset period, it is necessary to reduce the impedance of the element that determines the response speed of the second signal generation circuit. According to the present invention, after the power-on reset is released, the switch means is turned off by feedback from the power-on reset signal generation circuit to the second signal generation circuit, so that steady current consumption can be reduced.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a circuit diagram showing a power-on reset circuit according to the first embodiment of the present invention. The power-on reset signal may be active at a high level or may be active at a low level. In the present embodiment, a case where a power-on reset signal that is active at a low level is generated will be described. To do.
[0012]
In Figure 1, the first signal generating circuit 1, the power supply voltage V _CC at the rising of the power supply voltage V _CC is in response to exceeding the first potential, generating a first output signal at a high level. The second signal generating circuit 2, the power supply voltage V _CC at the rising of the power supply voltage V _CC is in response to exceeding the second potential higher than the first potential, a second output of the low level Output a signal. The first output signal is connected to the inverted set input (S bar) of the SR latch circuit 3 constituting the power-on reset signal generating circuit, and the second output signal is the inverted reset input (R bar) of the SR latch circuit 3. )It is connected to the. The input terminal of the inverter circuit INV2 is connected to the output (Q) of the SR latch circuit 3, and the power-on reset signal POR is output from the output terminal of the inverter circuit INV2. Alternatively, the power-on reset signal POR may be output from the inverted output (Q bar) of the SR latch circuit 3.
[0013]
First signal generation circuit 1 includes a P-channel MOS transistor MP1 as an element for shifting power supply voltage V _CC . The source of the transistor MP1 is connected to the power supply voltage V _CC , the gate is connected to the drain (node N1), and the shifted voltage is output from the drain. A resistor R1 is connected as an impedance element between the drain of the transistor MP1 and the ground potential in order to form a current path. An input terminal of the buffer circuit BUF1 is also connected to the node N1. The output terminal of the buffer circuit BUF1 is connected to the inverting set input terminal (S bar) of the SR latch circuit 3. The buffer circuit BUF1 is composed of two inverter circuits connected in series.
[0014]
Second signal generation circuit 2 includes a P-channel MOS transistor MP2 as an element for shifting power supply voltage V _CC . The source of the transistor MP2 is connected to the power supply voltage V _CC , the gate is connected to the drain, and the shifted voltage is output from the drain. Between the drain of the transistor MP2 and the ground potential, an N-channel MOS transistor MN1 as a switch element and a resistor R2 as an impedance element are connected to form a current path. The input terminal of the inverter circuit INV1 is also connected to the source (node N3) of the transistor MN1. The output terminal of the inverter circuit INV1 is connected to the inverting reset input terminal (R bar) of the SR latch circuit 3. Further, the output (Q) of the SR latch circuit 3 is connected to the gate of the MOS transistor MN1 serving as a switching means, whereby the output of the power-on reset signal generation circuit is fed back to the second signal generation circuit. .
[0015]
Here, the resistance R1 is set to a large value in order to reduce the steady consumption current. On the other hand, the resistance R2 is set to a small value in order to stabilize the power-on reset period. For example, the value of the resistor R2 is 1 kΩ, and the value of the resistor R1 is 100 kΩ, which is two orders of magnitude larger than that. Further, the threshold voltage (absolute value) of the buffer circuit BUF1 is made smaller than the threshold voltage (absolute value) of the inverter circuit INV1. These values are determined based on the rising speed of the power supply voltage V _CC and the steady value.
[0016]
The operation of the above circuit will be described with reference to FIGS.
Immediately after the power is turned on, both the potential V _{N1 of the} node N1 and the potential V N3 of the node _N3 are at a low level. Therefore, the potential V _N2 of the node N2 through the buffer circuit BUF1 is at a low level, and the potential V _N4 of the node N4 through the inverter circuit INV1 is at a high level. As a result, the SR latch circuit 3 is set and the power-on reset signal POR is at a low level (power-on reset state).
[0017]
When the power supply voltage V _CC rises from 0 V after the power is turned on, the potential V _{N1 of the} node _N1 also starts to rise from the time when the power supply voltage V _CC exceeds the threshold voltage Vt of the transistor MP1. The potential V _{N1 of the} node N1 has a value that is a voltage drop from the power supply voltage V _{CC by} the threshold voltage Vt of the transistor MP1 (V _N1 = V _CC −Vt). As shown in FIG. 2, at time t ₁ when the potential V _N1 of the node N1 exceeds the threshold voltage of the buffer circuit BUF1, the output of the buffer circuit BUF1 is inverted and the potential V _{N2 of the} node N2 becomes high level. In this way, the first signal generation circuit generates a first output signal having a high level. At this time, as for the input of the SR latch circuit 3, both the inverting set input terminal (S bar) and the inverting reset input terminal (R bar) are at the high level, and the SR latch circuit 3 is in the latch state. Therefore, the power-on reset signal POR is at a low level, and the power-on reset state is maintained.
[0018]
Next, when the power supply voltage V _CC further rises, at time t ₂ when the potential V _{N3 of the} node N3 reaches the threshold voltage of the inverter circuit INV1, the output of the inverter circuit INV1 is inverted and the potential of the node N4 V _N4 goes low. In this way, the second signal generation circuit generates a second output signal having a low level. At this time, the SR latch circuit 3 is in a reset state. Therefore, the power-on reset signal POR becomes high level, and the power-on reset period ends.
[0019]
At this time, since the output (Q) of the SR latch circuit 3 becomes low level, the transistor MN1 is turned off in the second signal generation circuit 2, and the potential V _{N3 of the} node N3 becomes low level. As a result, the potential V _{N4 of the} node N4 via the inverter circuit INV1 becomes high level, and the SR latch circuit 3 returns to the latch state. Therefore, the power-on reset signal POR remains at the high level, and the power-on reset end state is maintained. By this operation, current does not flow through the resistor R2 having a relatively low resistance value, so that current consumption can be reduced.
[0020]
On the other hand, the first signal generation circuit 1 serves only to cancel (set to high level) the set signal before the SR latch circuit 3 performs the reset operation. Even if changes, there is no problem. Accordingly, since a relatively high resistance value can be used for the resistor R1, even if a steady current flows through the resistor R1, the influence on the current consumption of the entire IC is small.
[0021]
The first and second signal generation circuits have the same configuration as the combination of the P channel MOS transistor MP11 and the resistor R11 shown in FIG. 6, but as shown in FIG. 4, the P channel MOS transistor An N channel MOS transistor MN11 may be used instead of MP11, or an N channel MOS transistor MN12 may be used instead of the resistor R11 as shown in FIG.
[0022]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a power-on reset circuit in which a constant current consumption is small and a power-on reset period is stable without using a large-area element such as a capacitor. Can do.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a power-on reset circuit according to a first embodiment of the present invention.
2 is a waveform diagram showing voltage changes at various parts in the power-on reset circuit of FIG. 1; FIG.
3 is a waveform diagram showing a voltage change at a node N4 in the power-on reset circuit of FIG. 1; FIG.
FIG. 4 is a circuit diagram showing another example of a voltage shift element that can be used in the power-on reset circuit according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram showing another example of an impedance element that can be used in the power-on reset circuit according to the first embodiment of the present invention.
FIG. 6 is a circuit diagram showing an example of a conventional power-on reset circuit.
FIG. 7 is a waveform diagram showing voltage changes at various parts in a conventional power-on reset circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st signal generation circuit 2 2nd signal generation circuit 3 SR latch circuit MP1-MP11 P channel MOS transistor MN1-MN12 N channel MOS transistor R1-R11 Resistor BUF1 Buffer circuit INV1-INV12 Inverter circuit N1-N11 Node POR Power On-reset signal _VCC supply voltage Vt threshold voltage

Claims (11)

A first signal generating circuit for generating a first output signal in response to the supply voltage exceeding the first potential;
The node causing the power supply voltage, is connected between the ground potential, and generating a second output signal in response to said power supply voltage exceeds a second potential higher than the first potential,
A second signal generating circuit including switch means for turning on / off the second output signal;
Wherein the first output signal type and said second output signal, a power-on reset signal generating circuit for outputting a power-on reset signal, activating the power-on reset signal have accompanied the rise of the power supply voltage and then, after the first output signal is generated, the second output signal is maintained between active until generation, non the power-on reset signal after said second output signal is generated A power-on reset signal generating circuit which is active and turns off the switch means;
Equipped with,
A power-on reset circuit characterized in that an open control is performed between a node that generates the power supply voltage in the second signal generation circuit and a ground potential by turning off the switch means . The first signal generation circuit comprises:
A first voltage shift element that inputs the power supply voltage and shifts and outputs the value of the power supply voltage;
A first impedance element to form a first current path between the output and the ground potential of the first voltage shifting element,
A first voltage detection circuit that inputs a voltage applied to the first impedance element and outputs a high-level first output signal when the voltage exceeds a first potential;
The power-on reset circuit according to claim 1, comprising:   The power-on reset circuit according to claim 2, wherein the first voltage shift element includes a MOS transistor having a gate and a drain connected to each other.   The power-on reset circuit according to claim 2, wherein the first impedance element includes one of a resistor and a MOS transistor. It said first voltage detection circuit includes a buffer circuit composed of even several inverter circuits connected in series, the power-on reset circuit of claim 2 wherein. The second signal generation circuit comprises:
A second voltage shift element that inputs the power supply voltage and shifts and outputs the value of the power supply voltage;
A second impedance element for forming a second current path between the output and the ground potential of the second voltage shifting element,
A second voltage detection circuit that inputs a voltage applied to the second impedance element and outputs a second output signal that is at a low level when the voltage exceeds a second potential;
The power-on reset circuit according to claim 1, comprising:   The power-on reset circuit according to claim 6, wherein the second voltage shift element includes a MOS transistor having a gate and a drain connected to each other.   The power-on reset circuit according to claim 6, wherein the second impedance element includes one of a resistor and a MOS transistor.   The power-on reset circuit according to claim 6, wherein the second impedance element has an impedance smaller than that of the first impedance element.   The power-on reset circuit according to claim 6, wherein the second voltage detection circuit includes an odd number of inverter circuits connected in series. The power-on reset signal generating circuit, the power-on reset signal is in the set state when the first and second output signal is not present and active, the first output signal is present, the second non the power-on reset signal is said power-on reset signal is latched on when the output signal is not present and held active, the reset state when said first and second output signals are present turning off said switch means with an active, said switch means includes a SR latch circuit again holding the power-on reset signal is latched on the inactive by turning off, power-on according to claim 1 Reset circuit.

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