JP3692737B2 - Charge pump circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge-up circuit that charges up a voltage supplied from the outside (for example, a power supply line) and outputs a charge-up voltage.
[0002]
[Prior art]
FIG. 11 shows a configuration of a conventional charge pump circuit.
The positive side terminal of the first capacitor 3 is connected to the power supply line 1 via the diode 2, and the positive side terminal of the second capacitor 5 is connected via the diode 4 from the connection point of the positive side terminal of the diode 2 and the capacitor 3. It is connected. The negative terminal of the capacitor 3 is connected to the output terminal of the oscillator 7 via the inverter 8, and the negative terminal of the capacitor 5 is connected to the output terminal of the oscillator 7 via the inverters 9 and 10. The oscillator 7 outputs an oscillation signal (clock signal) having a constant frequency. Then, the boosted voltage is output from the output terminal 6 connected to the connection point between the diode 4 and the positive terminal of the capacitor 5. The inverters 8 to 10 are composed of CMOS circuits.
[0003]
In such a configuration, when the output of the oscillator 7 is at a high level, the output of the inverter 8 is at a low level. Therefore, the + side of the capacitor 3 is charged from the power supply line 1 to the power supply voltage level via the diode 2. .
When the output of the oscillator 7 changes to a low level from this state, the output of the inverter 8 becomes a high level. Therefore, the negative side of the capacitor 3 becomes the power supply voltage, and the positive side of the capacitor 3 starts from the doubled power supply voltage. It is charged up to a voltage obtained by subtracting the voltage drop V _F of the diode 2.
[0004]
Further, when the output of the oscillator 7 is low, the output of the inverter 10 is at a low level, the voltage which the voltage of the positive side of the capacitor 5 is obtained by subtracting the voltage drop V _F of the diode 4 from the voltage of the + side of the capacitor 3 If it is lower, the charge on the + side of the capacitor 3 flows to the + side of the capacitor 5 due to the rectifying action of the diode 4, and the + side of the capacitor 5 drops the voltage 2 × It is charged to a voltage obtained by subtracting the V _F.
[0005]
Next, when the output of the oscillator 7 becomes a high level, the output of the inverter 10 becomes a high level, and the negative side of the capacitor 5 becomes the power supply voltage. It is charged up to a voltage obtained by subtracting the voltage drop 2 × V _F at 2 and 4. This charged up voltage is supplied from the output terminal 6 to a load connected thereto.
[0006]
[Problems to be solved by the invention]
In the conventional charge pump circuit described above, since the oscillator 7 is provided externally, there is a problem that it is difficult to obtain a stable desired charge-up voltage. For example, when the oscillation frequency of the oscillator 7 is high, charging and discharging of the capacitors 3 and 5 cannot catch up, and the charge-up voltage does not become a desired voltage.
[0007]
The present invention has been made in view of the above problems, and an object thereof is to obtain a stable desired charge-up voltage.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, the first and second capacitors (12a, 12b) and the first and second rectifying means (11a, 11b) are provided. The charging of one terminal of the capacitor (12a) and the charging of one terminal of the second capacitor (12b) are alternately performed to charge one terminal voltage of the second capacitor (12b) as a charge-up voltage. In the charge pump circuit, a plurality of signal inverting circuits (13 to 15) including the first and second signal inverting circuits (14, 15) are connected in a ring shape, and are connected to the first signal inverting circuit (14). A ring oscillation circuit (100) that performs an oscillation operation by transmitting a signal in the direction of the second signal inversion circuit (15) is provided, and the second signal inversion circuit (15 ) is connected to the other terminal of the first capacitor (12a). output) is connected, the Of the other terminal of the capacitor (12b) and the output of the first signal inversion circuit (14) is connected, the delay of transmission of the signal, the potential of the other terminal of the first capacitor (12a) is at a low When the potential of the other terminal of the second capacitor (12b) is shifted to the high level before the level reaches the level, the potential of the other terminal of the first capacitor (12a) becomes the low level. In addition, the second capacitor (12b) is prevented from being pulled out of the second capacitor (12b) by the parasitic capacitance of the second rectifier (11b) .
[0009]
In this case, the outputs of the different signal inverting circuits in the plurality of signal inverting circuits (13 to 15) are respectively connected to the other terminal of the first capacitor (12a) and the other terminal of the second capacitor (12b). Therefore, the ring oscillation circuit (100) performs an oscillation operation in accordance with the charge / discharge operation of the first and second capacitors (12a, 12b). For this reason, a stable desired charge-up voltage can be obtained.
[0012]
In the first aspect of the present invention, the output of the second signal inversion circuit (15) is obtained by inverting the output of the first signal inversion circuit (14). When the output of the circuit (15) becomes low level, the parasitic capacitance of the second rectifier (11b) prevents the charge from being drawn from the second capacitor (12b) to the first capacitor (12a). And the efficiency of the charge pump circuit can be increased.
[0013]
The signal inverting circuit (13, 14, 15) constituting the ring oscillation circuit (100) includes the inverter (131, 141, 151) and the buffer (132, 142, 152) as in the second aspect of the invention. ) Can be configured respectively. In this case, as in the third aspect of the present invention, the inverter (131, 141, 151) includes the NPN transistors (131b, 141b, 151b), and the NPN transistors (131b, 141b, 151b) If a resistor (131d, 141d, 151d) is connected between the emitter and the base, the NPN transistor can be extracted from the base when the NPN transistor (131b, 141b, 151b) changes from on to off. The switching speed of (131b, 141b, 151b) is increased to enable high-speed operation.
[0014]
Further, as in the invention described in claim 4 , the buffer (132, 142, 152) is configured to perform an emitter follower output by the NPN transistor (132a, 142a, 152a) and the PNP transistor (132b, 142b, 152b). For example, the delay in the buffer (132, 142, 152) can be minimized, and in this case, high-speed operation is possible.
[0015]
In addition, the code | symbol in the above-mentioned parenthesis shows the correspondence with the specific means shown in embodiment mentioned later, and the code | symbol attached | subjected to the 1st, 2nd capacitor | condenser, the 1st, 2nd rectifier means, etc. FIG. 5 shows a portion related to the invention in an embodiment to be described later, and the number of capacitors and rectifying means is not limited to two, and the number is appropriately set according to the number of stages of the charge pump circuit.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows a configuration of a charge pump circuit according to a first embodiment of the present invention.
In this embodiment, diodes 11a to 11d are connected in series between an input terminal (power supply terminal) 20 and an output terminal (boost terminal) 30, and a first connection point between the first diode 11a and the second diode 11b is the first. The positive terminal of the first capacitor 12a is connected, the positive terminal of the second capacitor 12b is connected to the connection point of the second diode 11b and the third diode 11c, and the third diode 11c and the fourth diode. The positive terminal of the third capacitor 12c is connected to the connection point 12d.
[0017]
The output of the signal inverting circuit 13 is connected to the-side terminal of the first capacitor 12a, and the output of the signal inverting circuit 14 is connected to the-side terminal of the second capacitor 12b. The output of the signal inverting circuit 15 is connected to the negative terminal of 12c. The signal inverting circuits 13, 14, and 15 constitute a ring oscillator (ring oscillator) 100 that is connected in series in a ring shape.
[0018]
The signal inverting circuit 13 includes an inverter 131 and a buffer 132. Similarly, the signal inverting circuit 14 includes an inverter 141 and a buffer 142, and the signal inverting circuit 15 includes an inverter 151 and a buffer 152.
The operation of the above configuration will be described.
The ring oscillator 100 performs an oscillation operation by an odd number of signal inverting circuits 13, 14, 15 connected in a ring shape. Here, the node 101 at the connection point between the signal inverting circuit 13 and the signal inverting circuit 14, the node 102 at the connection point between the signal inverting circuit 14 and the signal inverting circuit 15, and the node 103 at the connection point between the signal inverting circuit 15 and the signal inverting circuit 13. The signal waveform is as shown in FIG. In the signal waveform of FIG. 2, it is assumed that there is no waveform rounding.
[0019]
Now, when the node 101 becomes low level, the capacitor 12a is charged from the power supply terminal 20 via the first diode 11a. Next, when the node 101 becomes high level and the node 102 becomes low level, the charge charged in the capacitor 12a moves to the second capacitor 12b through the diode 11b.
Next, when the node 102 changes from the low level to the high level and the node 103 changes to the low level, the charge charged in the capacitor 12b moves to the third capacitor 12c via the diode 11c.
[0020]
Thus, by the oscillation operation of the ring oscillator 100, the charge moves from the first capacitor 12a to the second capacitor 12b, and further, the charge moves to the third capacitor 12c. Due to the movement of the electric charge, a boosted voltage is generated in the third capacitor 12b.
In this case, the outputs of the signal inverting circuits 13, 14 and 15 are connected to the negative terminals of the first, second and third capacitors 12a, 12b and 12c, respectively. The output changes in accordance with the negative terminal potentials of the first, second, and third capacitors 12a, 12b, and 12c. Accordingly, the ring oscillator 100 performs an oscillating operation in accordance with the charging / discharging operation of the first, second, and third capacitors 12a, 12b, and 12c, so that a stable desired charge-up voltage can be obtained.
(Second Embodiment)
In the first embodiment described above, the node 101 changes from the low level to the high level, the charge moves from the first capacitor 12a to the second capacitor 12b via the second diode 11b, and then the node 102 becomes high. Before reaching the level, the node 101 has transitioned from the high level to the low level.
[0021]
At this time, the potential of the node 104 that is capacitively coupled to the node 101 decreases as the level of the node 101 varies. In addition, since the node 104 and the node 105 are coupled by the parasitic capacitance generated at both ends of the second diode 11b, the potential of the node 105 also decreases due to the level fluctuation of the node 101.
Accordingly, a part of the charge transferred from the capacitor 12a to the capacitor 12b returns to the capacitor 12a, and the amount of charge transmitted to the next stage is reduced. Similarly, since the node 105 and the node 106 are also coupled by the parasitic capacitance generated at both ends of the third diode 11c, the amount of charge to be transmitted is reduced when the charge is transferred from the capacitor 12b to the capacitor 12c. become. When the amount of charge transmitted in this way decreases, particularly when the number of stages is increased, it causes a decrease in the ability as a charge pump circuit.
[0022]
Therefore, in the present embodiment, a configuration that solves such a problem is adopted.
FIG. 3 shows the configuration. Compared to the configuration shown in FIG. 1, the signal transmission direction of the ring oscillator 100 is reversed. In the figure, the ring oscillator 100 is the same as that in FIG. 1, and the signal transmission direction between the power supply terminal 20 and the boosting terminal 30 is opposite to that in FIG.
[0023]
The operation of the configuration shown in FIG. 3 will be described.
Now, when the node 103 becomes low level, the capacitor 12a is charged from the power supply terminal 20 via the first diode 11a. Next, when the node 103 becomes high level, the charge charged in the capacitor 12a moves to the second capacitor 12b via the diode 11b.
[0024]
Here, since the potential of the node 103 is obtained by inverting the potential of the node 102 by the signal inverting circuit 15 and there is a delay in signal transmission, the potential of the node 103 is low level as shown in the waveform diagram of FIG. Before becoming, the potential of the node 102 has shifted to a high level.
Accordingly, the charge transfer from the capacitor 12b to the capacitor 12c can be completed before the charge is extracted from the capacitor 12b by the parasitic capacitance of the second diode 11b. This operation is the same in the next stage. As a result, a charge pump circuit that is more efficient than the first embodiment can be obtained.
[0025]
Next, a specific configuration of the ring oscillator 100 in the first and second embodiments described above will be described.
FIG. 4 shows a specific circuit configuration thereof. The signal inverting circuit 13 includes an impedance element 131a configured by a constant current circuit or a resistor, an NPN transistor 131b, an impedance element 131c such as a resistor, and a buffer 132. The impedance element 131a, the NPN transistor 131b, and the impedance element 131c constitute an inverter 131.
[0026]
Similarly, the signal inverting circuit 14 includes an impedance element 141a, an NPN transistor 141b, an impedance element 141c, and a buffer 142. The signal inverting circuit 15 includes an impedance element 151a, an NPN transistor 151b, an impedance element 151c, and a buffer 152. ing.
With this configuration, the NPN transistors 131b, 141b, and 151b can be alternately turned on and off to cause ring oscillation.
[0027]
Reference numerals 40 and 50 in the figure denote a power supply terminal and a ground terminal of the ring oscillator 100.
FIG. 5 shows a more specific configuration. In the configuration shown in FIG. 5, the constant current circuit 17 is provided, the impedance elements 131a, 141a, 151a are PNP transistors, and the PNP transistor 17a in the constant current circuit 17 and the current mirror circuit are configured to flow a constant current. It has become. The constant current circuit 17 includes a PNP transistor 17a, a PNP transistor 17b, and a constant current source 17c.
[0028]
The impedance elements 131c, 141c, and 151c are composed of resistors, and resistors 131d, 141d, and 151d are connected between the bases and emitters of the NPN transistors 131b, 141b, and 151b, respectively. These resistors 131 c ~151 c, by 131D～151d, it is possible to change the operating point of the transistor 131B～151b. Further, by providing the resistors 131d, 141d, and 151d, when the NPN transistors 131b, 141b, and 151b change from on to off, charges can be extracted from the base, so that the switching speed of the NPN transistors 131b, 141b, and 151b is increased. It can be speeded up, and high-speed operation becomes possible.
[0029]
Further, in the example shown in FIG. 5, the buffer 132 is composed of an NPN transistor 132a and a PNP transistor 132b. Similarly, the buffer 142 is composed of an NPN transistor 142a and a PNP transistor 142b, and the buffer 152 is composed of an NPN transistor 152a and a PNP transistor 152b. In this case, since each buffer is configured to perform emitter follower output with an NPN transistor and a PNP transistor, the delay in the buffer can be minimized. In addition, it is good also as a structure which interposed one diode or two diodes connected in series between each base of the NPN transistor and PNP transistor which comprise each buffer.
[0030]
Further, as shown in FIG. 6, the transistors 131 a, 141 a, 151 a, 131 b, 141 b, and 151 b that constitute the inverter can be reversed between the PNP type and the NPN type, as shown in FIG. 6.
In the conventional charge-up circuit, a MOS element is used to ensure the capability of the charge pump circuit. However, even if a bipolar element having a slow switching speed is used as in the examples shown in FIGS. By adopting a ring oscillator configuration that makes effective use of time, the capability of the charge pump circuit can be sufficiently ensured.
[0031]
Note that the ring oscillator 100 can also be configured using MOS elements. FIG. 7 shows an example in which N-channel MOS transistors 131b ′, 141b ′, and 151b ′ are used. In this case, Zener diodes 131d ′, 141d ′, and 151d ′ are provided to protect the gate of the MOS transistor. As described above, by using the MOS transistors 131b ′, 141b ′, and 151b ′, the switching speed can be increased, so that the oscillation frequency is increased and the capability of the charge pump circuit can be increased.
(Third embodiment)
In the first and second embodiments, the inverters 131, 141, 151 and the buffers 132, 142, 152 are connected in series. However, as shown in FIG. 8, the buffers 132, 142, 152 are connected in a ring. You may make it arrange | position between each output terminal of the oscillator 100, and the-side terminal of each capacitor | condenser. The one shown in FIG. 8 corresponds to the second embodiment, but can be configured similarly in the first embodiment.
[0032]
A specific configuration of what is shown in FIG. 8 is shown in FIG. Ring oscillation is performed by supplying the collector voltages of the NPN transistors 131b, 141b, and 151b to the bases of the transistors of the next stage. 9 shows the structure corresponding to the structure shown in FIG. 5, but the structure shown in FIGS. 6 and 7 can also be used.
[0033]
In the various embodiments described above, the number of stages of the charge pump circuit is not limited to 3, and may be configured with 4 or more stages. The number of signal inverting circuits can be set individually with the number of stages of the charge pump circuit. FIG. 10 shows a configuration when boosted in five stages. The configuration of the ring oscillator 100 is the same as that shown in FIG. 3, and diodes 11e and 11f and capacitors 12d and 12e are added to form a connection as shown in the figure.
[0034]
Further, although the diodes 11a to 11d are used as the rectifying means, a bipolar transistor, a MOS transistor or the like may be used as long as it has a rectifying action.
Further, although the ring oscillator 100 is configured using the buffers 132, 142, and 152, the buffers 132, 142, and 152 can be omitted if the output capacity of the inverters 131, 141, and 151 is sufficient. is there.
[0035]
In the various embodiments described above, the output terminal 30 can be grounded and a negative voltage can be generated at the power supply terminal 20.
In order to stop the oscillation operation of the ring oscillator 100, for example, the base potential of the NPN transistor 131b of the inverter 131 is forcibly set to the ground potential via another NPN transistor, and the NPN transistor 131b is forcibly turned off. That's fine.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a charge pump circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing signal waveforms of the ring oscillator 100 in FIG.
FIG. 3 is a diagram showing a configuration of a charge pump circuit according to a second embodiment of the present invention.
FIG. 4 is a diagram showing a specific configuration of the ring oscillator 100 shown in the first and second embodiments.
FIG. 5 is a diagram showing a more specific configuration of what is shown in FIG. 4;
FIG. 6 is a diagram showing another specific configuration of the ring oscillator 100 shown in the first and second embodiments.
FIG. 7 is a diagram showing still another specific configuration of the ring oscillator 100 shown in the first and second embodiments.
FIG. 8 is a diagram showing a configuration of a charge pump circuit according to a third embodiment of the present invention.
9 is a diagram showing a specific configuration of what is shown in FIG.
FIG. 10 is a configuration diagram of a charge pump circuit showing still another embodiment of the present invention.
FIG. 11 is a diagram showing a configuration of a conventional charge pump circuit.
[Explanation of symbols]
11a to 11d ... diodes, 12a, 12b, 12c ... capacitors,
13 to 15: Signal inversion circuit, 100: Ring oscillator.

Claims (4)

First and second capacitors (12a, 12b);
A first rectifying means (11a) for charging one terminal side of the first capacitor (12a);
Second rectifying means (11b) for charging from one terminal side of the first capacitor (12a) to one terminal side of the second capacitor (12b);
Charging one terminal side of the first capacitor (12a) and charging one terminal side of the second capacitor (12b) are alternately performed to one terminal of the second capacitor (12b). In a charge pump circuit using a voltage as a charge-up voltage,
A plurality of signal inversion circuits (13 to 15) including first and second signal inversion circuits (14, 15) are connected in a ring shape, and the second signal inversion is performed from the first signal inversion circuit (14). A ring oscillation circuit (100) that performs an oscillation operation when a signal is transmitted in the direction of the circuit (15) ;
The output of the second signal inversion circuit (15) is connected to the other terminal of the first capacitor (12a), and the other terminal of the second capacitor (12b) is connected to the first signal inversion circuit ( 14) is connected,
Due to the delay of the signal transmission, the potential of the other terminal of the second capacitor (12b) shifts to the high level before the potential of the other terminal of the first capacitor (12a) becomes the low level. When the potential of the other terminal of the first capacitor (12a) becomes a low level, the second capacitor (12b) causes the parasitic capacitance of the second capacitor (12b) to A charge pump circuit characterized in that it prevents the first capacitor (12a) from drawing out electric charges . The signal inversion circuit (13, 14, 15) constituting the ring oscillation circuit (100) includes an inverter (131, 141, 151) and a buffer (132, 142, 152), respectively. The charge pump circuit according to claim 1, wherein: The inverter (131, 141, 151) includes an NPN transistor (131b, 141b, 151b), and a resistor (131d, 141d) is connected between the emitter and base of the NPN transistor (131b, 141b, 151b). 151d) is connected to the charge pump circuit according to claim 2 . Said buffer (132, 142, 152) is, NPN transistors (132a, 142a, 152a) and PNP transistors (132b, 142b, 152b) according to claim 2 or, characterized in that it is configured to perform emitter follower output by 3. The charge pump circuit according to 3 .

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