JP3695993B2 - Semiconductor device inspection apparatus and inspection method - Google Patents

Description

【００３８】
【数２】

【００３９】
つまり、ある工程のウエハの欠陥特徴量を式１に入力し変数ｘを求め、この変数ｘが式２の右辺へ代入され、式２が演算される。このように、ウエハ上の各チップ毎に演算が行われる（ＳＴ５）。この演算の結果得られた全てのチップの良否の値Ｙ（１／０）を予測値１と称す。また、フェイルマップ１５に示される各チップ毎の良否（１／０）を測定値１と称す。
【００４０】
結合荷重値ｗｉとしきい値θｊを調整し、測定値１と予測値１の差が最小になるように結合荷重値ｗｉとしきい値θｊが決定される。
【００４１】
このようにして、決定された結合荷重値ｗｉとしきい値θｊによるニューラルネットワークモデルが一旦構築される（ＳＴ６）。
【００４２】
次に、このモデルを用いて、他のウエハのチップの良否の判断が正確に行われるか否か確認される。すなわち、構築したモデルの確度が評価される。
【００４３】
まず、他のウエハの欠陥特徴量を式１に入力して変数ｘを求め、この変数ｘが式２の右辺に代入され、式２が演算される。この演算結果を、予測値２と称す。また、フェイルマップに示される各チップ毎の良否（１／０）を測定値２と称す。次に、この予測値２が測定値２に近いかが比較される。
【００４４】
このようにして、最終的に、測定値と予測値の差が最も小さくなるような結合荷重値ｗｉとしきい値θｊが決定され、ニューラルネットワークモデルが構築される（ＳＴ７）。
【００４５】
次に、上記のようにして構築されたモデルを用いて、製品の歩留まりが予測される。例えば他のウエハの欠陥分布を測定し、欠陥特徴量Ｘｉ（ｉ＝１、２、…、ｎ）を抽出する（ＳＴ８）。この欠陥特徴量Ｘｉを、構築したモデルに入力することにより、製品の良否（１／０）が演算される。ここで、製品特性のよいものを例えば１、悪いものを例えば０とした場合、ウエハ上のチップ数に対して１の数が何％あるかを算出する。これによって、製品の歩留まりが予測される（ＳＴ９）。
【００４６】
また、モデルを構築する際に、結合荷重値ｗｉが大きかった工程を記録しておくことより、後に欠陥不良を及ぼす重要工程が抽出される（ＳＴ１０）。
【００４７】
上記第１の実施例によれば、パターンが形成されたウエハの歩留まりを既存の画像比較タイプの欠陥検査装置を使用して確実に予測できる。
【００４８】
また、同じパターンが繰り返し形成される領域の画像は、分割して１つに重ね合わすことができる。そのため、繰り返しパターンの欠陥像の情報を圧縮することができる。従って、歩留まりの予測等の処理の高速化が図れる。
【００４９】
また、結合荷重値ｗｉの大小により、疑似欠陥と実欠陥を区別することができるため（結合荷重値ｗｉの小さい欠陥は疑似欠陥である可能性が高い）、疑似欠陥を排除することが可能である。
【００５０】
また、欠陥データ（欠陥の特徴量）をニューラルネットワークモデルに入力することにより、チップごとの良否が予測できる。そのため、製品の歩留まりを予測することができる。
【００５１】
また、工程ごとの欠陥特徴量Ｘｉ毎に製品の良否に対する感度を比較することにより、歩留まりに対する影響の大きい重要工程が抽出できる。従って、重要工程におけるウエハの欠陥を処理することにより、歩留まりを向上させることができる。
【００５２】
また、ニューラルネットワークモデルは入出力の関係が非線形の方式をとるため、柔軟性が非常に高い。
【００５３】
尚、ニューラルネットワークモデルの中間層のユニットの数を増やすことにより、より複雑な学習が可能となる。
【００５４】
また、欠陥特徴量Ｘｉに入力する数値は、種々の工程ウエハにおける１種類の欠陥特徴量に限定されない。例えば、ある工程のウエハの１チップ当たりの欠陥特徴量のうち、ある欠陥の特徴（例えば欠陥の大きさ）をＸ１、別の欠陥の特徴（例えば欠陥の位置）をＸ２としてもよい。この場合、モデルを構築する際に、結合荷重値ｗｉが大きかった工程を記録しておくことより、後に欠陥不良を及ぼす重要な欠陥の特徴を抽出することができる。
【００５５】
［第２の実施例］
次に、本発明の第２の実施例について説明する。第２の実施例はチップの欠陥データと製品特性の良否との対応調査方法として、重回帰モデルを適用した場合を示す。ここで、第２の実施例において、前記第１の実施例と同様の工程については説明を省略する。
【００５６】
図２に示すように、第１の実施例と同様に、工程途中の特定ウエハによる重ね合わせ画像による欠陥のドットマップ、完成ウエハのフェイルマップが作製される（ＳＴ１〜ＳＴ４）。
【００５７】
次に、ドットマップ及びフェイルマップを用いて、多変量重回帰モデルにより、チップの欠陥像と製品の特性の良否（１／０）との対応が調査される。
【００５８】
式３に示すように、この多変量重回帰モデルは、ｍが欠陥検査するチップの数、Ｘｎはある工程の１チップ当たりの欠陥の特徴を表す量（欠陥特徴量）、αが回帰係数、Ｙがチップの良否（１／０）を示している。ここで、欠陥特徴量は、例えば欠陥の大きさ、位置等が数値化されている。
【００５９】
【数３】

【００６０】
まず、ある工程のウエハ上の１チップ当たりの欠陥特徴量を式３のＸｎに入力し、式３が演算される。このように、ウエハ上の各チップ毎に演算が行われる（ＳＴ５）。この演算の結果得られた全てのチップの良否の値Ｙ（１／０）を予測値１と称す。また、フェイルマップに示される各チップ毎の良否（１／０）を測定値１と称す。
【００６１】
回帰係数αを調整して、測定値１と予測値１の差が最小になるように回帰係数αが決定される。
【００６２】
このようにして、決定された回帰係数αによる多変量重回帰モデルが一旦構築される（ＳＴ６）。
【００６３】
次に、このモデルを用いて、他のウエハのチップの良否の判断が正確に行われるか否か確認される。すなわち、構築したモデルの確度が評価される。
【００６４】
まず、他のウエハの欠陥特徴量を式３に入力し、式３が演算される。この演算結果を予測値２と称す。また、フェイルマップに示される各チップ毎の良否（１／０）を測定値２と称す。次に、この予測値２が測定値２に近いかが比較される。
【００６５】
このようにして、最終的に、測定値と予測値の差が最も小さくなるような回帰係数αが決定され、重回帰モデルが構築される（ＳＴ７）。
【００６６】
次に、上記のようにして構築されたモデルを用いて、製品の歩留まりが予測される。例えば他のウエハの欠陥分布を測定し、欠陥特徴量Ｘｉ（ｉ＝１、２、…、ｎ）を抽出する（ＳＴ８）。この欠陥特徴量Ｘｉを、構築したモデルに入力することにより、製品の良否（１／０）が演算される。ここで、製品特性のよいものを例えば１、悪いものを例えば０とした場合、ウエハ上のチップ数に対して１の数が何％あるかを算出する。これによって、製品の歩留まりが予測される（ＳＴ９）。
【００６７】
また、モデルを構築する際に、回帰係数αが大きかった工程を記録しておくことより、後に欠陥不良を及ぼす重要工程が抽出される（ＳＴ１０）。
【００６８】
上記第２の実施例によれば、パターンが形成されたウエハの歩留まりを既存の画像比較タイプの欠陥検査装置を使用して確実に予測できる。
【００６９】
また、同じパターンが繰り返し形成される領域の画像は、分割して１つに重ね合わすことができる。そのため、繰り返しパターンの欠陥像の情報を圧縮することができる。従って、歩留まりの予測等の処理の高速化が図れる。
【００７０】
また、欠陥データ（チップ内の欠陥分布の測定データ）からチップごとの良否が予測できる。そのため、製品の歩留まりを予測することができる。
【００７１】
また、工程ごとの欠陥特徴量Ｘｉにより製品の良否が判断されるため、歩留まりに対する影響の大きい重要工程が抽出できる。従って、重要工程におけるウエハの欠陥を処理することにより、歩留まりを向上させることができる。
【００７２】
［第３の実施例］
次に、本発明の第３の実施例について説明する。第３の実施例では、前記第１の実施例の欠陥検出方法として光散乱検出タイプを用いた例である。従って、欠陥検出方法以外は第１の実施例と同様の工程であるため、異なる点のみ説明する。
【００７３】
まず、図２に示すように、ＳＴ１からＳＴ３より、チップが形成される工程途中のウエハを用いて欠陥検出が行われる。
【００７４】
ここで、第３の実施例では、光散乱検出タイプの欠陥検出方法により、ウエハ上の繰り返しパターンから生じる回折光がフィルタリングされ、欠陥に起因する散乱光のみを抽出して欠陥が検出される。この際、検出される欠陥には、実欠陥及び疑似欠陥の両方が含まれている。このようにして、欠陥検査装置によるウエハ内の欠陥分布評価が行われる（ＳＴ１）。
【００７５】
以下の処理は、第１の実施例と同様である。尚、欠陥像は散乱像となるが、これについてもドットマップ化は可能である。
【００７６】
上記第３の実施例によれば、前記第１の実施例と同様の効果が得られる。しかも、この実施例は散乱像を用いて歩留まりを予測できる利点を有している。
【００７７】
また、第３の実施例に示す欠陥検出方法を第２の実施例に適用することを可能であり、この場合も第２の実施例と同様の効果を得ることができる。
【００７８】
尚、本発明は、上記実施形態に限定されるものではない。例えば、歩留まり予測モデルとして、例えばファジィモデル等を用いてもよい。
【００７９】
その他、本発明は、その要旨を逸脱しない範囲で、種々変形して実施することが可能である。
【００８０】
【発明の効果】
以上説明したように本発明によれば、実欠陥中の致命欠陥のみを検出し、製品の歩留まりを予測することが可能な半導体装置の検査装置と検査方法を提供できる。
【図面の簡単な説明】
【図１】本発明に係わる半導体装置の検査方法を示すブロック図。
【図２】本発明に係わる半導体装置の検査方法を示す図。
【図３】ドット化された欠陥特徴を示す図。
【図４】重ね合わせのドットマップを示す図。
【図５】フェイルマップを示す図。
【図６】ニューラルネットワークモデルを示す図。
【図７】欠陥特徴量を示す図。
【図８】ユニットを示す図。
【符号の説明】
１１…ウエハ、
１２…チップ、
１３…ドット、
１４…ドットマップ、
１５…フェイルマップ、
１６…ニューロン、
１７…結合線、
１８…ユニット。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for classifying defects on a semiconductor wafer surface on which a pattern is formed. In particular, the defect distribution data obtained by optical inspection may be a fatal defect that affects product characteristics. The present invention relates to a semiconductor device inspection apparatus and inspection method for extracting high defects.
[0002]
[Prior art]
Conventionally, as an optical defect inspection apparatus which is practically used as a method for classifying defects on a semiconductor wafer surface on which a pattern is formed, for example, a type for comparing images (image comparison, such as the 21 series of KLA-Tencor). Type) and a type that detects light scattering from a defect (light scattering detection type), such as the OSI IQ series.
[0003]
In the image comparison type, a pattern and a color are compared with a peripheral chip for a specific chip. As a result, if there is a location where a difference from the peripheral chip is detected, this location is output as a defect.
[0004]
In the light scattering detection type, the diffracted light generated from the repeated pattern on the wafer is filtered, and only the scattered light caused by the defect is extracted to detect the defect. In addition, there is a type in which the probe light for defect detection is polarized by the defect, and the defect is detected using this change.
[0005]
[Problems to be solved by the invention]
However, in the image comparison type defect detection apparatus, color unevenness occurs in the image due to a subtle difference in the thickness of the deposited film. As a result, when image comparison by color is performed, uneven color tends to be easily detected as a defect.
[0006]
Therefore, in order to avoid such a problem, normal sensitivity adjustment is performed, and the influence of color unevenness is suppressed. However, in this case, the sensitivity to real defects, which are real defects, also decreases.
[0007]
In addition, when there is a grain on the surface of the wafer, there is a problem that it is detected as a defect.
[0008]
Thus, defects due to color unevenness, grains, and the like are apparent defects. Therefore, these defects need to be distinguished from actual defects as pseudo defects. However, in the image comparison type, it is difficult to distinguish these defects from the measurement principle.
[0009]
In the light scattering detection type, a pseudo defect caused by color unevenness in the image comparison type is not detected in the measurement method.
[0010]
However, if grains are present on the surface of the deposited film, metal film, or the like, this is detected as a defect. For this reason, as with the image comparison type, there is a problem that pseudo defects occur.
[0011]
As described above, as a problem common to both defect detection methods, it is inevitable that the detected defect includes a pseudo defect.
[0012]
Even if the detected defect is an actual defect, the influence on the product characteristics may differ depending on the location where the actual defect exists. That is, whether or not an actual defect becomes a fatal defect (fatal defect) for a product depends on a location where the actual defect exists. However, with both defect detection methods, it is difficult to detect only fatal defects in actual defects.
[0013]
Therefore, it is difficult to determine the influence of the detected defect data on the product characteristics and accurately predict the product yield.
[0014]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device inspection apparatus capable of detecting only fatal defects in actual defects and predicting product yields. To provide an inspection method.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the present invention uses the following means.
[0017]
According to an aspect of the present invention, there is provided a method for inspecting a semiconductor device, wherein a defect inspection apparatus detects a defect in a wafer in the middle of the process, detects a feature of the defect in an image including the defect, and generates a defect image. A process for measuring the quality of product characteristics in a completed wafer and generating a fail map; and using the defect image and the fail map to investigate the quality of product characteristics of the wafer and predicting a yield a step of constructing a in the construction of the prediction model, look including a step of extracting process on the defective characteristics, in the step of generating the defect image, the region where the same pattern is repeatedly formed, the repeating pattern According to the number, an image including the defect is divided by this number, and the defect information is compressed by superimposing the divided images into one .
[0018]
The feature of the defect image detected by the defect inspection apparatus is displayed as a dot map.
[0020]
Using the prediction model, only fatal defects are selected from the defects of the wafer, and the yield is predicted.
[0021]
The prediction model is constructed using a neural network. The prediction model is constructed using a multiple regression model.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0023]
[First embodiment]
The first embodiment of the present invention is a defect inspection apparatus and inspection method using an image comparison type.
[0024]
FIG. 1 shows an example of an inspection apparatus. The defect inspection apparatus 1 is a known apparatus that optically detects a defect on a wafer. In this defect inspection apparatus 1, the defect feature amount of the wafer being manufactured is extracted, and the defect inspection apparatus 2 is, for example, a well-known test apparatus. The apparatus 2 performs a characteristic evaluation test on the completed wafer, The quality of each chip is extracted. Data of the defect inspection apparatus 1 is supplied to the defect processing unit 3, and the defect features are processed by the processing unit 3. Each processed data is supplied to the model construction unit 4, and a prediction model such as a yield is constructed in the model construction unit 4. Moreover, the defect processing part 3 and the model construction part 4 are comprised by the control apparatus 5 which consists of a known computer, for example.
[0025]
FIG. 2 is a flowchart showing the operation of the apparatus shown in FIG. The details of the defect detection method will be described with reference to this flowchart.
[0026]
First, in ST1 to ST3, using the defect inspection apparatus 1, a defect is detected from a wafer being manufactured.
[0027]
That is, a pattern and a color are compared with a peripheral chip for a specific chip by an image comparison type defect detection method. As a result, if there is a location where a difference from the peripheral chip is detected, this location is output as a defect. Further, the position (coordinates) where the defect exists is extracted. At this time, the detected defects include both real defects and pseudo defects. In this way, the defect distribution evaluation in the wafer is performed by the defect inspection apparatus 1 (ST1).
[0028]
Next, as shown in FIG. 3, an image including defects (real defects and pseudo defects) for each chip 12 in the wafer 11 is represented by dots 13 in order to make the characteristics of the defects of the evaluation result easy to understand. In this way, defect feature extraction is performed (ST2).
[0029]
Next, as shown in FIG. 4A, for a region (region having translational symmetry) in which the pattern of the same dot 13 is repeatedly formed in one chip 12, the number n (≧ 1) of the repeated patterns is set. Accordingly, the image of the dot 13 is equally divided into n pieces. Thereafter, as shown in FIG. 4B, n divided images are superimposed on each other, and a dot map 14 of a defect due to a specific wafer in the middle of the process is produced (ST3). In this way, defect images are superimposed and defect information is compressed.
[0030]
On the other hand, the defect inspection apparatus 2 tests the electrical characteristics of each chip on the completed wafer. From this test result, the quality of each chip is measured, and as shown in FIG. 5, a fail map in which, for example, 1 indicates that the product characteristics are good and 0 indicates that the product characteristics are good, corresponding to the quality of each chip on the wafer. 15 is produced (ST4).
[0031]
Next, using the dot map 14 and the fail map 15, the correspondence between the defect image of the chip and the quality (1/0) of the product characteristics is investigated. A neural network is used as a model (multi-input variable 1-output function) for predicting the quality of a chip from such defects in the chip.
[0032]
As shown in FIG. 6, for example, a hierarchical neural network is employed. In this network, a unit 18 composed of neurons 16 and connection lines 17 is arranged in separate layers of an input layer, an intermediate layer, and an output layer.
[0033]
Xn is a quantity representing the feature of a defect per chip in a certain process (defect feature quantity), and Y is a quality of the chip (1/0). Here, as the defect feature amount, for example, the size and position of the defect are quantified.
[0034]
First, as shown in FIG. 7, for example, the defect feature amount per chip (for example, defect size) in the wafer in step 1 is X1, and the defect feature amount per chip in the wafer in step 2 (for example, defect size). ) Is X2, and the defect feature amount (for example, defect size) per chip in the wafer in step n is Xn. Such X1, X2,..., Xn are respectively input to the input layer shown in FIG.
[0035]
FIG. 8 shows the structure of one unit shown in FIG. Here, W represents a combined load value (signal transmission rate), and θ represents a threshold value (a threshold value indicating whether or not a value input to Y is suitable). Further, the function f (x) is expressed by Expression 1 and Expression 2.
[0036]
First, data Din (defect feature amounts X1, X2,..., Xn) is input to the input layer, and the data Dout is passed through the function f (x) using the provisional coupling load value W and threshold value θ. Is output. Thereafter, the data Dout is supplied to the intermediate layer.
[0037]
[Expression 1]

[0038]
[Expression 2]

[0039]
In other words, the defect feature quantity of a wafer in a certain process is input to Equation 1, a variable x is obtained, this variable x is substituted into the right side of Equation 2, and Equation 2 is calculated. Thus, the calculation is performed for each chip on the wafer (ST5). The quality value Y (1/0) of all the chips obtained as a result of this calculation is referred to as a predicted value 1. Further, the quality (1/0) for each chip shown in the fail map 15 is referred to as a measured value 1.
[0040]
The combined load value wi and the threshold value θj are adjusted, and the combined load value wi and the threshold value θj are determined so that the difference between the measured value 1 and the predicted value 1 is minimized.
[0041]
In this way, a neural network model is determined once based on the determined combined load value wi and threshold value θj (ST6).
[0042]
Next, using this model, it is confirmed whether the quality of chips on other wafers can be accurately judged. That is, the accuracy of the constructed model is evaluated.
[0043]
First, the defect feature quantity of another wafer is input to Equation 1 to obtain a variable x, and this variable x is substituted into the right side of Equation 2 to calculate Equation 2. This calculation result is referred to as a predicted value 2. Further, the quality (1/0) for each chip shown in the fail map is referred to as a measured value 2. Next, whether the predicted value 2 is close to the measured value 2 is compared.
[0044]
In this way, finally, the combined load value wi and the threshold value θj that minimize the difference between the measured value and the predicted value are determined, and a neural network model is constructed (ST7).
[0045]
Next, the yield of the product is predicted using the model constructed as described above. For example, the defect distribution of another wafer is measured, and defect feature amounts Xi (i = 1, 2,..., N) are extracted (ST8). By inputting this defect feature quantity Xi into the constructed model, the quality (1/0) of the product is calculated. Here, when the product having good product characteristics is, for example, 1 and the bad product is, for example, 0, the percentage of the number of 1 with respect to the number of chips on the wafer is calculated. As a result, the product yield is predicted (ST9).
[0046]
Further, when building a model, by recording the process where the combined load value wi is large, an important process that causes a defect failure later is extracted (ST10).
[0047]
According to the first embodiment, the yield of a wafer on which a pattern is formed can be reliably predicted using an existing image comparison type defect inspection apparatus.
[0048]
In addition, images of regions where the same pattern is repeatedly formed can be divided and overlapped into one. Therefore, it is possible to compress the defect pattern information of the repeated pattern. Therefore, it is possible to increase the processing speed such as yield prediction.
[0049]
Moreover, since the pseudo defect and the real defect can be distinguished from each other by the magnitude of the combined load value wi (a defect having a small combined load value wi is likely to be a pseudo defect), it is possible to eliminate the pseudo defect. is there.
[0050]
In addition, the quality of each chip can be predicted by inputting defect data (defect feature amount) into the neural network model. Therefore, the product yield can be predicted.
[0051]
In addition, by comparing the sensitivity to product quality for each defect feature amount Xi for each process, it is possible to extract an important process having a large influence on the yield. Therefore, the yield can be improved by processing the wafer defect in the important process.
[0052]
The neural network model is very flexible because the input / output relationship is nonlinear.
[0053]
Note that more complex learning is possible by increasing the number of intermediate layer units of the neural network model.
[0054]
The numerical value input to the defect feature amount Xi is not limited to one type of defect feature amount in various process wafers. For example, among defect feature amounts per chip of a wafer in a certain process, a feature of a certain defect (for example, the size of the defect) may be X1, and a feature of another defect (for example, the position of the defect) may be X2. In this case, when the model is constructed, it is possible to extract important defect features that cause defect defects later by recording a process in which the combined load value wi is large.
[0055]
[Second Embodiment]
Next, a second embodiment of the present invention will be described. The second embodiment shows a case where a multiple regression model is applied as a method for investigating the correspondence between chip defect data and product characteristics. Here, in the second embodiment, description of the same steps as those in the first embodiment will be omitted.
[0056]
As shown in FIG. 2, similarly to the first embodiment, a defect dot map and a completed wafer fail map are produced by a superimposed image of a specific wafer during the process (ST1 to ST4).
[0057]
Next, using a dot map and a fail map, the correspondence between the defect image of the chip and the quality of the product (1/0) is investigated by a multivariate multiple regression model.
[0058]
As shown in Equation 3, this multivariate multiple regression model is such that m is the number of chips to be inspected for defects, Xn is a quantity representing the characteristics of defects per chip in a certain process (defect feature quantity), α is a regression coefficient, Y indicates the quality of the chip (1/0). Here, as the defect feature amount, for example, the size and position of the defect are quantified.
[0059]
[Equation 3]

[0060]
First, a defect feature amount per chip on a wafer in a certain process is input to Xn of Equation 3, and Equation 3 is calculated. Thus, the calculation is performed for each chip on the wafer (ST5). The quality value Y (1/0) of all the chips obtained as a result of this calculation is referred to as a predicted value 1. Further, the quality (1/0) for each chip shown in the fail map is referred to as a measured value 1.
[0061]
The regression coefficient α is adjusted so that the difference between the measured value 1 and the predicted value 1 is minimized.
[0062]
In this way, a multivariate multiple regression model with the determined regression coefficient α is once constructed (ST6).
[0063]
Next, using this model, it is confirmed whether the quality of chips on other wafers can be accurately judged. That is, the accuracy of the constructed model is evaluated.
[0064]
First, the defect feature quantities of other wafers are inputted into Equation 3, and Equation 3 is calculated. This calculation result is referred to as a predicted value 2. Further, the quality (1/0) for each chip shown in the fail map is referred to as a measured value 2. Next, whether the predicted value 2 is close to the measured value 2 is compared.
[0065]
In this way, the regression coefficient α is finally determined so that the difference between the measured value and the predicted value is minimized, and a multiple regression model is constructed (ST7).
[0066]
Next, the yield of the product is predicted using the model constructed as described above. For example, the defect distribution of another wafer is measured, and defect feature amounts Xi (i = 1, 2,..., N) are extracted (ST8). By inputting this defect feature quantity Xi into the constructed model, the quality (1/0) of the product is calculated. Here, when the product having good product characteristics is, for example, 1 and the bad product is, for example, 0, the percentage of the number of 1 with respect to the number of chips on the wafer is calculated. As a result, the product yield is predicted (ST9).
[0067]
In addition, when the model is constructed, important processes that cause defect defects are extracted later by recording processes in which the regression coefficient α is large (ST10).
[0068]
According to the second embodiment, the yield of a wafer on which a pattern is formed can be reliably predicted using an existing image comparison type defect inspection apparatus.
[0069]
In addition, images of regions where the same pattern is repeatedly formed can be divided and overlapped into one. Therefore, it is possible to compress the defect pattern information of the repeated pattern. Therefore, it is possible to increase the processing speed such as yield prediction.
[0070]
Also, the quality of each chip can be predicted from the defect data (measurement data of defect distribution in the chip). Therefore, the product yield can be predicted.
[0071]
In addition, since the quality of the product is determined based on the defect feature amount Xi for each process, an important process having a large influence on the yield can be extracted. Therefore, the yield can be improved by processing the wafer defect in the important process.
[0072]
[Third embodiment]
Next, a third embodiment of the present invention will be described. In the third embodiment, a light scattering detection type is used as the defect detection method of the first embodiment. Therefore, since the process is the same as that of the first embodiment except for the defect detection method, only the differences will be described.
[0073]
First, as shown in FIG. 2, from ST1 to ST3, defect detection is performed using a wafer in the process of forming a chip.
[0074]
Here, in the third embodiment, the diffracted light generated from the repetitive pattern on the wafer is filtered by the light scattering detection type defect detection method, and only the scattered light caused by the defect is extracted to detect the defect. At this time, the detected defects include both real defects and pseudo defects. In this way, the defect distribution evaluation in the wafer is performed by the defect inspection apparatus (ST1).
[0075]
The following processing is the same as in the first embodiment. The defect image is a scattered image, but this can also be converted to a dot map.
[0076]
According to the third embodiment, the same effect as in the first embodiment can be obtained. In addition, this embodiment has an advantage that the yield can be predicted using the scattered image.
[0077]
Further, the defect detection method shown in the third embodiment can be applied to the second embodiment, and in this case, the same effect as that of the second embodiment can be obtained.
[0078]
The present invention is not limited to the above embodiment. For example, as a yield prediction model, for example, a fuzzy model or the like may be used.
[0079]
In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.
[0080]
【The invention's effect】
As described above, according to the present invention, it is possible to provide an inspection apparatus and an inspection method for a semiconductor device capable of detecting only a fatal defect in an actual defect and predicting a product yield.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a semiconductor device inspection method according to the present invention.
FIG. 2 is a view showing an inspection method of a semiconductor device according to the present invention.
FIG. 3 is a view showing dot defect characteristics.
FIG. 4 is a diagram showing an overlapping dot map.
FIG. 5 is a diagram showing a fail map.
FIG. 6 is a diagram showing a neural network model.
FIG. 7 is a diagram showing defect feature amounts.
FIG. 8 is a diagram showing a unit.
[Explanation of symbols]
11 ... wafer,
12 ... chip,
13 ... dot,
14 ... dot map,
15 ... Fail map,
16 ... neurons,
17 ... bond line,
18 ... Unit.

Claims (5)

A step of detecting defects in the wafer in the middle of the process by the defect inspection apparatus;
Detecting a feature of the defect in the image including the defect and generating a defect image;
Measuring the quality of product characteristics in the completed wafer and generating a fail map;
Using the defect image and the fail map, investigating the quality of the product characteristics of the wafer, building a yield prediction model,
In the construction of the prediction model, a process of extracting a process that causes a characteristic defect; and
Including
In the step of generating the defect image, for an area where the same pattern is repeatedly formed, the image including the defect is divided by this number according to the number of the repeated patterns, and the divided images are overlapped into one. A method for inspecting a semiconductor device, wherein defect information is compressed . 2. The method of inspecting a semiconductor device according to claim 1 , wherein the feature of the defect image detected by the defect inspection apparatus is displayed as a dot map . 2. The method for inspecting a semiconductor device according to claim 1, wherein pseudo defects are excluded from defects on the wafer and the yield is predicted using the prediction model . 4. The semiconductor device inspection method according to claim 3, wherein the prediction model is constructed using a neural network . 4. The semiconductor device inspection method according to claim 3, wherein the prediction model is constructed using a multiple regression model .

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