JP3698413B2 - Digital circuit verification apparatus and verification method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital circuit verification apparatus and verification method for verifying a clock-synchronized digital circuit.
[0002]
[Prior art]
Currently, register translevel (RTL) design using hardware description language (HDL) is performed in the design of digital circuits. Similarly, when verifying design data, a simulation pattern is created and verified using HDL, a dedicated language, or the like. An advantage of creating and verifying a simulation pattern in HDL or a dedicated language is that the signal inside the circuit can be traced. However, with the dramatic increase in the degree of integration of semiconductor integrated circuits, the circuit becomes larger and more complicated, and the following problems occur when performing verification.
[0003]
That is, when the verifier creates the simulation pattern: 1. It takes a very long time for human creation. 2. An input pattern that is not intended by the verifier exists and a verification item is missing. 3. Since the software developer and verifier who create the actual software are different, the software setting order and input pattern order are different, which may result in verification failure and even cause malfunction. There are various problems such as a case where the operation cannot be normally performed depending on the timing of the input pattern.
[0004]
In addition, when a pattern for simulation is created by an automatic pattern generation tool, 5. 5. Even if a pattern is generated randomly, it does not mean that the verification has been completed. All combinations are very time consuming and unrealistic.
[0005]
As described above, even if a verification pattern is created and verified by either a verifier or an automatic pattern generation tool, complete verification is very difficult. However, in practice, it is not necessary to perform all combinations infinitely in circuit verification, and the part to be verified is a very small part of the combinational circuit. Therefore, if the verifier creates a pattern, only necessary function verification can be accurately performed. In addition, by specifying the input pattern that is the setting sequence of the digital circuit in the external specification of the designed circuit, the verifier can also create software similar to the simulation pattern. Can prevent an unintended input pattern from occurring.
[0006]
[Problems to be solved by the invention]
As described above, there is an advantage in that the verifier creates a simulation pattern rather than using the automatic pattern generation tool. However, when the verifier creates a simulation pattern, as described above, depending on the timing of the input pattern, it may not be able to operate normally no matter how much it is verified. This is because the verifier does not consider the internal state of a digital circuit to be verified (hereinafter referred to as a target circuit) and creates a pattern by making the target circuit into a black box.
[0007]
Therefore, an object of the present invention is to provide a digital circuit verification apparatus and a verification method that can solve a problem relating to timing that occurs when a verifier creates a simulation pattern and can reliably verify a target circuit.
[0008]
[Means for Solving the Problems]
The present invention holds an input state of a clock-synchronized digital circuit having a sequential element (flip-flop) and a combinational circuit portion and an output state of the sequential element , and compares the internal state of the digital circuit with each of the current state and the current state. A pattern for verifying and verifying the digital circuit according to the determination result is input to the digital circuit at a predetermined timing.
[0009]
In the digital circuit, when the state of the target circuit is considered, one state can be represented by an input signal to the target circuit and a sequential circuit inside the target circuit. The state of the target circuit is a stable state (no change stable state) in which the state does not change at all after a certain time elapses when a clock signal is input to the target circuit and other input signals do not change. This is a state that has a periodic rule and keeps changing (periodic stable state).
[0010]
For example, when a setting value is output from the target circuit by writing the setting value from the CPU to a register inside the target circuit, such as a port control circuit, the state does not change at all within a few clocks after setting to the register. It becomes a stable state. Also, like the up counter circuit, when the up counter operation permission is set from the CPU to the register in the target circuit, the counter starts counting up from 0, and when the counter reaches the maximum value, the counting up from 0 is started. In order to do so, it becomes a periodically stable state that changes with periodic rules.
[0011]
In the unchanged stable state, the same result can be obtained even if the input signal to the target circuit is generated at any timing, even if the output signal from the target circuit is output delayed by the timing of the input signal. In the periodic stable state, if the input signal to the target circuit is generated in the same cycle, the same result can be obtained even if the output signal from the target circuit is output later in time with the cycle.
[0012]
For the above reason, if the verifier can know the unchanged stable state and the periodic stable state, a verification pattern of timing that changes the input signal after the unchanged stable state and the periodic stable state is not created.
[0013]
The following circuit is required as a digital circuit verification method model (hereinafter referred to as a digital circuit verification model). The state determination circuit holds the input state of the target circuit and the state of the sequential circuit inside the target circuit, a flip-flop circuit that can hold the state at every rising edge of the clock signal, and the current state and the state one clock before Comparing circuit for comparison and a determination circuit for determining whether the input state and the state of the sequential circuit in the target circuit are changed between the current state and the state one clock before, from the determination circuit The output is passed as a determination result signal to an input signal generation circuit that generates a pattern for verification. The input signal generation circuit makes a pattern a task so that it can be generated every access cycle of the device (host circuit) that is actually connected to the target circuit, and the execution of the task is permitted / prohibited by the judgment result signal in the task execution condition Control.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a digital circuit verification model. As shown in FIG. 1, the digital circuit verification model includes a target circuit 110, an input signal generation circuit 100 that generates a simulation pattern to be input to the target circuit, a state determination circuit 120 that determines an internal state of the target circuit 110, and Consists of.
[0015]
The target circuit 110 is only a digital circuit that is in an unchanged stable state, and the target circuit 110 includes a flip-flop circuit 113, 114, 115 that operates with a single clock signal as a sequential circuit, and a combinational circuit 111, 112. Is done.
[0016]
The input signal generation circuit 100 includes a clock generation circuit 103, a task 101 arranged in the execution order, and a task execution permission prohibition control circuit 102 that permits / inhibits execution of the task 101.
[0017]
FIG. 2 shows the task generation timing. For example, a task that generates input signals 1, 2, and 3 is assumed. Tasks can be created for each set of input signals when HDL simulation is performed. When creating a task, first, a basic task that is basic to the access cycle of the external device is created. When using a task, it is possible to perform the same timing input as that of an external device to the target circuit 100 by calling the basic task and giving only a changing input signal value in the basic task. As shown in the example, the input signals 1, 2 and 3 are all “1” when the task is not executed, the input signals 1 and 2 are “0” and the input signal 3 is “1” or “ Assume a basic task that is 0 ".
[0018]
For example, if the determination result signal from the state determination circuit 120 is “1”, the task execution permission prohibition control circuit 102 permits the task execution and executes the next task. If the determination result signal is “0”, the execution of the task is prohibited and the execution of the next task is awaited.
[0019]
The state determination circuit 120 receives an input signal from the input signal generation circuit 100 to the target circuit 110 and an output signal from the flip-flop circuits 113, 114, and 115 inside the digital circuit. The state determination circuit 120 receives a flip-flop circuit 121 for holding the state one clock before, a comparison circuit 122 for comparing the state one clock before and the current state, and an output result from the comparison circuit 122. And a determination circuit 123. The comparison circuit 122 can be configured by, for example, an exclusive logical product circuit (hereinafter referred to as an EX-NOR circuit). When the comparison circuit is configured by the EX-NOR circuit, “1” is output if the state one clock before matches the current state, and “0” is output if they do not match. The determination circuit 123 can be composed of, for example, an AND circuit (hereinafter referred to as an AND circuit). When the determination circuit is configured by an AND circuit, “1” is output if all the output results from the comparison circuit 122 are “1”, and “0” is output if any one is “0”. In the following description, it is assumed that an EX-NOR circuit is used for the comparison circuit and an AND circuit is used for the comparison circuit.
[0020]
FIG. 3 is a timing chart for explaining the operation of the digital circuit verification model configured as described above. At the start of the simulation, the initial setting is always performed so that the input signal to the target circuit 110 and the flip-flop circuits 113, 114, and 115 in the target circuit have fixed values. In order to initialize the flip-flops 113, 114, and 115 in the target circuit, it can be usually initialized by using a reset signal as an input signal to the target circuit 110. By this initial setting, the comparison circuit 122 of the state determination circuit 120 can compare the determined values.
[0021]
If the target circuit 110 is a non-change stable circuit, only the clock signal is changed, and after a certain time has passed, a stable state is obtained in which the state does not change at all. That is, when the state one clock before and the current state are compared, all the signals match, and the comparison results from all the comparison circuits 122 become “1”. The determination result of the determination circuit 123 is also “1”, and the task execution permission prohibition control circuit 102 of the input signal generation circuit 100 permits task execution, whereby task 1 is executed.
[0022]
When the task 1 is executed, the determination result signal of the state determination circuit 120 becomes “0”, and the task execution permission prohibition control circuit 102 waits for the execution of the task 2, that is, prohibits the task execution. If a certain period of time elapses after the task 1 is executed, the stable state remains unchanged, and the determination result signal of the state determination circuit 120 also becomes “1”. The task execution permission prohibition control circuit 102 permits task execution, whereby task 2 is executed.
[0023]
By verifying the execution time of each task and recording the execution time of each task, the verifier can know the time until the unchanged stable state is reached. Since the part that is problematic in terms of time is the period until each task reaches the unchanged stable state, the problem can be solved by creating a simulation pattern that executes the next task within the period until it reaches the unchanged stable state. Can be solved.
[0024]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 4 is a block diagram showing a digital circuit verification model. As shown in FIG. 1, the digital circuit verification model includes a target circuit 410, an input signal generation circuit 100, and a state determination circuit 420. A difference from the digital circuit verification model shown in FIG. 1 is that a time-out for the state determination circuit 420 to finish the state determination within a certain period when the target circuit 410 has a circuit that performs a periodic stable operation. The determination period timeout circuit 424 is provided with a set time.
[0025]
In the first embodiment, when the target circuit 410 includes a circuit that is in a periodically stable state, when the target circuit 410 transitions to the periodically stable state, the flip-flop circuits 413, 414, and 415 in the determination target circuit 410 are included. Any one or more of these is different from the state one clock before. For this reason, the determination result signal is always “0”, and the next task cannot be executed.
[0026]
The determination period timeout circuit 424 includes an up counter, and counts up from “0” after executing the task. When the up counter reaches the maximum value, the determination result signal is set to “1” regardless of the result of the determination circuit 423, and task execution is permitted. The maximum value of the up counter can be represented by 2 ^N, where N is the number of flip-flop circuits in the target circuit 410. The reason is that when the input signal does not change, the target circuit 410 has only the number of states of the flip-flop circuits in the target circuit, and the flip-flop circuits have two states of “0” or “1”. This is because only 2 ^N states exist in the target circuit 410 because there are only states. The same condition always occurs while the up-counter is counting 2 ^N times, resulting in a periodic stable state.
[0027]
FIG. 5 is a timing diagram for explaining the operation of the digital circuit verification model configured as described above. After the initial setting is performed so that the input signal to the target circuit 410 and the flip-flops 413, 414, and 415 in the target circuit have fixed values, the task 1 is executed, and thereby the task execution signal becomes active. In response to the task execution signal, the counter of the determination period timeout circuit 423 in the state determination circuit 420 starts a count operation. In the target circuit 410 that is a periodic stable circuit, the flip-flop circuits 413, 414, and 415 in the target circuit always change, so that one of the comparison circuits 422 in the state determination circuit 420 is always inconsistent. When the determination period timeout circuit 424 counts the maximum value, the timeout signal for one clock becomes active. As a result, the determination result signal becomes “1” regardless of the signal from the comparison circuit 422, and the next task is executed.
[0028]
When the periodic stable state does not occur, the constant change stable state is reached after a certain period of time, so that the comparison result signals from the comparison circuit 422 are all “1”, and the determination result signal of the determination circuit 423 is Since it is “1”, the next task can be executed.
[0029]
By verifying the execution time of each task and recording the execution time of each task, the verifier can know the time until the unchanged stable state is reached. In addition, it is possible to determine which task causes the periodic stable state. The verifier can solve the problem by creating a simulation pattern that performs the next task within the period until the unchanged stable state or the periodic stable state is reached.
[0030]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
FIG. 6 is a block diagram showing a digital circuit verification model. As shown in FIG. 6, the digital circuit verification model includes a target circuit 610, an input signal generation circuit 600, and a state determination circuit 620. Considering the case of having a circuit that performs periodic stable operation similarly to the digital circuit verification model shown in FIG. 4, the difference from the digital circuit verification model shown in FIG. 4 is that the target circuit 610 is periodically stable. When there are a plurality of circuits that perform the operation, the state determination circuit 620 includes a determination period timeout circuit 624 in which a timeout period is set for ending the determination state within a certain period for each circuit that performs the periodically stable operation. It is in.
[0031]
Specifically, in the target circuit 610, flip-flop circuits that are in a periodically stable state are classified into periodic flip-flop circuit groups 613 and 614, and a flip-flop that generates a periodic generation trigger signal indicating the periodic stable state for each classification is generated. Circuits 615 and 616 are also classified. One operation of the periodic flip-flop circuit group does not affect the other periodic flip-flop circuit group.
[0032]
The determination period timeout circuit 624 is preset with a determination period timeout period for each periodic flip-flop circuit group, and counts up from “0” by a period generation trigger signal. When the up counter reaches the set time-out time, the determination result signal is set to “1” regardless of the result of the determination circuit 623, and task execution is permitted.
[0033]
【The invention's effect】
As described above, according to the present invention, the input state of the clock-synchronized digital circuit having the sequential circuit (flip-flop) and the combinational circuit and the output state of the sequential circuit are held, and the digital state is compared with the current state for each. By constructing a digital circuit verification model for determining the internal state of the circuit and inputting a pattern for verifying the digital circuit to the digital circuit at a predetermined timing according to the determination result, the verifier can set the simulation pattern. Since a stable state that becomes a problem that occurs during creation can be recognized, and the timing in the stable state can be removed and a pattern can be input to the target circuit, the target circuit can be reliably verified.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a digital circuit verification model according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing input signals that are basic tasks.
FIG. 3 is a timing chart showing the operation of the digital circuit verification model according to the first embodiment.
FIG. 4 is a configuration diagram showing a digital circuit verification model according to a second embodiment of the present invention.
FIG. 5 is a timing chart showing the operation of the digital circuit verification model according to the second embodiment.
FIG. 6 is a configuration diagram showing a digital circuit verification model according to a third embodiment of the present invention.
[Explanation of symbols]
100, 400, 600 Input signal generation circuit 101, 401, 601 Task 102, 402, 602 Task execution permission prohibition control circuit 103, 403, 603 Clock generation circuit 110, 410, 610 Target circuit 111, 112, 411, 412, 611 , 612 Combinational circuit 113, 114, 115, 413, 414, 415 Flip-flop circuit (internal)
120, 420, 620 State determination circuit 121, 421, 621 Flip-flop circuit (holds state one clock before)
122, 422, 622 Comparison circuit 123, 423, 623 Determination circuit 424, 624 Determination period timeout circuit 613 Period A flip-flop circuit group 614 Period B flip-flop circuit group 615 Period A generation trigger flip-flop circuit 616 Period B generation trigger flip-flop circuit

Claims (3)

In a digital circuit verification apparatus for verifying a clock-synchronized digital circuit having a sequential element and a combinational circuit part , the input state of the digital circuit and the output state of the sequential element are held, and each of them is compared with the current state. A state determination circuit that determines an internal state of the digital circuit; and an input signal generation circuit that inputs a pattern for verifying the digital circuit in accordance with a determination result of the state determination circuit to the digital circuit at a predetermined timing. A digital circuit verification device characterized by that.  When one circuit that performs a periodic operation exists in the digital circuit, the state determination circuit includes a determination period time-out circuit in which a time-out time is set for ending the state determination within a certain period. The digital circuit verification apparatus according to claim 1.  When there are a plurality of circuits that perform a periodic operation in the digital circuit, the state determination circuit has a determination period timeout circuit in which a timeout period is set for each circuit to finish the state determination within a certain period. The digital circuit verification apparatus according to claim 1.

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