JP3698902B2 - Memory access device and access method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory access device and a method for accessing a DRAM or SDRAM having a plurality of bank configurations.
[0002]
[Prior art]
As a conventional memory access device, for example, the one shown in FIG. 3 is known.
[0003]
3 includes a request storage buffer 3-1, a bank busy counter 3-2, a refresh check circuit 3-3, a bank check circuit 3-4, and a selector 3-5.
[0004]
The request storage buffer 3-1 stores a memory request received from the request issuer when bank busy or refresh busy. The bank busy counter 3-2 counts the bank busy time from the bank address of the memory request sent to the memory control unit and generates bank busy.
[0005]
The refresh check circuit 3-3 generates refresh requests at regular intervals. The bank check circuit 3-4 generates a request select from the bank busy, refresh request, and the bank address of the access destination of the request stored in the request storage buffer 3-1. The selector 3-5 selects a memory request by request selection and outputs it to the memory control unit.
[0006]
[Problems to be solved by the invention]
In the conventional memory access device described above, when a read memory request and a write memory request are stored in the request storage buffer 3-1, for example, due to bank busy, the read and write memory requests are ordered. There is a need to guarantee. Therefore, the output order of the request storage buffer 3-1 is a FIFO (FARST IN FARST OUT) operation. In other words, even if the access destination bank of the subsequent request is not busy, the preceding request cannot be overtaken, resulting in a problem that the memory throughput is reduced.
[0007]
In addition, when the SDRAM is used, there is a problem that the bank in the SDRAM is not effectively used because the inter-bank cycle management in the same SDRAM is not performed.
[0008]
The present invention has been made in view of such circumstances, and can provide a memory access device and an access method thereof that can improve memory throughput by increasing the use efficiency of memory elements. To do.
[0009]
[Means for Solving the Problems]
2. The memory access device according to claim 1, wherein the memory access device is a memory device that is a DRAM or an SDRAM incorporating a plurality of banks, and stores received memory requests in ascending order of word numbers. And comparing the address information of each of the received memory requests with the memory request staying in the request storage buffer, and checking whether a memory request accessing the same address exists in the request storage buffer , generating an address comparator circuit for outputting an address comparison results for all memory requests, a bank busy counter for generating bank busy information, a refresh request at predetermined intervals, and the refresh check circuit for outputting a refresh request, before A request selection circuit that generates a request select signal for selecting a memory request to be output to a memory control unit that controls the memory element, and a memory request is selected by the generated request select signal to the memory control unit A selector for outputting, and guaranteeing the order of memory requests for accessing the same address according to a result of checking by the address comparison circuit.
The request storage buffer outputs a memory request to the memory control unit when the received memory request is not bank busy or refresh busy, and stores up to n memory requests (for n words) when the bank request is busy. Can be.
The request storage buffer can store up to n memory requests (n words, from word “0” to word “n−1”) and stores memory requests in ascending order of word numbers. When a word number “m” (0 ≦ m ≦ n−1) is output, a memory request with a word number equal to or less than “m−1” is retained as the word number, and “n−1” Memory requests from “m” to “m + 1” can be shifted to “−1” word numbers, respectively, to store the memory requests.
The address comparison circuit can output the address comparison result of the preceding memory request for each n word request after checking whether the memory request exists in the request storage buffer.
Further, the address comparison circuit can perform comparison of bank addresses, which is a partial comparison.
The bank busy counter sets the bank busy time from the bank address and command of the memory request sent to the memory control unit, counts down by −1 every clock cycle, and is bank busy when the counter value is other than “0”. A bank busy counter for notifying that there is a bank can be provided for each bank.
The request selection circuit also issues a memory request based on the bank busy information from the bank busy counter, the refresh request from the refresh check circuit, the access destination bank address of the memory request in the request storage buffer, and the address comparison result from the address comparison circuit. Can be selected.
Further, the request selection circuit may prioritize the request selection in the order of the refresh request, the word number stored in the request storage buffer in ascending order, and the memory request transmitted from the request issuer. it can.
In addition, the request selection circuit can generate a request select signal when the bank to be accessed is not bank busy and when the access destination addresses of the memory requests having high priority do not match.
The bank busy counter may be provided with a counter for each bank, which counts the cycle time between banks when an access is made to a different bank in the same SDRAM.
The memory access method according to claim 11 is a memory access method of a memory element which is a DRAM or an SDRAM incorporating a plurality of banks, and stores received memory requests in a request storage buffer in ascending order of word numbers. a first step of, comparing the requests stored memory request each address information received with the memory request staying in the buffer memory request to access the same address is present in the request storage buffer A second step of outputting address comparison results for all memory requests, a third step of generating bank busy information, generating refresh requests at regular intervals, and outputting refresh requests And controlling the memory element. And a fifth step of generating a request select signal for selecting a memory request to be output to the memory control unit, and selecting a memory request by the generated request select signal and outputting the request to the memory control unit. And a step of guaranteeing the order of memory requests for accessing the same address according to the result of the check.
In the first step, when the received memory request is not bank busy or refresh busy, the memory request is output to the memory control unit, and when the received memory request is bank busy, a maximum of n memory requests (for n words) are stored. The process to perform can be included.
In the first step, a maximum of n memory requests (n words, from word “0” to word “n−1”) can be stored, and memory requests are stored in ascending order of word numbers. When a word number “m” (0 ≦ m ≦ n−1) is output, a memory request with a word number equal to or less than “m−1” is retained as the word number, and “n−1” Each of the memory requests from “m + 1” to “m + 1” can be shifted to the word number incremented by “−1” to include a step of storing the memory request.
The second step may include a step of checking whether a memory request is stored and then outputting an address comparison result of a preceding memory request for each n-word request. it can.
The second step may include a step of comparing bank addresses, which is a partial comparison.
In the third step, the bank busy time is set from the bank address and command of the memory request to be sent to the memory control unit, the count is decremented by −1 every clock cycle, and when the counter value is other than “0”, the bank A step of notifying that it is busy may be included.
Further, the fifth step can include a step of selecting a memory request based on bank busy information, a refresh request, an access destination bank address of a stored memory request, and an address comparison result.
Further, the fifth step includes a step in which the priority order as the request selection is the order of the refresh request, the stored word number in ascending order, and the memory request transmitted from the request issuer. be able to.
Further, the fifth step includes a step of generating a request select signal when the bank to be accessed is not bank busy and when the access destination addresses of the high priority memory requests do not match. be able to.
Further, the third step can include a step of counting, for each bank, an inter-bank cycle time when an access is made to a different bank in the same SDRAM with respect to the SDRAM.
In the memory access device and the access method thereof according to the present invention, when a memory request is stored in the request storage buffer due to bank busy, the addresses of the memory requests in the request storage buffer are compared, and the access destination address is one. It is checked whether or not the request is made, and the guarantee of the order of the memory requests is not required, and the memory request with the bank busy released is issued. Further, when an SDRAM is used as a memory element, cycle management between banks in the same SDRAM is performed so that banks in the SDRAM are effectively used.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0011]
FIG. 1 is a diagram showing an embodiment of a memory access device of the present invention, and FIG. 2 is a flowchart for explaining an access method of the memory access device of FIG.
[0012]
The memory access device shown in FIG. 1 includes a request storage buffer 1-1, an address comparison circuit 1-2, a bank busy counter 1-3, a refresh check circuit 1-4, a request selection circuit 1-5, and a selector 1-6. ing.
[0013]
The request storage buffer 1-1 is a buffer for saving a request when the bank is busy. The request storage buffer 1-1 can store up to n memory requests (n words, from word “0” to word “n−1”), and stores the memory requests in ascending order of word numbers.
[0014]
For example, in the case where the word number “m” (0 ≦ m ≦ n−1) is output, the memory request with the word number equal to or less than “m−1” is held in the same word number. Each memory request from “n−1” to “m + 1” is shifted to the word “−1” and the memory request is stored. Therefore, when a memory request is stored, the stored request is stored from the lowest number, so that the stored request is not stored in the toothless state.
[0015]
The address comparison circuit 1-2 compares the address information of the memory request staying in the request storage buffer 1-1. That is, it is checked whether or not a memory request for accessing the same address in the preceding memory request exists in the request storage buffer 1-1, and the address comparison result for each of the n word request and the input request Is output.
[0016]
As an example, a method of checking the address comparison result of the word “X” is shown. That is, when the access address of the word “X” is “Y”, it is compared with all the access addresses from the word “X−1” to the word “0”. At this time, if they do not match, the address comparison result is passed. If the addresses match even at one location, it can be seen that the preceding memory request matches the address to be accessed.
[0017]
At this time, the memory request of the word “X” does not satisfy the output condition. Requests received from the request issuer need to be compared with the access addresses of all memory requests staying in the request storage buffer 1-1.
[0018]
Note that the address comparison by the address comparison circuit 1-2 is not limited to comparison of all addresses, but is effective only by partial comparison with respect to, for example, a bank address.
[0019]
The bank busy counter 1-3 sets a predetermined bank busy time for a bank cycle from the bank address and command of a memory request to be sent to a memory control unit that controls a memory element (not shown). Each bank cycle includes a bank busy counter that counts down by −1 for each clock cycle and notifies that the bank is busy when the counter value is other than “0”, and generates bank busy information.
[0020]
In the case of an SDRAM in which a plurality of banks are built in the same memory element, an interbank busy counter is provided. In this case, a predetermined bank busy time corresponding to the inter-bank cycle of the SDRAM is set, -1 is counted down every clock cycle, and when the counter value is other than “0”, it is notified that the bank is busy.
[0021]
The refresh check circuit 1-4 generates a refresh request at regular intervals, and generates a refresh request with the highest priority.
[0022]
The request selection circuit 1-5 generates a request select signal for selecting a memory request to be output to the memory control unit. In this case, the request selection circuit 1-5 receives the bank busy information from the bank busy counter 1-3, the refresh request from the refresh check circuit 1-4, and the memory request stored in the request storage buffer 1-1. The access destination bank address and the address comparison result from the address comparison circuit 1-2 are input.
[0023]
The priority as the request selection at this time is the refresh request, the word number stored in the request storage buffer 1-1 in ascending order, and the memory request transmitted from the request issuer.
[0024]
A condition necessary for generating the request select signal is that the bank to be accessed is not bank busy. In addition, the access destination addresses of the memory requests having a high priority, that is, a small word number do not match. Select the request that satisfies the above conditions and has the highest priority.
[0025]
The selector 1-6 selects a memory request based on the request select signal, and transmits the memory request to the memory control unit.
[0026]
Next, an access method by the memory access device having such a configuration will be described with reference to FIG.
[0027]
First, when the access destination bank of the memory request received from the request issuer is not bank busy and the preceding request is not stored in the request storage buffer 1-1, the received memory request is output to the memory control unit.
[0028]
When the preceding request is stored in the request storage buffer 1-1, whether the stored request and the access destination bank of the received request are busy is determined from the bank busy information of the bank busy counter 1-3. Check (step 2-1).
[0029]
Next, the memory request staying in the request storage buffer 1-1 and the address information of each received memory request are compared. In this case, the address comparison circuit 1-2 checks whether or not a memory request for accessing the same address exists in the request storage buffer 1-1 (step 2-2), and the address comparison result is sent to all memory requests. Output for.
[0030]
Among the requests that pass the above check result, the request with the highest priority is selected (step 2-3), and a request select is generated (step 2-4).
[0031]
In response to the generated request select, the request storage buffer 1-1 replaces the memory request in the buffer (step 2-5). Further, by the generated request select, a value corresponding to the bank cycle is set to the corresponding bank busy counter from the access destination bank address and command of the memory request output via the selector 1-6 (step 2-6). .
[0032]
Thus, in this embodiment, when a memory request is stored in the request storage buffer 1-1 due to bank busy, the address of the memory request in the request storage buffer 1-1 is compared, and the access destination address Therefore, it is not necessary to guarantee the order of requests, and a memory request in which bank busy is released can be issued, so that throughput can be improved.
[0033]
Further, when an SDRAM is used as a memory element, cycle management between banks in the same SDRAM is performed and banks in the SDRAM are effectively used, so that the throughput can be further improved.
[0034]
【The invention's effect】
As described above, according to the memory access device and the access method thereof according to the present invention, when a memory request is stored in the request storage buffer due to bank busy, the addresses of the memory requests in the request storage buffer are compared and accessed. Check whether the destination addresses match, make it unnecessary to guarantee the order of memory requests, issue a memory request with the bank busy canceled, and use SDRAM as a memory element, in the same SDRAM Since the inter-bank cycle management is performed and the banks in the SDRAM are effectively used, the use efficiency of the memory elements can be increased and the memory throughput can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a memory access device of the present invention.
FIG. 2 is a flowchart for explaining an access method by the memory access device of FIG. 1;
FIG. 3 is a diagram illustrating a conventional memory access device.
[Explanation of symbols]
1-1 Request storage buffer 1-2 Address comparison circuit 1-3 Bank busy counter 1-4 Refresh check circuit 1-5 Request selection circuit 1-6 Selector

Claims (20)

A memory access device for a memory device, which is a DRAM or an SDRAM incorporating a plurality of banks,
A request storage buffer that stores received memory requests in ascending order of word number;
Compares the address information of each memory request that stays in the request storage buffer and the received memory request , checks whether a memory request that accesses the same address exists in the request storage buffer, and compares the addresses An address comparison circuit that outputs the results for all memory requests ;
A bank busy counter that generates bank busy information;
A refresh check circuit that generates refresh requests at regular intervals and outputs refresh requests;
A request selection circuit that generates a request select signal for selecting a memory request to be output to a memory control unit that controls the memory element;
A selector that selects a memory request based on the generated request select signal and outputs the selected memory request to the memory control unit,
A memory access device for guaranteeing an order of memory requests for accessing the same address according to a check result of the address comparison circuit.   The request storage buffer outputs the memory request to the memory control unit when the received memory request is not bank busy or refresh busy, and when the bank request is busy, up to n memory requests (for n words). The memory access device according to claim 1, wherein the memory access device is stored. The request storage buffer is capable of storing up to n memory requests (n words, from word “0” to word “n−1”), and stores memory requests in ascending order of word numbers. When outputting the word number “m” (0 ≦ m ≦ n−1), the memory request with the word number equal to or less than “m−1” holds the memory request with the same word number, and “n−1” 2. The memory access device according to claim 1, wherein each of the memory requests from “m + 1” to “m + 1” is shifted to a word number incremented by “−1” to store the memory request.   The address comparison circuit checks whether or not the memory request exists in the request storage buffer, and then outputs an address comparison result of a preceding memory request for each n-word request. Item 4. The memory access device according to Item 1.   5. The memory access device according to claim 1, wherein the address comparison circuit compares a bank address as a partial comparison.   The bank busy counter sets the bank busy time from the bank address and command of the memory request sent to the memory control unit, counts down by −1 every clock cycle, and is bank busy when the counter value is other than “0”. 2. The memory access device according to claim 1, further comprising a bank busy counter for notifying that there is a bank unit.   The request selection circuit is based on bank busy information from the bank busy counter, a refresh request from the refresh check circuit, an access destination bank address of a memory request in the request storage buffer, and an address comparison result from the address comparison circuit. The memory access device according to claim 1, wherein the memory request is selected.   The request selection circuit is configured such that the priority for request selection is a refresh request, a word number stored in the request storage buffer in ascending order, and a memory request transmitted from a request issuer. The memory access device according to claim 1.   The request selection circuit generates the request select signal when an access destination bank is not bank busy and when an access destination address of a memory request having a high priority does not match. The memory access device described.   2. The bank busy counter is provided with a counter for each bank, which counts an inter-bank cycle time when an access to a different bank in the same SDRAM occurs with respect to the SDRAM. Memory access device. A memory access method for a memory device, which is a DRAM or an SDRAM incorporating a plurality of banks,
A first step of storing received memory requests in a request storage buffer in ascending order of word numbers;
Compares the address information of each memory request that stays in the request storage buffer and the received memory request , checks whether a memory request that accesses the same address exists in the request storage buffer, and compares the addresses A second step of outputting results for all memory requests ;
A third step of generating bank busy information;
A fourth step of generating a refresh request at regular intervals and outputting the refresh request;
A fifth step of generating a request select signal for selecting a memory request to be output to a memory control unit that controls the memory element;
A sixth step of selecting a memory request based on the generated request select signal and outputting the selected memory request to the memory control unit,
A memory access method characterized by guaranteeing the order of memory requests for accessing the same address according to the result of the check.   In the first step, when the received memory request is not bank busy or refresh busy, the memory request is output to the memory control unit, and when the received memory request is bank busy, at most n memory requests (n words) The memory access method according to claim 11, further comprising a step of storing up to minutes). In the first step, memory requests can be stored up to n (n words, from word “0” to word “n−1”), and memory requests are stored in ascending order of word numbers. When outputting the word number “m” (0 ≦ m ≦ n−1), the memory request with the word number equal to or less than “m−1” holds the memory request with the same word number, and “n−1” 12. The memory access method according to claim 11, further comprising the step of storing the memory request by shifting the memory request from “m + 1” to “m + 1” to a word number incremented by “−1”.   The second step includes a step of outputting an address comparison result of a preceding memory request for each n word request after checking whether or not the memory request is stored. The memory access method according to claim 11.   15. The memory access method according to claim 11, wherein the second step includes a step of comparing bank addresses, which is a partial comparison.   In the third step, the bank busy time is set from the bank address and command of the memory request to be sent to the memory control unit, and is counted down by −1 every clock cycle. When the counter value is other than “0”, the bank 12. The memory access method according to claim 11, further comprising a step of notifying that it is busy.   The fifth step includes a step of selecting the memory request based on the bank busy information, the refresh request, an access destination bank address of the stored memory request, and the address comparison result. The memory access method according to claim 11.   The fifth step includes a step in which the priority as the request selection is a refresh request, the stored word number in ascending order, and a memory request transmitted from the request issuer. The memory access method according to claim 11.   The fifth step includes a step of generating the request select signal when the bank to be accessed is not bank busy, and when the access destination addresses of the high priority memory requests do not match. The memory access method according to claim 11.   12. The step according to claim 11, wherein the third step includes a step of counting, for each bank, a cycle time between banks when an access is made to different banks in the same SDRAM with respect to the SDRAM. Memory access method.

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