JP3700290B2 - Orthogonal frequency division multiplexing signal transmission method and receiving apparatus used therefor - Google Patents

Description

（１ａ）式で表される行列式の参照信号は偶数シンボルに、（１ｂ）式で表される行列式の参照信号は奇数シンボルに挿入する。ここで、Ｘ、Ｙは既知の参照信号値、ｐは伝送する該当正キャリアの実数部、ｑは伝送する該当正キャリアの虚数部、ｒは伝送する該当負キャリアの実数部、ｕは伝送する該当負キャリアの虚数部である。上記の参照信号を挿入する搬送波は中心搬送波周波数Ｆ０に対して対称な正負の搬送波周波数を組として、ここでは上記のように２シンボル毎に切り換えるようにしているため、２５６シンボルですべての正負１２８組の搬送波で伝送される。つまり、任意の一搬送波は、２５６シンボル周期で参照信号を伝送する。
【００２８】
演算部４は一例としてデータ系列が２５６本の搬送波で送信されるとき、２倍オーバーサンプリングのＩＤＦＴ演算をして信号を発生させる、５１２ポイントＩＤＦＴ演算する。このときの演算部４への入力割り当ては、入力周波数整列型で順番に番号をふると、次のようになる。
【００２９】
ｎ＝０〜１２８ 搬送波を変調する情報信号が与えられる。
【００３０】
ｎ＝１２９〜３８３ 搬送波レベルを０とし、信号を発生させない。
【００３１】
ｎ＝３８４〜５１１ 搬送波を変調する情報信号が与えられる。
【００３２】
演算部４は、１番目から１２７番目の入力端子と３８５番目から５１１番目の入力端子に４ビットのＲ信号及び４ビットのＩ信号とがそれぞれ入力されると共に、０番目、１２８番目及び３８４番目の入力端子に一定電圧が入力され、それ以外の１２９番目から３８３番目の入力端子には０が入力されて、２倍オーバーサンプリングＩＤＦＴ演算を行い、その結果同相信号（Ｉ信号）及び直交信号（Ｑ信号）を得た後、Ｉ信号とＱ信号にそれぞれマルチパス歪みを軽減させるためのガードインターバルを挿入してから、出力バッファ７へ出力する。
【００３３】
ここで、１番目から１２８番目までの計１２８個の入力端子の入力情報は、０番目の入力端子の入力情報を伝送する中心搬送波周波数Ｆ０に対し、上側（高域側）の情報伝送用搬送波（これを本明細書では正のキャリア又は搬送波というものとする）で伝送され、３８４番目から５１１番目までの計１２８個の入力端子の入力情報は、中心搬送波周波数Ｆ０に対し下側（低域側）の情報伝送用搬送波（これを本明細書では負のキャリア又は搬送波というものとする）で伝送され、特に１２８番目と３８４番目の入力端子の入力パイロット信号はＩＤＦＴ演算の結果、ナイキスト周波数の１／２倍の周波数と等価である両端の周波数の搬送波で伝送され、残りの１２９番目から３８３番目の入力端子には０が入力され（グランド電位とされ）、その部分の搬送波が発生しないようにされる（データ伝送には用いない）。
【００３４】
出力バッファ７は、演算部４の出力演算結果が１回のＩＤＦＴ演算において２５６個の入力情報が５１２点の時間軸信号（Ｉ信号及びＱ信号）として、バースト的に発生されるのに対し、出力バッファ７以降の回路としては、出力バッファ７の内容の読み取り速度一定で連続的に動作するため、両者の時間的違いを調整するために設けられている。
【００３５】
図１のクロック分周器３からのクロックに基づいて、出力バッファ７より連続的に読み出されたＩＤＦＴ演算結果であるＩ信号とＱ信号は、Ｄ／Ａ変換器・低域フィルタ（ＬＰＦ）８に供給され、ここでクロック分周器３からのクロックをサンプリングクロックとしてアナログ信号に変換された後、ＬＰＦにより必要な周波数帯域の成分のＩ信号とＱ信号とが通過されて直交変調器９へそれぞれ供給される。
【００３６】
直交変調器９は中間周波数発振器１０よりの１０．７ＭＨｚの中間周波数を第１の変調波とし、かつ、この中間周波数の位相を９０°シフタ１１により９０°シフトした１０．７ＭＨｚ中間周波数を第２の変調波として、それぞれＤ／Ａ変換器・ＬＰＦ８より入力されたディジタルデータのＩ信号とＱ信号で直交振幅変調（ＱＡＭ）して２５７波（正負１２８組の搬送波と中心搬送波一つ）の情報搬送波からなるＯＦＤＭ信号を生成する。直交変調器９より出力されたＯＦＤＭ信号は周波数変換器１２により所定の送信周波数帯のＲＦ信号に周波数変換された後、送信部１３で電力増幅等の送信処理を受けて図示しないアンテナより放射される。
【００３７】
次に、図２に示す周波数分割多重信号受信装置について説明する。この周波数分割多重信号受信装置は後述するように、ガードインターバル期間処理回路３０とＤＦＴ，ＱＡＭ復号回路３１の構成に特徴がある。図２において、空間伝送路を介して入力されたＯＦＤＭ信号は、受信部２１により受信アンテナを介して受信された後高周波増幅され、更に周波数変換器２２により中間周波数に周波数変換され、中間周波増幅器２３により増幅された後、キャリア抽出及び直交復調器２４に供給される。
【００３８】
キャリア抽出及び直交復調器２４のキャリア抽出回路部分は、入力ＯＦＤＭ信号の中心搬送波（キャリア）を位相誤差少なくできるだけ正確に抽出する回路である。ここでは、情報を伝送する各搬送波は、シンボル周波数である３８７Ｈｚ毎に隣接配置されてＯＦＤＭ信号を構成しているため、中心搬送波に隣接する情報伝送用搬送波も中心周波数に対して３８７Ｈｚ離れており、中心搬送波を抽出するためには、３８７Ｈｚしか離れていない隣接する情報伝送用搬送波の影響を受けないように、選択度の高い回路が必要となる。そこで、キャリア抽出回路部にＰＬＬ回路を用いて中心搬送波Ｆ０の抽出を行う。
【００３９】
キャリア抽出及び直交復調器２４により抽出された中心搬送波Ｆ０は、中間周波数発振器２５に供給され、ここで中心搬送波Ｆ０に位相同期した１０．７ＭＨｚの中間周波数を発生させる。中間周波数発振器２５の出力中間周波数は第１の復調波として直交復調器２４に直接に供給される一方、９０°シフタ２６により位相が９０°シフトされてから第２の復調波としてキャリア抽出及び直交復調器２４に供給される。
【００４０】
これにより、キャリア抽出及び直交復調器２４の直交復調器部からは送信装置の直交変調器９に入力されたアナログ信号と同等のアナログ信号（周波数分割多重信号）が復調されて取り出され、同期信号発生回路２７に供給される一方、低域フィルタ（ＬＰＦ）２８によりＯＦＤＭ信号情報として伝送された必要な周波数帯域の信号が通過されてＡ／Ｄ変換器２９に供給されてディジタル信号に変換される。
【００４１】
ここで重要なのはＡ／Ｄ変換器２９の入力信号に対するサンプリングのタイミングで、これは同期信号発生回路２７によりパイロット信号より生成された、ナイキスト周波数の２倍の周波数のサンプル同期信号に基づいて発生される。すなわち、パイロット信号はサンプルクロック周波数に対して所定の整数比に設定されており、周波数比に応じた周波数逓倍を行ってサンプルクロックのタイミングを得る。
【００４２】
同期信号発生回路２７は、復調アナログ信号が入力され、ガードインターバル期間を含む各シンボル期間で連続信号として伝送されるパイロット信号に位相同期するＰＬＬ回路によりサンプルクロックを発生するサンプルクロック発生回路部と、サンプルクロック発生回路部の一部より取り出した信号によりパイロット信号の位相状態を調べ、シンボル期間を検出してシンボル同期信号を発生するシンボル同期信号発生回路部などよりなる。
【００４３】
なお、シンボル同期信号の発生に際しては、例えば本出願人が先に特願平８−２１９２４２号にて提案したように、ガードインターバルがシンボルの後のデータと同じデータが巡回して配置されているため、ガードインターバルの最後のデータと次のシンボルの開始データの所のみで殆どすべてのキャリアで不連続になっていることに着目し、高域フィルタにより入力復調信号（Ｉ、Ｑどちらの信号でもよい）からキャリアの情報成分を除去すると共に、シンボルの開始点の位置情報（シンボルデータ）を有する残留高周波数成分を抽出し、これをピークディテクタとコンパレータによりパルス列に変換してＰＬＬ（位相同期ループ）回路に入力して、ジッタのないシンボルタイミングクロックを発生させ、これをサンプルクロックを分周する分周回路の分周スタート信号とすることで、分周回路からシンボル同期信号を得る構成を使用してもよい。
【００４４】
Ａ／Ｄ変換器２９より取り出されたディジタル信号は、ガードインターバル期間処理回路３０に供給され、ここで同期信号発生回路２７よりのサンプルクロックとシンボル同期信号に基づいて、ＤＦＴウィンドウの所定量のディジタルデータ列がＤＦＴ，ＱＡＭ復号回路３１に出力される。ＤＦＴ，ＱＡＭ復号回路３１は、同期信号発生回路２７よりのサンプルクロックに基づいて、入力ディジタルデータ列を取り込み、それを複素フーリエ演算して受信複素数の復調信号（復号ディジタル情報信号）を得る一方、シンボル番号を復号し、更にこのシンボル番号に対応した正負キャリアの受信参照信号を求め、これらに基づいて伝送路特性の補正式を検出し、この補正式に基づいて上記の受信複素数の復調信号が補正される。また、ＤＦＴ，ＱＡＭ復号回路３１は、後述する前進信号と後退信号を生成する。
【００４５】
ＤＦＴ，ＱＡＭ復号回路３１から出力された復号ディジタル情報信号は、出力回路３２により並直列変換などの出力処理が行われて出力端子３３へ出力される。また、ＤＦＴ，ＱＡＭ復号回路３１により生成された後述する前進信号と後退信号はそれぞれガードインターバル期間処理回路３０に供給される。
【００４６】
図３は上記のＤＦＴ，ＱＡＭ復号回路３１の一例のブロック図を示す。同図に示すように、ＤＦＴ，ＱＡＭ復号回路３１はＤＦＴ演算回路３１１、補正回路３１２、制御回路３１３及び位相演算回路３１４から構成されている。このＤＦＴ，ＱＡＭ復号回路３１にガードインターバル期間処理回路３０から入力されたディジタルデータ列はＩ信号Ｉ’とＱ信号Ｑ’からなり、それぞれはＤＦＴ演算回路３１１に供給され、ここでＤＦＴ演算されることにより、それぞれの変調信号である伝送情報Ｒ’とＩ’に復号された後、補正回路３１２に供給されて復号値が補正され、補正値である信号Ｒ’及びＩ’がそれぞれ出力され、図２の出力回路３２へ出力される。
【００４７】
次に、補正回路３１２の動作について説明する。補正回路３１２では、ＤＦＴ演算により復号された伝送情報中のシンボル番号に基づいて、そのシンボル番号に対応した正負キャリアの受信値、すなわち受信参照信号値を求める。この受信参照信号値は、偶数シンボルでは、ｐ_0s’、ｑ_0s’、ｒ_0s’及びｕ_0s’であり、奇数シンボルでは、ｐ_1s’、ｑ_1s’、ｒ_1s’及びｕ_1s’であったものとする。
【００４８】
ここで、前記特願平８−４３８５４号にて提案しているように、次式で表される係数Ｓ０〜Ｓ７を上記の参照信号値から算出する。
【００４９】
【数２】

ここで、
Ｓ０＝ (p_0s'・X-p_1s'・Y-q_0s'・Y+q_1s'・X)/2(X²-Y²)
Ｓ１＝ (p_0s'・Y-p_1s'・X+q_0s'・X-q_1s'・Y)/2(X²-Y²)
Ｓ２＝ (p_0s'・X-p_1s'・Y+q_0s'・Y-q_1s'・X)/2(X²-Y²)
Ｓ３＝−(p_0s'・Y-p_1s'・X-q_0s'・X+q_1s'・Y)/2(X²-Y²)
Ｓ４＝ (r_0s'・X-r_1s'・Y+u_0s'・Y-u_1s'・X)/2(X²-Y²)
Ｓ５＝−(r_0s'・Y-r_1s'・X-u_0s'・X+u_1s'・Y)/2(X²-Y²)
Ｓ６＝ (r_0s'・X-r_1s'・Y-u_0s'・Y+u_1s'・X)/2(X²-Y²)
Ｓ７＝ (r_0s'・Y-r_1s'・X+u_0s'・X-u_1s'・Y)/2(X²-Y²)
である。
【００５０】
上記の各係数のうち、Ｓ０は、正キャリアの実数部が、正キャリアの実数部へ伝達する率を示しており、正キャリアの虚数部が、正キャリアの虚数部へ伝達する率を示している。Ｓ１は、正キャリアの実数部が、正キャリアの虚数部へ漏洩する率を示しており、正キャリアの虚数部が、正キャリアの実数部へ漏洩する率を示している。Ｓ２は、負キャリアの実数部が、正キャリアの実数部へ漏洩する率を示しており、負キャリアの虚数部が、正キャリアの虚数部へ漏洩する率を示している。
【００５１】
Ｓ３は、負キャリアの実数部が、正キャリアの虚数部へ漏洩する率を示しており、負キャリアの虚数部が、正キャリアの実数部へ漏洩する率を示している。Ｓ４は、正キャリアの実数部が、負キャリアの実数部へ漏洩する率を示しており、正キャリアの虚数部が、負キャリアの虚数部へ漏洩する率を示している。
Ｓ５は、正キャリアの実数部が、負キャリアの虚数部へ漏洩する率を示しており、正キャリアの虚数部が、負キャリアの実数部へ漏洩する率を示している。Ｓ６は、負キャリアの実数部が、負キャリアの実数部へ伝達する率を示しており、負キャリアの虚数部が、負キャリアの虚数部へ伝達する率を示している。Ｓ７は、負キャリアの実数部が、負キャリアの虚数部へ漏洩する率を示しており、負キャリアの虚数部が、負キャリアの実数部へ漏洩する率を示している。ここで、率の−，＋の説明は省略した。
【００５２】
すなわち、上記の係数Ｓ０〜Ｓ７はＩ信号、Ｑ信号の伝送路の特性を示しており、これらの係数Ｓ０〜Ｓ７を上式により受信参照信号値から算出することにより、伝送路の特性を検出できることになる。
【００５３】
また、（２）式の逆行列を求めることにより、受信データを補正し送信データを推定することができる。ここで、（２）式の逆行列は次式で表される。
【００５４】
【数３】

ただし、上式中Ｈ０〜Ｈ７及びｄｅｔ Ａは次式で表される。
【００５５】
H0 = +S0(S6S6+S7S7)-S2(S4S6+S5S7)+S3(S4S7-S5S6)
H1 = +S1(S6S6+S7S7)-S3(S4S6+S5S7)-S2(S4S7-S5S6) H2 = +S4(S2S2+S3S3)-S6(S0S2+S1S3)+S7(S0S3-S1S2) H3 = +S5(S2S2+S3S3)-S7(S0S2+S1S3)-S6(S0S3-S1S2) H4 = +S2(S4S4+S5S5)-S0(S4S6+S5S7)-S1(S4S7-S5S6) H5 = +S3(S4S4+S5S5)-S1(S4S6+S5S7)+S0(S4S7-S5S6) H6 = +S6(S0S0+S1S1)-S4(S0S2+S1S3)-S5(S0S3-S1S2) H7 = +S7(S0S0+S1S1)-S5(S0S2+S1S3)+S4(S0S3-S1S2)ｄｅｔ Ａ＝Ｓ０×Ｈ０＋Ｓ１×Ｈ１＋Ｓ４×Ｈ２＋Ｓ５×Ｈ３
そこで、補正回路３１２は、入力された係数Ｓ０〜Ｓ７から上式に基づいてｄｅｔ ＡとＨ０〜Ｈ７を算出して、更にこれらの算出値から（３）式中の逆行列のうち次式の補正式の値を算出して記憶保持する。
【００５６】
【数４】

このようにして、該当正負搬送波での補正式が用意される。該当正負搬送波はシンボル番号によって決定される。当然、各搬送波毎に補正式があり、この実施の形態のように２５７本のキャリアを使用する場合は、約１２８個の補正式が順次算出保持される。また、係数Ｓ０〜Ｓ７は時々刻々と変化しているので、補正式も時々刻々と更新される。
【００５７】
補正回路３１２はＤＦＴ演算回路３１１よりの受信情報を、受信参照信号値に基づいて計算されて保持されている上記の補正式を用いてそれぞれの正負キャリアの組で次式を演算して補正し、これにより補正された伝送情報Ｒ’及びＩ’を出力する。
【００５８】
【数５】

ただし、（５）式中、ａ〜ｄは受信補正した、該当正キャリアに割り当てられた受信データ（補正後）の複素数を（ａ＋ｊｂ）とし、受信補正した、該当負キャリアに割り当てられた受信データ（補正後）の複素数を（ｃ＋ｊｄ）としたときの値、ａ’〜ｄ’は受信復号した、該当正キャリアに割り当てられた受信データ（補正前）の複素数を（ａ’＋ｊｂ’）とし、受信復号した、該当負キャリアに割り当てられた受信データ（補正前）の複素数を（ｃ’＋ｊｄ’）としたときの値である。
【００５９】
次に、本実施の形態の要部である制御回路３１３と位相演算回路３１４の動作について説明する。電源投入等の初期状態において、同期信号発生回路２７から出力されるシンボル同期信号に基づいてＤＦＴウィンドウが指定され、そのＤＦＴウィンドウの部分のディジタルデータ列がＤＦＴ演算回路３１１に入力され、ＤＦＴ演算された後補正回路３１２に入力されて上記の補正動作が行われる。
【００６０】
このとき、制御回路３１３は、補正回路３１２より入力された復号シンボル番号に基づき、シンボル番号が一巡したかどうかを、すなわち、１フレーム期間経過したかを監視する。すべてのキャリアについて係数Ｓ０〜Ｓ７を求めるためである。シンボル番号が一巡したことを検出すると、制御回路３１３は位相演算回路３１４に対して演算指令を発する。
【００６１】
位相演算回路３１４は、この演算指令に基づき補正回路３１２が保持している各キャリアの係数Ｓ０、Ｓ１、Ｓ６及びＳ７を取り込み、以下の演算を施し、演算結果（積算値）を制御回路３１３にわたす。ここで、係数Ｓ０とＳ１は正のキャリアの特性を顕著に表しており、係数Ｓ６とＳ７は負のキャリアの特性を顕著に表しており、これらの係数のみでの演算で、後述する比較に対する性能を確保できる。係数Ｓ２〜Ｓ５は、係数Ｓ０、Ｓ１、Ｓ６及びＳ７に比べて小さな値であり、演算量を少なくする効果も含め、無視して差し支えない。
【００６２】
次に、位相演算回路３１４の演算動作について説明する。いま第＋１０キャリアの係数Ｓ０、Ｓ１をＳ０₊₁₀、Ｓ１₊₁₀、第−１０キャリアの係数Ｓ６、Ｓ７をＳ６_-10、Ｓ７_-10、第＋２０キャリアの係数Ｓ０、Ｓ１をＳ０₊₂₀、Ｓ１₊₂₀、第−２０キャリアの係数Ｓ６、Ｓ７をＳ６_-20、Ｓ７_-20とすると、これらの伝送路特性係数は図７で示される。
【００６３】
従って、第＋１０キャリアと第＋２０キャリアとの位相差θは、次式で表せる。
【００６４】

そこで、位相演算回路３１４は上記の第＋１０キャリアと第＋２０キャリアとの位相差θをｔａｎ（θ₊₂₀−θ₊₁₀）で近似し、

を演算する。同様に、位相演算回路３１４は第−１０キャリアと第−２０キャリアとの位相差θをｔａｎ（θ）で近似し、

を演算する。以下、同様に、第＋Ｘキャリアと第＋（Ｘ＋１０）キャリアとの位相差θを近似的に
Ｉ_+X＝{S0_+X・S1_+X+10-S0_+X+10・S1_+X}/{S0_+X・S0_+X+10+S1_+X・S1_+X+10}
を演算し、第−Ｘキャリアと第−（Ｘ＋１０）キャリアとの位相差θを近似的に
Ｉ_-X＝{S6_-X・S7_-X-10-S6_-X-10・S7_-X}/{S6_-X・S6_-X-10+S7_-X・S7_-X-10}
を演算する。
【００６５】
ここで、Ｘは正の整数で、１０キャリア毎の位相差を演算するため、１０、２０、３０、４０、５０、．．．の値をとる。また、例としてキャリア数が±１２８本の場合は、Ｘ＝．．．、１００、１１０までである。
【００６６】
なお、この実施の形態では、１０キャリア毎の位相差を求めたが、例えば５キャリア毎でも、２０キャリア毎でも得ようとする最終結果、すなわち判断結果に影響を及ぼさない。また、演算時間に制約がある場合は、片側である正キャリア方向のみの演算でもよく、また、端の方のキャリアを省略しても構わない。
【００６７】
次に、位相演算回路３１４は、正方向、負方向それぞれの位相差を加算し、その絶対値を合計し積算値Ｉとし、これを演算結果として制御回路３１３へ出力する。ここで、

である。制御回路３１３は上記の演算結果（積算値Ｉ）を記憶した後、前回の積算値と今回の積算値を比較し、今回の積算値が前回の積算値以下の時は、ガードインターバル期間処理回路３０に前進信号を出力し、今回の積算値が前回の積算値より大きいときにはガードインターバル期間処理回路３０に後退信号を出力する。この積算値が最小のときに、ＤＦＴウィンドウと有効シンボル期間が一致する。
【００６８】
次に、ガードインターバル期間処理回路３０の構成及び動作について図４及び図５と共に説明する。ガードインターバル期間処理回路３０は、図４に示すように、データ管理回路３０１と調整回路３０２からなる。データ管理回路３０１は、調整回路３０２が出力する開始信号に基づき、図２に示したＡ／Ｄ変換器２９の出力ディジタルデータ列（Ｉ信号Ｉ’、Ｑ信号Ｑ’）から５１２個のディジタルデータをＤＦＴ，ＱＡＭ復号回路３１に伝達する。
【００６９】
調整回路３０２は、動作開始に当り同期信号発生回路２７から入力される図５（Ａ）に示すシンボル同期信号でカウント値をクリアし、以降は同期信号発生回路２７から入力される図５（Ｂ）に示すサンプルクロックをカウントし、５２４カウント毎に図５（Ｃ）に示すように開始信号をデータ管理回路３０１に出力する。
【００７０】
ここでは、５１２ポイントＤＦＴ演算にて復号するため、５１２個のディジタルデータと、ガードインターバル用に１２個のディジタルデータからなる、図５（Ｅ）に模式的に示すＯＦＤＭ信号の１つのシンボルに対して、シンボル同期信号とサンプルクロックは図５（Ａ）、（Ｂ）に示す関係にある。ここで、図５（Ｄ）に模式的に示すＡ／Ｄ変換器２９の出力ディジタルデータ列は、１シンボルを構成する５２４個のディジタルデータのうち、開始信号から５１２個のデータのみＤＦＴウィンドウ内のデータとしてＤＦＴ，ＱＡＭ復号回路３１に伝達され、残りの１２個のデータは伝達されない。
【００７１】
図１２でも説明したように、図５（Ｃ）の開始信号は同図（Ｅ）に示すＯＦＤＭ信号の正確な有効シンボル期間のデータを切り出す位相関係にはないが、開始信号は図５（Ｅ）に斜線を付して示す隣接シンボルの干渉域には存在しないため、データの復号は可能である。ただし、この状態では隣接キャリア間は、位相関係において係数が大きく異なっている。
【００７２】
調整回路３０２は、ＤＦＴ，ＱＡＭ復号回路３１から前進信号が入力されたときは、１サンプルクロック間引く動作をする。これにより、調整回路３０２から出力される開始信号は、図５（Ｆ）に示すように、１サンプルクロック周期分遅延された信号となる。この開始信号を受けて、データ管理回路３０１は、初期状態のディジタルデータ列と比べると、２個目から５１３個目までのディジタルデータ列を伝達し、最初の１個分と最後の残り１１個分を伝達しないようなＤＦＴウィンドウを設定して動作する。
【００７３】
これ以降、次回の前進信号に対しても調整回路３０２は１サンプルクロック間引いて１サンプルクロック周期分遅延された開始信号を出力するため、データ管理回路３０１は、３個目から５１４個目までのディジタルデータ列を伝達し、最初の２個分と最後の残り１０個分を伝達しないように動作する。以下、同様にして、開始信号は徐々にガードインターバルの最後の方に移動していき、データ管理回路３０１は徐々に後方のディジタルデータ列を伝達するように動作する。
【００７４】
前記位相差の積算値は、開始信号がガードインターバルの最後の位置では最小になり、開始信号が有効シンボル期間内に入ると大きくなり、またガードインターバルの先頭に近い位置ほど位相差の積算値が大きくなる。従って、開始信号が有効シンボル期間にくると、今度はＤＦＴ，ＱＡＭ復号回路３１から後退信号が出力され、これにより調整回路３０２は１サンプルクロックを追加する動作をする。
【００７５】
これにより、調整回路３０２から出力される開始信号は、１サンプルクロック周期分位相が進むようにされた信号となる。この開始信号を受けて、データ管理回路３０１は、初期状態のディジタルデータ列と比べると、１個分前方のデータ列を伝達するように動作する。以下、同様にして、開始信号は徐々に隣接シンボルとの干渉域の方に移動していき、データ管理回路３０１は徐々に前方のディジタルデータ列を伝達するように動作する。
【００７６】
調整回路３０２は例えば、図６に示すように、５１２分周回路３０２１と、シフトレジスタ３０２２と、セレクタ３０２３とから構成される。この調整回路３０２は、５１２分周回路３０２１がシンボル同期信号によりクリアされ、サンプルクロックを５１２個カウントする毎に分周パルスを出力する。シフトレジスタ３０２２はこの分周パルスを受けて、サンプルクロックに同期してシフト動作を行い、例えば８ビット出力をセレクタ３０２３に入力する。
【００７７】
セレクタ３０２３は前進信号がアップ端子に入力されたときは、シフトレジスタ３０２２の出力のうち前回よりも１サンプルクロック分位相が遅れた出力パルスを選択し、後退信号がダウン端子に入力されたときは前回よりも１サンプルクロック分位相が進んだパルスを選択し、それを開始信号として出力する。
【００７８】
ガードインターバル期間処理回路３０は、前進信号を受け前記の動作を行い、ＤＦＴ，ＱＡＭ復号回路３１内の制御回路３１３は、前回と同様に補正回路３１２により伝達されるシンボル番号をもとにシンボルが一巡したかどうかを監視し、シンボルが一巡したと検出したときに、位相演算回路３１４に対し演算命令を発する。位相演算回路３１４は、前回と同様に、演算命令に基づき、補正回路３１２の保持する各キャリアの係数Ｓ０、Ｓ１、Ｓ６及びＳ７を取り込み、演算結果（積算値）を制御回路３１３にわたす。
【００７９】
制御回路３１３は、前述したように前回の積算結果と今回の積算結果の大きさを比較し、今回の方が小さかった場合、更に前進信号を発し、前記の動作を繰り返す。積算結果の大きさが、今回の方が大きかった場合（位相の極小値は前回であったことを意味する）、後退信号を発生し、最適位置の決定を完了する。
【００８０】
なお、ガードインターバル期間処理回路３０とＤＦＴ，ＱＡＭ復号回路３１の他の実施の形態として、ガードインターバル期間処理回路３０は、数シンボル分の記憶回路で構成し、同期信号発生回路２７の出力シンボル同期信号とサンプルクロックに基づき、ディジタルデータ列をリング状に構成してもよく、また、ＤＦＴ，ＱＡＭ復号回路３１は中央処理装置（ＣＰＵ）プロセッサで構成してもよい。
【００８１】
図８はＤＦＴ，ＱＡＭ復号回路３１を構成するＣＰＵプロセッサの動作説明用フローチャートを示す。同図において、電源が投入されると（ステップ４１）、補正回路３１２からのシンボル番号が一巡したかどうか監視し（ステップ４２）、シンボルが一巡したときは、補正回路３１２の保持する各キャリアの係数Ｓ０、Ｓ１、Ｓ６及びＳ７を取り込み、前記した位相差積算演算を行い（ステップ４３）、その演算が１回目であるときは再びステップ４２に戻ってシンボル番号が一巡したかどうか監視し、２回目以降であるときは前回の積算結果と今回の積算結果の大きさを比較する（ステップ４４、４５）。
【００８２】
ステップ４５において、今回の積算結果が前回のそれより以下の場合、前進信号を発し、前記したようにデータ管理回路３０１が、１個分前方のデータ列を伝達するようにデータ取り込み位置のアドレスを１つ進ませ（ステップ４６）、再びステップ４２に戻りシンボル番号が一巡したかどうか監視する。
【００８３】
ステップ４５において、今回の積算結果が前回のそれよりも大きかった場合（位相の極小値は前回であったことを意味する）、後退信号を発生し、データ管理回路３０１が１個分後方のデータ列を伝達するように、データ取り込み位置のアドレスを１つ戻し（ステップ４７）、最適位置の決定を完了する（ステップ４８）。
【００８４】
なお、シンボルの構成例として、ガードインターバルの他に、プリガードインターバルの挿入が考えられる。すなわち、５１２ポイントＩＦＦＴ演算結果が、図９（Ａ）に示す如く、５１２個のディジタルデータＢのうち、先頭の２個のディジタルデータをＡ、最後の１０個のディジタルデータをＣとしたとき、同図（Ｂ）に示す如く、５１２個のディジタルデータＢを有効シンボル期間に配置し、先頭のガードインターバルには１０個のディジタルデータＣを配置し、最後のプリガードインターバルには２個のディジタルデータＡを配置して１シンボルを構成する。
【００８５】
これは、希望波よりも先行して到来するゴースト波に対する干渉対策である。このような構成のＯＦＤＭ信号に対しても本発明を適用することができる。
【００８６】
また、本実施の形態においては、参照信号の挿入方法を正負の搬送波の組で送受した例を示したが、前記したように、係数Ｓ０、Ｓ１とＳ６、Ｓ７を使用し、係数Ｓ２〜Ｓ５を使用しなくても十分な精度は確保できる。すなわち、他の例として、正負の搬送波の組で参照信号を送受しないＯＦＤＭ信号送受信システムでも本発明は十分に適用可能である。
【００８７】
【発明の効果】
以上説明したように、本発明によれば、近傍の搬送波間での位相差の近似値を算出し、更に設定した数の搬送波のそれぞれについて上記の位相差の近似値を算出してそれらを積算し、その積算値を前回入力時と今回入力時とで比較して、その比較結果に応じて積算値が極小となるように時間窓の位相を調整制御することにより、有効シンボル期間の始まりを正確に検出できるようにしたため、近傍搬送波間での係数加算平均によりノイズを除去する場合に、発生する平均化した係数のずれを極力少なくでき、よって装置性能を向上させることができる。
【００８８】
また、本発明によれば、シンボル同期信号の生成に関する性能は従来と同じでよく、簡単な回路あるいはソフトウェアでシンボル同期信号の位置ずれを極力少なくできる。
【図面の簡単な説明】
【図１】本発明になる直交周波数分割多重信号伝送方法の送信系の一実施の形態のブロック図である。
【図２】本発明になる直交周波数分割多重信号伝送方法の受信系及び受信装置の一実施の形態のブロック図である。
【図３】図２中のＤＦＴ，ＱＡＭ復号回路の一例のブロック図である。
【図４】図２中のガードインターバル期間処理回路の一例のブロック図である。
【図５】図４の動作説明用タイミングチャートである。
【図６】図４のガードインターバル期間処理回路中の調整回路の一例のブロック図である。
【図７】図３の位相演算回路の動作を説明する図である。
【図８】ＤＦＴ，ＱＡＭ復号回路をＣＰＵプロセッサで構成した場合の動作説明用フローチャートである。
【図９】本発明を適用し得る他のシンボル構成例を示す図である。
【図１０】ＯＦＤＭ信号のベースバンド時間軸波形図である。
【図１１】ＯＦＤＭ信号のシンボル構成の一例を示す図である。
【図１２】希望波と遅延したゴースト波を受信した場合のシンボル同期信号位置を説明する図である。
【符号の説明】
２ 入力回路
３ クロック分周器
４ 演算部
５ シンボル番号計数回路
６ 参照信号挿入回路
７ 出力バッファ
８ Ｄ／Ａ変換器・低域フィルタ（ＬＰＦ）
９ 直交変調器
１０、２５ 中間周波数発振器
１１、２６ ９０°シフタ
１２、２２ 周波数変換器
２１ 受信部（受信手段）
２４ キャリア抽出及び直交復調器（復調手段）
２７ 同期信号発生回路（同期信号発生手段）
２９ Ａ／Ｄ変換器
３０ ガードインターバル期間処理回路（ガードインターバル期間処理手段）
３１ ＤＦＴ，ＱＡＭ復号回路
３２ 出力回路
３０１ データ管理回路
３０２ 調整回路（調整制御手段）
３１１ ＤＦＴ演算回路（復号手段）
３１２ 補正回路（補正手段）
３１３ 制御回路（調整制御手段）
３１４ 位相演算回路（位相演算手段）
３０２１ ５１２分周回路
３０２２ シフトレジスタ
３０２３ セレクタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an orthogonal frequency division multiplex signal transmission method and a receiving apparatus used therefor, and in particular, converts multi-value modulated digital information into an orthogonal frequency division multiplex (OFDM) signal in a limited frequency band. The present invention relates to an orthogonal frequency division multiplex signal transmission method for transmitting and receiving and a receiving apparatus used therefor.
[0002]
[Prior art]
Multi-level quadrature amplitude modulation (QAM) and multi-level phase modulation (PSK: Phase Shift Keying) are methods for transmitting digital information such as encoded digital video signals in a limited frequency band. There is known an OFDM system in which digital information is transmitted by an OFDM signal obtained by frequency-division-multiplexing a large number of multi-carrier waves each of which is modulated in various ways. This OFDM system is a system in which a large number of carriers are arranged orthogonally, and independent digital information is transmitted by each carrier. Features such as being strong against multipath, being less susceptible to interference, and having relatively good frequency utilization efficiency. There is research and development not only in the communications field but also in the digital broadcasting field. Note that “the carrier waves are orthogonal” means that the spectrum of the adjacent carrier wave becomes zero at the frequency position of the carrier wave.
[0003]
Since the OFDM signal transmitted by the OFDM system is modulated according to information to be transmitted by a large number of carriers and frequency division multiplexed, its baseband time axis waveform is as shown in FIG. The information transmission is performed in units of symbol periods. In each symbol period, as indicated by ta in FIG. 11, a guard interval gi is set immediately before an effective symbol period ts in which data obtained by inverse fast Fourier transform (IFFT) calculation of information to be transmitted is transmitted. It is an added period. The guard interval gi is a period for reducing the multipath, and the signal waveform in the period is a signal waveform of the effective symbol period ts that is repeated.
[0004]
The frequency interval of each carrier of the OFDM signal is equal to the reciprocal of the effective symbol period ts. In order to obtain a value sampled at a period obtained by dividing the effective symbol period ts by N, N base point IDFT calculation is performed on N frequency complex data once for each symbol period ta on the frequency axis. A signal waveform is obtained.
[0005]
On the receiving side, the OFDM signal is sampled at a period of ts / N, subjected to N-point discrete Fourier transform (DFT) once every symbol period ta, and the phase and amplitude of each carrier frequency component are calculated, Get received data. At this time, a time window (generally referred to as a DFT window) is set for each symbol period, and a DFT operation is performed on a data string of the DFT window. The symbol synchronization signal designates the DFT window.
[0006]
As a method of generating the symbol synchronization signal, for example, there is a method of using a symbol of a predetermined period as a null symbol (no signal period) and using it. The symbol synchronization signal does not need to accurately detect a symbol break and is allowed to be detected within a certain range (± several samples). To explain this, when a receiving apparatus receives a delayed ghost wave as schematically shown in FIG. 12B together with a desired wave schematically shown in FIG. The symbol synchronization signal sa shown in FIG. 6C is generated at the start time point a of the effective symbol period of the large desired wave, thereby specifying the DFT window and taking out the data string from the effective symbol start time point a to perform the DFT operation. In this case, as can be seen from FIGS. 12A and 12B, since the data string up to the start time point b of the ghost wave symbol period before the start time point a is not subjected to the interference of the adjacent symbol, the symbol synchronization signal May be generated at time point b as indicated by sb in FIG. 12D, and may be generated anywhere from time point b to time point a.
[0007]
That is, this margin is generated by setting the guard interval period longer than the ghost wave delay time. Therefore, conventionally, the generation of the symbol synchronization signal has been facilitated (simple) by setting the guard interval period to be longer than the assumed ghost wave delay time.
[0008]
[Problems to be solved by the invention]
By the way, in the OFDM signal transmission system previously proposed by the present inventor in Japanese Patent Application No. 8-43854, a reference signal is inserted into the OFDM signal as known reference data and transmitted, and this reference signal is transmitted to the receiving side. Based on this, the transmission path characteristics indicating the error between the in-phase signal (I signal) and the quadrature signal (Q signal) are detected, and the information signal is restored almost accurately by correcting the transmission path characteristics by obtaining a correction formula. can do.
[0009]
However, the received reference signal includes a noise component, and it is difficult to accurately grasp the transmission path characteristics. Therefore, in the above-mentioned proposal by the present inventor, the average of the coefficients of the transmission path characteristics is calculated with a nearby carrier wave (filter processing), and the transmission path characteristics without the influence of noise are detected. Even if a simple addition average of coefficients of neighboring carriers is taken, the noise removal effect is great.
[0010]
However, since the relationship between these coefficients is not a linear relationship but a several order curve, a large number of addition averages deviate from actual values. In a modulation scheme having a small threshold, for example, 256 QAM or more, this deviation cannot be ignored. One cause of the difference in coefficients between the carrier waves is a shift in symbol synchronization position.
[0011]
For example, in an OFDM signal transmission apparatus that performs an n-point FFT operation, if there is a misalignment of m samples in the symbol synchronization signal, the relationship between the coefficients of adjacent symbols is (2π / n) × m [rad. ] Appears as a phase difference. When performing the averaging, a deviation due to this factor occurs. As an example, in an OFDM signal transmission apparatus that performs 512-point FFT operation, the relationship between coefficients of adjacent symbols is 2π / 512 = π / 256 [rad. ] Appears as a phase difference.
[0012]
To further explain this relationship, for example, the nth carrier has a waveform of n cycles in the effective symbol period. That is, (2π × n) [rad. ] Phase change. When this is seen in one sample, (2π × n) / 512 [rad. ] Of the phase difference. Therefore, (2π × n) / 512 [rad. ] Will be corrected. On the other hand, in the n + 1th carrier, (2π × (n + 1)) [rad. ] Phase change. When this is viewed in one sample, (2π × (n + 1)) / 512 [rad. ] Of the phase difference. Accordingly, (2π × (n + 1)) / 512 [rad. ] Will be corrected.
[0013]
Therefore, the difference between the correction values of the nth carrier and the (n + 1) th carrier is
{(2π × (n + 1)) / 512} − {(2π × n) / 512} = 2π / 512 = 2π / 256 [rad. ]
It becomes. In the case of X sample deviation, the above-mentioned phase deviation is multiplied by X, so that the difference between the correction values of the nth carrier and the (n + 1) th carrier is also X × 2π / 256 [rad. ], The greater the sample deviation, the greater the difference in the correction values between adjacent ones.
[0014]
As described above, if the DFT window does not extend over the adjacent symbols, the symbol synchronization signal allows a deviation of several samples, and there is no difference in apparatus performance. However, when noise is removed by averaging the coefficients of adjacent carriers, it is important to improve the device performance to reduce the symbol synchronization shift as much as possible and to reduce the difference in coefficients between adjacent carriers. .
[0015]
The present invention has been made in view of the above points, and provides an orthogonal frequency division multiplex signal transmission method capable of reducing symbol synchronization shift as much as possible and reducing errors caused by coefficient addition averaging between adjacent carriers, and a receiving apparatus used therefor. For the purpose.
[0016]
[Means for Solving the Problems]
  In order to achieve the above object, the orthogonal frequency division multiplexing signal transmission method of the present invention, on the transmission side,Inverse discrete Fourier transform in synchronization with a sample clock of a known reference signal and pilot signal reference data corresponding to a value of a symbol number that sequentially changes for each symbol period and makes a round in one frame period. Then, by quadrature modulation,Each of a plurality of carriers having different frequencies is modulated separately by an information signal to be transmitted assigned to each carrier,Varies depending on the symbol number valueInsert a known reference signal into a given carrierIn addition, a pilot signal set to a predetermined integer ratio with respect to the frequency of the sample clock is inserted into a predetermined carrier wave.Then, an orthogonal frequency division multiplex signal frequency-division multiplexed is generated and transmitted in a symbol unit consisting of a guard interval and an effective symbol period,
  On the receiving side, receivedOrthogonalFrequency division multiplexed signalAfter quadrature demodulation, based on the pilot signal in the quadrature demodulated signal, the sample clock and symbol unitGenerate a symbol sync signalSample clock andIncluded in the time window set based on the symbol sync signalThe quadrature demodulated signal based on the sample clockAn orthogonal frequency division multiplex signal transmission method for decoding an information signal and a reference signal to be transmitted by discrete Fourier transform,
  The receiving side calculates the approximate value of the phase difference between a pair of nearby carriers among a plurality of carriers using a coefficient representing the transmission path characteristics of the carriers, and performs them for each of the set number of carriers. The integrated value of the approximate value is calculated, the previous integrated value is compared with the current integrated value, and the phase of the time window is adjusted so that the obtained integrated value is minimized according to the comparison result.In units of one cycle of the sample clockAdjust discretely,Using the value of the reference signal inserted in the predetermined carrier wave subjected to discrete Fourier transformA time window whose phase characteristics are discretely adjusted using the correction characteristics by detecting the transmission path characteristics of the carrier wave, calculating and storing a correction characteristic that is opposite to the transmission path characteristics from the detected transmission path characteristics.Included in the quadrature demodulated signal based on the sample clockDiscrete Fourier transformAn information signal is obtained by correcting an error component that cannot be corrected in the demodulated signal obtained.
[0017]
  In addition, the method of the present invention isBy performing inverse discrete Fourier transform on the information signal to be transmitted in synchronization with the sample clock,Multiple carriers with different frequenciesIn addition to transmitting digital information signals to be transmitted inA set of a positive carrier on the high-frequency side and a negative carrier on the low-frequency side that is symmetrical with respect to the center carrier among a plurality of carriersA known reference signal is inserted into the pilot signal, and a pilot signal set to a predetermined integer ratio with respect to the frequency of the sample clock is inserted into a predetermined carrier wave. TheSpecific transportIn the wavesIt is specified by the symbol number to be transmitted and is cyclically changed at regular intervals to generate an orthogonal frequency division multiplexed signal that is frequency division multiplexed and transmitted in symbol units consisting of a guard interval and an effective symbol period.,
  On the receiving side, the received frequency division multiplexed signalIs orthogonally demodulated, and based on the pilot signal in the quadrature demodulated signal, the sample clock andGenerate a symbol sync signalSample clock andIncluded in the time window set based on the symbol sync signalThe quadrature demodulated signal based on the sample clockWhen the information signal and symbol number to be transmitted are decoded by discrete Fourier transform, the reference signal is decoded based on the decoded symbol number, and the real part of the positive carrier wave is transmitted from this reference signal, the negative carrier wave The transmission line characteristics are detected based on the signal component leaking to the imaginary part or real part of the signal, or the signal component leaking to the imaginary part or real part of the negative carrier when transmitting the imaginary part of the positive carrier. An orthogonal frequency division multiplexing signal transmission method for correcting an information signal decoded using the detected transmission path characteristics,
  The receiving side calculates the approximate value of the phase difference between a pair of nearby carriers among a plurality of carriers using the signal component that leaks the transmission path characteristics, and performs them for each of the set number of carriers. The integrated value of the approximate value is calculated for each predetermined period, the previous integrated value is compared with the current integrated value, and the integrated value obtained is determined according to the comparison result.MinimalThe phase of the time window so thatIn units of one cycle of the sample clockA time window that is discretely adjusted, calculates and stores a correction characteristic that is the inverse of the detected transmission path characteristic, and is phase-adjusted discretely using the correction characteristicBased on the sample clockDiscrete Fourier transformThe information signal is obtained by correcting the uncorrectable error component of the demodulated signal obtained.It is characterized by that.
[0018]
  The receiving device of the present invention isBy performing inverse discrete Fourier transform on the information signal to be transmitted in synchronization with the sample clock,Transmits a digital information signal to be transmitted by a plurality of carriers having different frequencies, and is known to a pair of a positive carrier on the high band side and a negative carrier wave on the low band side that is symmetrical with respect to the center carrier wave among the plurality of carriers. Is inserted,And a pilot signal set to a predetermined integer ratio with respect to the frequency of the sample clock is inserted into a predetermined carrier wave,A set of positive and negative carriers that transmit a reference signalInsertion positionA specific transportIn the wavesAn orthogonal frequency division multiplex signal that is specified by the symbol number to be transmitted and that is cyclically changed sequentially every fixed period, and that is transmitted in symbol units consisting of a guard interval and an effective symbol period, is received. Receiving signal, and orthogonally demodulating the received orthogonal frequency division multiplexed signal from the receiving means, and an information signal and a symbol number represented by a complex numberWhenReference signalAnd pilot signal andFrom the demodulation means to obtain theBased on the pilot signal, the sample clock andSynchronization signal generating means for generating a symbol synchronization signal having a symbol unit period, and a symbol synchronization signalAnd sample clockA guard interval period processing means for discretely setting a time window based on the information signal and passing the information signal, the symbol number and the reference signal from the demodulation means within the time window,
  The signal from the guard interval period processing meansBased on sample clockThe digital information signal is decoded by discrete Fourier transform, and the decoding means for decoding the symbol number and the reference signal; the reference signal is decoded from the symbol number from the decoding means; and the real part of the positive carrier wave is decoded from the reference signal. The signal component that leaks to the imaginary part or real part of the negative carrier when transmitting, or the signal component that leaks to the imaginary part or real part of the negative carrier when transmitting the imaginary part of the positive carrier The transmission path characteristics are detected based on this, and the correction characteristics that are the inverse characteristics of the transmission path characteristics are calculated and stored from the transmission path characteristics, and the stored correction characteristics are used.TheOf the digital information signal from the decoding meansThe information signal is obtained by correcting error components that cannot be corrected in the decoded signal.Correction meansCalculating an approximate value of a phase difference between a pair of nearby carriers among a plurality of carriers using a coefficient representing a transmission path characteristic, and integrating the approximate values by performing each of the set number of carriers. A value is obtained, the previous integrated value is compared with the current integrated value, and the phase of the time window in the guard interval period processing means is sampled so that the obtained integrated value is minimized according to the comparison result. Adjusting means for discretely adjusting in units of one cycleIt is characterized by having.
[0019]
In the present invention, the symbol synchronization signal is generated by the same method as before, an approximate value of the phase difference between neighboring carriers is calculated, and the above-mentioned approximate value of the phase difference is calculated for each of the set number of carriers. Calculated, integrated, and compared the integrated value between the previous input and the current input, and adjusted and controlled the phase of the time window so that the integrated value is minimized according to the comparison result. The beginning of the effective symbol period can be accurately detected.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a transmission system of an orthogonal frequency division multiplex signal transmission method according to the present invention, and FIG. 2 is an embodiment of a reception system and receiver of the orthogonal frequency division multiplex signal transmission method according to the present invention. A block diagram of the form is shown.
[0021]
The configuration of the transmission system in FIG. 1 is the same as that of the transmission device in the patent application previously proposed by the present inventor. In the figure, the input terminal 1 receives digital data to be transmitted. The digital data is, for example, a digital video signal or an audio signal compressed by an encoding method such as an MPEG method that is a color moving image encoding method. This input digital data is supplied to the input circuit 2 and, if necessary, an error correction code is given based on the clock from the clock frequency divider 3. The clock divider 3 divides the 10.7 MHz intermediate frequency from the intermediate frequency oscillator 10 and generates a clock synchronized with the intermediate frequency.
[0022]
The digital data to which the error correction code is added is supplied from the input circuit 2 to the arithmetic unit 4. The arithmetic unit 4 performs an inverse discrete Fourier transform (IDFT) operation on the digital data from the input circuit 2 to generate an in-phase signal (I signal) and a quadrature signal (Q signal), and a symbol number count as described later. The symbol number from the circuit 5 and the reference signal from the reference signal insertion circuit 6 are also supplied to a predetermined input terminal (input unit) for IDFT calculation. That is, a symbol number is inserted into a specific carrier wave, and a known reference signal (reference data) is inserted into another positive and negative carrier wave corresponding to the symbol number.
[0023]
Specifically, the symbol number counting circuit 5 expresses the symbol number by 8 bits, and 0, 1, 2, 3,. . . , 255, 0, 1, 2,. . In this way, the symbol numbers that sequentially change cyclically for each symbol period are counted and output.
[0024]
Here, since accurate decoding of the symbol number is important, dedicated reference data (reference signal) is prepared. Of the 8 bits output from the symbol number counting circuit 5, the 8th, 7th, 3rd, and 2nd 4 bits are input to the arithmetic unit 4 so that they are transmitted by a specific carrier, for example, the first carrier. IDFT operation is performed.
[0025]
The reference signal insertion circuit 6 receives the 8-bit symbol number output from the symbol number counting circuit 5, and calculates a reference signal to insert a reference signal into a predetermined carrier wave obtained based on the upper 7 bits of the symbol number. 4 and IDFT calculation is performed so that the data is transmitted by a predetermined carrier wave. Since the lower one bit of the symbol number is ignored, the reference signal is inserted into the carrier wave having the same value between the two symbols.
[0026]
Also, based on the least significant bit of the 8-bit symbol number, the reference signal insertion circuit 6 inserts the following two types of reference signals into an odd symbol and an even symbol.
[0027]
[Expression 1]

The determinant reference signal represented by equation (1a) is inserted into even symbols, and the determinant reference signal represented by equation (1b) is inserted into odd symbols. Here, X and Y are known reference signal values, p is the real part of the corresponding positive carrier to be transmitted, q is the imaginary part of the corresponding positive carrier to be transmitted, r is the real part of the corresponding negative carrier to be transmitted, and u is transmitted. This is the imaginary part of the negative carrier. The carrier wave into which the reference signal is inserted is a pair of positive and negative carrier frequencies symmetrical with respect to the center carrier frequency F0. Here, switching is performed every two symbols as described above. It is transmitted on a set of carriers. That is, one arbitrary carrier wave transmits a reference signal with a period of 256 symbols.
[0028]
For example, when the data series is transmitted with 256 carrier waves, the calculation unit 4 performs 512-point IDFT calculation to generate a signal by performing IDFT calculation of double oversampling. In this case, the input assignment to the calculation unit 4 is as follows when the numbers are assigned in order in the input frequency alignment type.
[0029]
n = 0 to 128 An information signal for modulating a carrier wave is provided.
[0030]
n = 129 to 383 The carrier level is set to 0 and no signal is generated.
[0031]
n = 384 to 511 An information signal for modulating a carrier wave is provided.
[0032]
The arithmetic unit 4 receives a 4-bit R signal and a 4-bit I signal from the 1st to 127th input terminals and the 385th to 511th input terminals, respectively, as well as 0th, 128th and 384th. A constant voltage is input to the other input terminal, and 0 is input to the other 129th to 383rd input terminals, and a double oversampling IDFT operation is performed. As a result, an in-phase signal (I signal) and a quadrature signal are obtained. After obtaining (Q signal), a guard interval for reducing multipath distortion is inserted into the I signal and Q signal, respectively, and then output to the output buffer 7.
[0033]
Here, the input information of a total of 128 input terminals from the 1st to the 128th is the information transmission carrier on the upper side (higher band side) than the center carrier frequency F0 for transmitting the input information of the 0th input terminal. (This is referred to as a positive carrier or a carrier wave in this specification), and the input information of a total of 128 input terminals from the 384th to the 511th is lower than the center carrier frequency F0 (low frequency band). Side) information transmission carrier (this is referred to as a negative carrier or a carrier in this specification), and in particular, the input pilot signals at the 128th and 384th input terminals are obtained as a result of the IDFT operation as a result of the Nyquist frequency. It is transmitted by a carrier wave having a frequency at both ends equivalent to a half frequency, and 0 is input to the remaining 129th to 383rd input terminals (to be a ground potential), Carriers of the portion is prevented from occurrence (not used for data transmission).
[0034]
In the output buffer 7, the output calculation result of the calculation unit 4 is generated in a burst manner as 256 time information signals (I signal and Q signal) in a single IDFT calculation, Since the circuit after the output buffer 7 operates continuously at a constant reading speed of the contents of the output buffer 7, it is provided to adjust the time difference between the two.
[0035]
Based on the clock from the clock frequency divider 3 in FIG. 1, the I signal and the Q signal, which are IDFT operation results read continuously from the output buffer 7, are converted into a D / A converter / low pass filter (LPF). 8 is converted into an analog signal using the clock from the clock frequency divider 3 as a sampling clock, and then the I signal and Q signal of components in the necessary frequency band are passed by the LPF, and the quadrature modulator 9 Supplied to each.
[0036]
The quadrature modulator 9 uses the intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 10 as the first modulated wave, and the intermediate frequency of 10.7 MHz obtained by shifting the phase of the intermediate frequency by 90 ° by the 90 ° shifter 11 is the second. 257 waves (128 positive and negative carrier pairs and one central carrier wave) are subjected to quadrature amplitude modulation (QAM) with digital data I and Q signals input from the D / A converter and LPF 8 respectively. An OFDM signal composed of a carrier wave is generated. The OFDM signal output from the quadrature modulator 9 is frequency-converted to an RF signal in a predetermined transmission frequency band by the frequency converter 12, and then is transmitted from an antenna (not shown) after undergoing transmission processing such as power amplification at the transmitter 13. The
[0037]
Next, the frequency division multiplex signal receiving apparatus shown in FIG. 2 will be described. As will be described later, this frequency division multiplex signal receiving apparatus is characterized by the configuration of a guard interval period processing circuit 30 and a DFT / QAM decoding circuit 31. In FIG. 2, an OFDM signal input via a spatial transmission path is received by a receiving unit 21 via a receiving antenna, then amplified by high frequency, and further frequency-converted to an intermediate frequency by a frequency converter 22, and an intermediate frequency amplifier. After being amplified by 23, it is supplied to a carrier extraction and quadrature demodulator 24.
[0038]
The carrier extraction circuit portion of the carrier extraction and quadrature demodulator 24 is a circuit that extracts the center carrier wave (carrier) of the input OFDM signal as accurately as possible with little phase error. Here, since each carrier wave for transmitting information is arranged adjacent to every symbol frequency of 387 Hz to form an OFDM signal, the information transmission carrier wave adjacent to the center carrier wave is also separated from the center frequency by 387 Hz. In order to extract the center carrier wave, a circuit with high selectivity is required so as not to be affected by the adjacent information transmission carrier wave separated only by 387 Hz. Therefore, the center carrier F0 is extracted using a PLL circuit in the carrier extraction circuit unit.
[0039]
The center carrier F0 extracted by the carrier extraction and quadrature demodulator 24 is supplied to an intermediate frequency oscillator 25, which generates an intermediate frequency of 10.7 MHz in phase synchronization with the center carrier F0. The output intermediate frequency of the intermediate frequency oscillator 25 is directly supplied to the quadrature demodulator 24 as the first demodulated wave, while the phase is shifted by 90 ° by the 90 ° shifter 26 and then carrier extracted and quadrature as the second demodulated wave. The signal is supplied to the demodulator 24.
[0040]
As a result, an analog signal (frequency division multiplexed signal) equivalent to the analog signal input to the quadrature modulator 9 of the transmitter is demodulated and extracted from the quadrature demodulator unit of the carrier extraction and quadrature demodulator 24, and the synchronization signal While being supplied to the generation circuit 27, a signal in a necessary frequency band transmitted as OFDM signal information by the low-pass filter (LPF) 28 is passed, supplied to the A / D converter 29, and converted into a digital signal. .
[0041]
What is important here is the sampling timing for the input signal of the A / D converter 29, which is generated based on the sample synchronization signal generated from the pilot signal by the synchronization signal generating circuit 27 and having a frequency twice the Nyquist frequency. The In other words, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and the frequency of the pilot signal is multiplied to obtain the timing of the sample clock.
[0042]
The synchronization signal generation circuit 27 receives a demodulated analog signal, and generates a sample clock by a PLL circuit that is phase-synchronized with a pilot signal transmitted as a continuous signal in each symbol period including a guard interval period; It comprises a symbol synchronization signal generation circuit unit that checks the phase state of the pilot signal with a signal extracted from a part of the sample clock generation circuit unit, detects a symbol period, and generates a symbol synchronization signal.
[0043]
When the symbol synchronization signal is generated, for example, as the applicant previously proposed in Japanese Patent Application No. 8-219242, the same guard interval data as the data after the symbol is cyclically arranged. Therefore, paying attention to the fact that there is discontinuity in almost all carriers only at the last data of the guard interval and the start data of the next symbol, the input demodulated signal (both I and Q signals is detected by the high pass filter). And the residual high frequency component having the symbol start point position information (symbol data) is extracted, converted into a pulse train by a peak detector and a comparator, and a PLL (phase locked loop) ) Input to the circuit to generate a jitter-free symbol timing clock, and divide this by dividing the sample clock By frequency dividing the start signal of the frequency divider circuit may be used a configuration in which a dividing circuit to obtain a symbol synchronization signal.
[0044]
The digital signal taken out from the A / D converter 29 is supplied to the guard interval period processing circuit 30, where a predetermined amount of digital signal in the DFT window is based on the sample clock and the symbol synchronization signal from the synchronization signal generation circuit 27. The data string is output to the DFT / QAM decoding circuit 31. The DFT and QAM decoding circuit 31 takes an input digital data sequence based on the sample clock from the synchronization signal generation circuit 27 and performs a complex Fourier operation on the input digital data sequence to obtain a reception complex number demodulated signal (decoded digital information signal). A symbol number is decoded, and a reception reference signal of a positive / negative carrier corresponding to this symbol number is obtained. Based on these, a channel characteristic correction expression is detected, and the received complex demodulated signal is generated based on this correction expression. It is corrected. The DFT / QAM decoding circuit 31 generates a forward signal and a backward signal, which will be described later.
[0045]
The decoded digital information signal output from the DFT / QAM decoding circuit 31 is subjected to output processing such as parallel-serial conversion by the output circuit 32 and is output to the output terminal 33. A forward signal and a backward signal, which will be described later, generated by the DFT / QAM decoding circuit 31 are supplied to the guard interval period processing circuit 30, respectively.
[0046]
FIG. 3 is a block diagram showing an example of the DFT / QAM decoding circuit 31 described above. As shown in the figure, the DFT / QAM decoding circuit 31 includes a DFT arithmetic circuit 311, a correction circuit 312, a control circuit 313, and a phase arithmetic circuit 314. The digital data string input from the guard interval period processing circuit 30 to the DFT / QAM decoding circuit 31 is made up of an I signal I ′ and a Q signal Q ′, which are supplied to the DFT operation circuit 311 where DFT operation is performed. Thus, after being decoded into transmission information R ′ and I ′ that are respective modulation signals, the decoded value is supplied to the correction circuit 312 and the corrected values R ′ and I ′ are output, respectively. It is output to the output circuit 32 of FIG.
[0047]
Next, the operation of the correction circuit 312 will be described. Based on the symbol number in the transmission information decoded by the DFT operation, the correction circuit 312 obtains the received value of the positive / negative carrier corresponding to the symbol number, that is, the received reference signal value. This received reference signal value is p for even symbols._0s', Q_0s', R_0s'And u_0s′, And for odd symbols, p_1s', Q_1s', R_1s'And u_1sSuppose that it was'.
[0048]
Here, as proposed in Japanese Patent Application No. 8-43854, coefficients S0 to S7 expressed by the following equations are calculated from the above reference signal values.
[0049]
[Expression 2]

here,
S0 = (p_0s'・ X-p_1s'・ Y-q_0s'・ Y + q_1s'・ X) / 2 (X²-Y²)
S1 = (p_0s'・ Y-p_1s'・ X + q_0s'・ X-q_1s'・ Y) / 2 (X²-Y²)
S2 = (p_0s'・ X-p_1s'・ Y + q_0s'・ Y-q_1s'・ X) / 2 (X²-Y²)
S3 =-(p_0s'・ Y-p_1s'・ X-q_0s'・ X + q_1s'・ Y) / 2 (X²-Y²)
S4 = (r_0s'・ X-r_1s'・ Y + u_0s'・ Y-u_1s'・ X) / 2 (X²-Y²)
S5 =-(r_0s'・ Y-r_1s'・ X-u_0s'・ X + u_1s'・ Y) / 2 (X²-Y²)
S6 = (r_0s'・ X-r_1s'・ Y-u_0s'・ Y + u_1s'・ X) / 2 (X²-Y²)
S7 = (r_0s'・ Y-r_1s'・ X + u_0s'・ X-u_1s'・ Y) / 2 (X²-Y²)
It is.
[0050]
Of the above coefficients, S0 represents the rate at which the real part of the positive carrier is transmitted to the real part of the positive carrier, and the rate at which the imaginary part of the positive carrier is transmitted to the imaginary part of the positive carrier. Yes. S1 indicates the rate at which the real part of the positive carrier leaks into the imaginary part of the positive carrier, and the rate at which the imaginary part of the positive carrier leaks into the real part of the positive carrier. S2 indicates the rate at which the real part of the negative carrier leaks to the real part of the positive carrier, and the rate at which the imaginary part of the negative carrier leaks to the imaginary part of the positive carrier.
[0051]
S3 indicates the rate at which the real part of the negative carrier leaks to the imaginary part of the positive carrier, and the rate at which the imaginary part of the negative carrier leaks to the real part of the positive carrier. S4 indicates the rate at which the real part of the positive carrier leaks to the real part of the negative carrier, and the rate at which the imaginary part of the positive carrier leaks to the imaginary part of the negative carrier.
S5 indicates the rate at which the real part of the positive carrier leaks to the imaginary part of the negative carrier, and the rate at which the imaginary part of the positive carrier leaks to the real part of the negative carrier. S6 indicates the rate at which the real part of the negative carrier is transmitted to the real part of the negative carrier, and the rate at which the imaginary part of the negative carrier is transmitted to the imaginary part of the negative carrier. S7 indicates the rate at which the real part of the negative carrier leaks to the imaginary part of the negative carrier, and the rate at which the imaginary part of the negative carrier leaks to the real part of the negative carrier. Here, the description of-and + of a rate was abbreviate | omitted.
[0052]
That is, the above coefficients S0 to S7 indicate the characteristics of the transmission path of the I signal and the Q signal, and the characteristics of the transmission path are detected by calculating these coefficients S0 to S7 from the received reference signal value according to the above equation. It will be possible.
[0053]
Further, by obtaining the inverse matrix of equation (2), it is possible to correct the reception data and estimate the transmission data. Here, the inverse matrix of the equation (2) is expressed by the following equation.
[0054]
[Equation 3]

However, H0 to H7 and det A in the above formula are represented by the following formulas.
[0055]
H0 = + S0 (S6S6 + S7S7) -S2 (S4S6 + S5S7) + S3 (S4S7-S5S6)
H1 = + S1 (S6S6 + S7S7) -S3 (S4S6 + S5S7) -S2 (S4S7-S5S6) H2 = + S4 (S2S2 + S3S3) -S6 (S0S2 + S1S3) + S7 (S0S3-S1S2) H3 = + S5 (S2S2 + S3S3) -S7 (S0S2 + S1S3) -S6 (S0S3-S1S2) H4 = + S2 (S4S4 + S5S5) -S0 (S4S6 + S5S7) -S1 (S4S7-S5S6) H5 = + S3 (S4S4 + S5S5 ) -S1 (S4S6 + S5S7) + S0 (S4S7-S5S6) H6 = + S6 (S0S0 + S1S1) -S4 (S0S2 + S1S3) -S5 (S0S3-S1S2) H7 = + S7 (S0S0 + S1S1) -S5 ( S0S2 + S1S3) + S4 (S0S3-S1S2) det A = S0 × H0 + S1 × H1 + S4 × H2 + S5 × H3
Therefore, the correction circuit 312 calculates det A and H0 to H7 from the input coefficients S0 to S7 based on the above equation, and further, from these calculated values, of the inverse matrix in the equation (3), The value of the correction formula is calculated and stored.
[0056]
[Expression 4]

In this way, a correction formula for the corresponding positive and negative carrier waves is prepared. The corresponding positive / negative carrier wave is determined by the symbol number. Of course, there are correction equations for each carrier wave, and when 257 carriers are used as in this embodiment, about 128 correction equations are sequentially calculated and held. Further, since the coefficients S0 to S7 are changing every moment, the correction formula is also updated every moment.
[0057]
The correction circuit 312 corrects the reception information from the DFT calculation circuit 311 by calculating the following expression for each pair of positive and negative carriers using the correction expression calculated and held based on the received reference signal value. Thus, the corrected transmission information R ′ and I ′ are output.
[0058]
[Equation 5]

However, in the equation (5), a to d are reception-corrected reception data assigned to the corresponding negative carrier, with the reception-corrected reception data assigned to the corresponding positive carrier (after correction) being a complex number (a + jb). The value when the complex number after (correction) is (c + jd), a ′ to d ′ are reception decoded and the reception data allocated to the corresponding positive carrier (before correction) is (a ′ + jb ′). This is a value when the complex number of received data (before correction) assigned to the corresponding negative carrier is (c ′ + jd ′).
[0059]
Next, operations of the control circuit 313 and the phase calculation circuit 314 which are the main parts of the present embodiment will be described. In an initial state such as when the power is turned on, a DFT window is designated based on the symbol synchronization signal output from the synchronization signal generation circuit 27, and a digital data string in the DFT window is input to the DFT operation circuit 311 and subjected to DFT operation. After that, it is input to the correction circuit 312 and the above correction operation is performed.
[0060]
At this time, based on the decoded symbol number input from the correction circuit 312, the control circuit 313 monitors whether the symbol number has made a complete round, that is, whether one frame period has elapsed. This is because the coefficients S0 to S7 are obtained for all carriers. When it is detected that the symbol number has been completed, the control circuit 313 issues a calculation command to the phase calculation circuit 314.
[0061]
The phase calculation circuit 314 takes in the coefficients S0, S1, S6, and S7 of each carrier held by the correction circuit 312 based on this calculation command, performs the following calculation, and outputs the calculation result (integrated value) to the control circuit 313. Watas. Here, the coefficients S0 and S1 remarkably represent the characteristics of the positive carrier, and the coefficients S6 and S7 remarkably represent the characteristics of the negative carrier. Performance can be secured. The coefficients S2 to S5 are smaller values than the coefficients S0, S1, S6, and S7, and may be ignored, including the effect of reducing the amount of calculation.
[0062]
Next, the calculation operation of the phase calculation circuit 314 will be described. Now the coefficients S0 and S1 of the + 10th carrier are set to S0₊₁₀, S1₊₁₀, The coefficients S6 and S7 of the −10th carrier are set to S6_-Ten, S7_-Ten, The coefficients S0 and S1 of the + 20th carrier are set to S0₊₂₀, S1₊₂₀The coefficients S6 and S7 of the -20th carrier are set to S6_-20, S7_-20Then, these transmission line characteristic coefficients are shown in FIG.
[0063]
Therefore, the phase difference θ between the + 10th carrier and the + 20th carrier can be expressed by the following equation.
[0064]

Therefore, the phase calculation circuit 314 calculates the phase difference θ between the + 10th carrier and the + 20th carrier as tan (θ₊₂₀−θ₊₁₀)

Is calculated. Similarly, the phase calculation circuit 314 approximates the phase difference θ between the −10th carrier and the −20th carrier by tan (θ),

Is calculated. Hereinafter, similarly, the phase difference θ between the + X carrier and the (X + 10) carrier is approximately
I_{+ X}= {S0_{+ X}・ S1_{+ X + 10}-S0_{+ X + 10}・ S1_{+ X}} / {S0_{+ X}・ S0_{+ X + 10}+ S1_{+ X}・ S1_{+ X + 10}}
Approximate the phase difference θ between the −Xth carrier and the − (X + 10) th carrier.
I_-X= {S6_-X・ S7_-X-10-S6_-X-10・ S7_-X} / {S6_-X・ S6_-X-10+ S7_-X・ S7_-X-10}
Is calculated.
[0065]
Here, X is a positive integer, and 10, 20, 30, 40, 50,. . . Takes the value of For example, when the number of carriers is ± 128, X =. . . , 100, and 110.
[0066]
In this embodiment, the phase difference for every 10 carriers is obtained. However, for example, the final result to be obtained every 5 carriers or every 20 carriers, that is, the determination result is not affected. When the calculation time is limited, the calculation may be performed only in the positive carrier direction on one side, or the carrier at the end may be omitted.
[0067]
Next, the phase calculation circuit 314 adds the phase differences in the positive direction and the negative direction, sums the absolute values to obtain an integrated value I, and outputs this to the control circuit 313 as the calculation result. here,

It is. After storing the calculation result (integrated value I), the control circuit 313 compares the previous integrated value with the current integrated value, and when the current integrated value is less than or equal to the previous integrated value, the guard interval period processing circuit. A forward signal is output to 30, and when the current integrated value is larger than the previous integrated value, a backward signal is output to the guard interval period processing circuit 30. When this integrated value is minimum, the DFT window and the effective symbol period coincide.
[0068]
Next, the configuration and operation of the guard interval period processing circuit 30 will be described with reference to FIGS. The guard interval period processing circuit 30 includes a data management circuit 301 and an adjustment circuit 302 as shown in FIG. Based on the start signal output from the adjustment circuit 302, the data management circuit 301 generates 512 digital data from the output digital data string (I signal I ′, Q signal Q ′) of the A / D converter 29 shown in FIG. Is transmitted to the DFT and QAM decoding circuit 31.
[0069]
The adjustment circuit 302 clears the count value with the symbol synchronization signal shown in FIG. 5A input from the synchronization signal generation circuit 27 at the start of operation, and thereafter the adjustment circuit 302 receives the signal from the synchronization signal generation circuit 27 (B). ) And a start signal is output to the data management circuit 301 as shown in FIG. 5C every 524 counts.
[0070]
In this case, since decoding is performed by 512-point DFT operation, one symbol of the OFDM signal schematically shown in FIG. 5E is composed of 512 digital data and 12 digital data for the guard interval. Thus, the symbol synchronization signal and the sample clock have the relationship shown in FIGS. Here, the output digital data sequence of the A / D converter 29 schematically shown in FIG. 5D is only 512 data from the start signal in the DFT window among the 524 digital data constituting one symbol. Data is transmitted to the DFT / QAM decoding circuit 31 and the remaining 12 data are not transmitted.
[0071]
As described in FIG. 12, the start signal in FIG. 5C is not in a phase relationship for cutting out the data of the correct effective symbol period of the OFDM signal shown in FIG. ) Is not in the interference area of adjacent symbols indicated by hatching, so that data can be decoded. However, in this state, adjacent carriers have greatly different coefficients in the phase relationship.
[0072]
The adjustment circuit 302 thins out one sample clock when the forward signal is input from the DFT / QAM decoding circuit 31. As a result, the start signal output from the adjustment circuit 302 is a signal delayed by one sample clock period as shown in FIG. In response to this start signal, the data management circuit 301 transmits the second to 513th digital data strings compared with the digital data string in the initial state, and the first one and the last remaining eleven. It operates by setting a DFT window that does not transmit minutes.
[0073]
Thereafter, since the adjustment circuit 302 outputs the start signal delayed by one sample clock period by thinning out one sample clock with respect to the next forward signal, the data management circuit 301 performs the operation from the third to the 514th. The digital data string is transmitted, and the first two and the last ten are not transmitted. Thereafter, similarly, the start signal gradually moves toward the end of the guard interval, and the data management circuit 301 operates so as to gradually transmit the rear digital data string.
[0074]
The integrated value of the phase difference is minimized when the start signal is at the last position of the guard interval, increases when the start signal enters the effective symbol period, and the integrated value of the phase difference becomes closer to the head of the guard interval. growing. Therefore, when the start signal comes in the effective symbol period, a backward signal is output from the DFT / QAM decoding circuit 31. Thus, the adjustment circuit 302 operates to add one sample clock.
[0075]
As a result, the start signal output from the adjustment circuit 302 is a signal whose phase is advanced by one sample clock period. In response to this start signal, the data management circuit 301 operates so as to transmit a data string ahead by one compared with the digital data string in the initial state. Similarly, the start signal gradually moves toward the interference area with the adjacent symbol, and the data management circuit 301 operates so as to gradually transmit the front digital data string.
[0076]
For example, as shown in FIG. 6, the adjustment circuit 302 includes a 512 frequency dividing circuit 3021, a shift register 3022, and a selector 3023. The adjustment circuit 302 outputs a divided pulse every time 512 sample clocks are counted when the 512 divider circuit 3021 is cleared by the symbol synchronization signal. The shift register 3022 receives this frequency-divided pulse, performs a shift operation in synchronization with the sample clock, and inputs, for example, an 8-bit output to the selector 3023.
[0077]
When the forward signal is input to the up terminal, the selector 3023 selects an output pulse whose phase is delayed by one sample clock from the previous output from the output of the shift register 3022, and when the backward signal is input to the down terminal. A pulse whose phase is advanced by one sample clock from the previous time is selected and output as a start signal.
[0078]
The guard interval period processing circuit 30 receives the forward signal and performs the above-described operation, and the control circuit 313 in the DFT / QAM decoding circuit 31 receives the symbol based on the symbol number transmitted by the correction circuit 312 as in the previous time. It is monitored whether or not the circuit has made a round, and when it is detected that the symbol has made a round, a calculation command is issued to the phase calculation circuit 314. Similarly to the previous time, the phase calculation circuit 314 takes in the coefficients S0, S1, S6, and S7 of each carrier held by the correction circuit 312 based on the calculation command, and passes the calculation result (integrated value) to the control circuit 313.
[0079]
As described above, the control circuit 313 compares the previous integration result with the current integration result. If the current integration result is smaller, the control circuit 313 further issues a forward signal and repeats the above operation. If the magnitude of the integration result is larger this time (meaning that the minimum value of the phase was the previous time), a backward signal is generated and the determination of the optimum position is completed.
[0080]
As another embodiment of the guard interval period processing circuit 30 and the DFT / QAM decoding circuit 31, the guard interval period processing circuit 30 is constituted by a storage circuit for several symbols, and the output symbol synchronization of the synchronization signal generating circuit 27 is performed. Based on the signal and the sample clock, the digital data string may be configured in a ring shape, and the DFT / QAM decoding circuit 31 may be configured by a central processing unit (CPU) processor.
[0081]
FIG. 8 is a flowchart for explaining the operation of the CPU processor constituting the DFT / QAM decoding circuit 31. In the figure, when the power is turned on (step 41), it is monitored whether or not the symbol number from the correction circuit 312 has made a round (step 42). The coefficients S0, S1, S6, and S7 are taken in and the above-described phase difference integration calculation is performed (step 43). When the calculation is the first time, the process returns to step 42 to monitor whether or not the symbol number has made a round. If it is after the first time, the previous integration result is compared with the current integration result (steps 44 and 45).
[0082]
In step 45, if the current integration result is less than that of the previous time, a forward signal is issued, and as described above, the data management circuit 301 sets the address of the data capture position so as to transmit one data string ahead. Go forward by one (step 46), and return to step 42 to monitor whether the symbol number has made a round.
[0083]
In step 45, if the current integration result is greater than that of the previous time (meaning that the minimum value of the phase was the previous time), a backward signal is generated, and the data management circuit 301 is one piece of data behind The address of the data capture position is returned by one so as to transmit the column (step 47), and the determination of the optimum position is completed (step 48).
[0084]
As an example of the symbol configuration, it is conceivable to insert a pre-guard interval in addition to the guard interval. That is, when the 512-point IFFT calculation result is as shown in FIG. 9A, among the 512 digital data B, the first two digital data are A, and the last ten digital data are C. As shown in FIG. 5B, 512 digital data B are arranged in the effective symbol period, 10 digital data C are arranged in the first guard interval, and 2 digital data are arranged in the last preguard interval. Data A is arranged to constitute one symbol.
[0085]
This is a countermeasure against interference with a ghost wave that arrives before the desired wave. The present invention can also be applied to an OFDM signal having such a configuration.
[0086]
Further, in the present embodiment, an example in which the reference signal insertion method is transmitted / received by a pair of positive and negative carrier waves has been described. However, as described above, coefficients S0, S1 and S6, S7 are used, and coefficients S2 to S5 are used. Sufficient accuracy can be ensured without using. That is, as another example, the present invention is sufficiently applicable to an OFDM signal transmission / reception system that does not transmit / receive a reference signal using a set of positive and negative carriers.
[0087]
【The invention's effect】
As described above, according to the present invention, the approximate value of the phase difference between neighboring carriers is calculated, and the approximate value of the above phase difference is calculated for each of the set number of carriers, and these are integrated. Then, by comparing the accumulated value between the previous input and the current input, and adjusting and controlling the phase of the time window so that the accumulated value is minimized according to the comparison result, the start of the effective symbol period is started. Since accurate detection is possible, when noise is removed by coefficient addition averaging between neighboring carriers, the deviation of the averaged coefficient that occurs can be reduced as much as possible, thereby improving the performance of the apparatus.
[0088]
In addition, according to the present invention, the performance related to the generation of the symbol synchronization signal may be the same as the conventional one, and the position shift of the symbol synchronization signal can be minimized with a simple circuit or software.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a transmission system of an orthogonal frequency division multiplexing signal transmission method according to the present invention.
FIG. 2 is a block diagram of an embodiment of a reception system and a reception apparatus of an orthogonal frequency division multiplexing signal transmission method according to the present invention.
3 is a block diagram of an example of a DFT / QAM decoding circuit in FIG. 2. FIG.
4 is a block diagram of an example of a guard interval period processing circuit in FIG. 2. FIG.
FIG. 5 is a timing chart for explaining the operation of FIG. 4;
6 is a block diagram of an example of an adjustment circuit in the guard interval period processing circuit of FIG. 4. FIG.
7 is a diagram for explaining the operation of the phase calculation circuit of FIG. 3; FIG.
FIG. 8 is a flowchart for explaining the operation when the DFT / QAM decoding circuit is configured by a CPU processor;
FIG. 9 is a diagram illustrating another symbol configuration example to which the present invention can be applied.
FIG. 10 is a waveform diagram of a baseband time axis of an OFDM signal.
FIG. 11 is a diagram illustrating an example of a symbol configuration of an OFDM signal.
FIG. 12 is a diagram illustrating a symbol synchronization signal position when a desired wave and a delayed ghost wave are received.
[Explanation of symbols]
2 Input circuit
3 Clock divider
4 Calculation unit
5 Symbol number counting circuit
6 Reference signal insertion circuit
7 Output buffer
8 D / A converter and low-pass filter (LPF)
9 Quadrature modulator
10, 25 Intermediate frequency oscillator
11, 26 90 ° shifter
12, 22 Frequency converter
21 Receiver (Receiving means)
24 Carrier extraction and quadrature demodulator (demodulation means)
27 Synchronization signal generation circuit (synchronization signal generation means)
29 A / D converter
30 guard interval period processing circuit (guard interval period processing means)
31 DFT, QAM decoding circuit
32 Output circuit
301 Data management circuit
302 Adjustment circuit (adjustment control means)
311 DFT arithmetic circuit (decoding means)
312 Correction circuit (correction means)
313 Control circuit (adjustment control means)
314 Phase calculation circuit (phase calculation means)
3021 512 divider circuit
3022 Shift register
3023 selector

Claims (3)

On the transmission side, a known reference signal and pilot signal reference data corresponding to the value of the information signal to be transmitted and the symbol number that sequentially changes for each symbol period and makes a round in one frame period are synchronized with the sample clock. after inverse discrete Fourier transform, by quadrature modulation, each of the plurality of carrier waves of different frequencies from each other, separately modulated with an information signal the to be transmitted allocated to each carrier, the symbol of the plurality of carriers while inserting the known reference signal to a predetermined carrier wave which changes according to the value of the number, by inserting a pilot signal set to a predetermined integer ratio to the frequency of the sample clock to a predetermined carrier wave, Generates frequency-division multiplexed orthogonal frequency division multiplexed signals and transmits them in symbol units consisting of guard intervals and effective symbol periods.
On the receiving side, after quadrature demodulating the orthogonal frequency division multiplex signal received, based on said pilot signal in the quadrature demodulated signal, and generates a symbol synchronization signal of the sample clock and the symbol unit, the sample Ru is included in the time window that is set based on the clock and symbol synchronization signals, orthogonal frequency division multiplexing said quadrature demodulation signal to decode the information signal and the reference signal to be the transmission with discrete Fourier transform on the basis of the sample clock A signal transmission method comprising:
For each of the set number of carriers, the receiving side calculates an approximate value of a phase difference between a pair of nearby carriers among the plurality of carriers by using a coefficient representing the channel characteristic of the carrier. To determine the integrated value of those approximate values, compare the previous integrated value with the current integrated value, and according to the comparison result, adjust the phase of the time window so that the integrated value obtained is minimized. Discretely adjusting in units of one cycle of the sample clock ,
The channel characteristic of the carrier wave is detected using the value of the reference signal inserted into the predetermined carrier wave that has been subjected to the discrete Fourier transform, and correction that is opposite to the channel characteristic from the detected channel characteristic A demodulated signal obtained by performing the discrete Fourier transform on the orthogonal demodulated signal based on the sample clock, which is included in the discretely phase-adjusted time window using the correction characteristic. An orthogonal frequency division multiplex signal transmission method, wherein the information signal is obtained by correcting an error component that cannot be corrected . On the transmission side, the information signal to be transmitted is subjected to inverse discrete Fourier transform in synchronization with the sample clock, and then orthogonally modulated to transmit digital information signals to be transmitted on a plurality of carriers having different frequencies, and A known reference signal is inserted into a set of a positive carrier on the high frequency side and a negative carrier on the low frequency side that are symmetrical with respect to the center carrier , and the frequency of the sample clock is set in a predetermined carrier. set pilot signal to a predetermined integer ratio is inserted against the set of the insertion position of the positive and negative carrier waves for transmitting the reference signal, designated by the symbol number be transmitted in a particular transport wave, and, at regular intervals Are sequentially cyclically changed to generate an orthogonal frequency division multiplexed signal that is frequency division multiplexed and transmitted in units of symbols including a guard interval and an effective symbol period,
On the receiving side, after quadrature demodulating the frequency division multiplexed signal received, based on said pilot signal in the quadrature demodulated signal, and generates the sample clock and the symbol sync signal, the sample clock and the symbol synchronization signal Ru is included in the time window that is set based on, the quadrature demodulating signal by decoding the information signal and the symbol number to be the transmission with discrete Fourier transform on the basis of the sample clock, on the basis of the said symbol number of decoding When the reference signal is decoded and the real part of the positive carrier wave is transmitted from the reference signal, the signal component leaking to the imaginary part or the real part of the negative carrier wave or the imaginary part of the positive carrier wave is transmitted. The transmission path characteristics are detected based on the signal component leaking to the imaginary part or the real part of the negative carrier, and the detected transmission A orthogonal frequency division multiplex signal transmitting method for correcting the information signal decoded using a road characteristic,
The receiving side calculates an approximate value of a phase difference between a pair of nearby carriers among the plurality of carriers using a signal component that leaks out the transmission path characteristics, for each of the set number of carriers. The integrated value of those approximate values is obtained every predetermined period, the previous integrated value is compared with the current integrated value, and the integrated value obtained is minimized according to the comparison result. The phase of the window is discretely adjusted in units of one cycle of the sample clock ,
A correction characteristic that is an inverse characteristic of the detected transmission line characteristic is calculated and stored, and the quadrature demodulated signal included in the discretely phase-adjusted time window using the correction characteristic is calculated based on the sample clock. An orthogonal frequency division multiplex signal transmission method, wherein the information signal is obtained by correcting an uncorrectable error component of the demodulated signal obtained by the discrete Fourier transform. An information signal to be transmitted is subjected to inverse discrete Fourier transform in synchronization with a sample clock, and then orthogonally modulated to transmit a digital information signal to be transmitted using a plurality of carriers having different frequencies, and among the plurality of carriers. A known reference signal is inserted into a set of a high-frequency side positive carrier wave and a low-frequency side negative carrier wave that are symmetrical with respect to the center carrier wave, and a predetermined carrier wave has a predetermined frequency with respect to the frequency of the sample clock. set pilot signals to the integer ratio is inserted, the set of the insertion position of the positive and negative carrier waves for transmitting the reference signal, designated by the symbol number be transmitted in a particular transport wave, and sequentially cyclically every predetermined period of time The orthogonal frequency division multiplex signal that is transmitted in symbol units consisting of a guard interval and an effective symbol period is received. And receiving means,
Demodulating means for orthogonally demodulating the received orthogonal frequency division multiplexed signal from the receiving means to obtain an information signal represented by a complex number, the symbol number , the reference signal, and the pilot signal ;
Synchronization signal generation means for generating a symbol synchronization signal of the sample clock and the symbol unit period based on the pilot signal from the demodulation means;
Guard interval period processing means for discretely setting a time window based on the symbol synchronization signal and the sample clock , and allowing the information signal from the demodulation means and the symbol number and the reference signal to pass through the time window, respectively.
Decoding the digital information signal by performing discrete Fourier transform on the signal from the guard interval period processing means based on the sample clock, and decoding the symbol number and the reference signal;
A signal component that leaks to the imaginary part or the real part of the negative carrier when the reference signal is decoded from the symbol number from the decoding means and the real part of the positive carrier is transmitted from the reference signal; Alternatively, when transmitting the imaginary part of the positive carrier wave, the transmission line characteristic is detected based on the signal component leaking to the imaginary part or the real part of the negative carrier wave, and the transmission line characteristic is detected from the transmission line characteristic. A correction characteristic which is an inverse characteristic of the digital signal is calculated and stored, and the stored correction characteristic is used to correct an error component which cannot be corrected in the decoded signal of the digital information signal from the decoding means. and correction means for obtaining,
Using the coefficient representing the transmission path characteristic, calculating an approximate value of the phase difference between a pair of nearby carriers among the plurality of carriers is performed for each of the set number of carriers, and An integrated value is obtained, the previous integrated value is compared with the current integrated value, and the phase of the time window in the guard interval period processing means is set so that the integrated value obtained is minimized according to the comparison result. An orthogonal frequency division multiplex signal receiving apparatus comprising: adjusting means for discretely adjusting the frequency of the sample clock in units of one cycle .

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