JP3701068B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device whose memory capacity can be changed after completion of a wafer process.
[0002]
[Prior art]
FIG. 28 is a schematic diagram showing a conventional semiconductor memory device formed on a wafer.
[0003]
Referring to FIG. 28, a rectangular region surrounded by dicing line 697 is a semiconductor memory device 699 having a 4 Mbit capacity. As can be seen from FIG. 28, a plurality of 4 Mbit semiconductor memory devices 699 are formed on the wafer 695.
[0004]
FIG. 29 is an enlarged view of one of a plurality of conventional semiconductor memory devices 699 formed on wafer 695 in FIG. Note that portions similar to those in FIG. 28 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0005]
Referring to FIG. 29, conventional semiconductor memory device 699 is formed in a region surrounded by dicing line 697. This conventional semiconductor memory device 699 includes a plurality of pads 701, an address buffer block 705, a decoder 711, a sense amplifier block 707, an output buffer block 709, a plurality of pads 703, and a 1M bit memory cell matrix M1, M2, M3, M4. Is included.
[0006]
Although not shown, the address buffer block 705 includes a plurality of address buffers corresponding to the plurality of pads 701. Although not shown, the output buffer block 709 includes a plurality of output buffers corresponding to the plurality of pads 703. Although not shown, the sense amplifier block 707 includes a plurality of sense amplifiers corresponding to a plurality of output buffers.
[0007]
The plurality of pads 701 receive a plurality of address signals from the outside. Address buffer block 705 receives a plurality of address signals from a plurality of pads 701. Memory cell matrices M1, M2, M3, and M4 each include a plurality of memory cells for storing information. The decoder 711 receives an address signal from the address buffer 705 and selects one memory cell from the plurality of memory cells.
[0008]
The sense amplifier included in the sense amplifier block 707 is for amplifying a minute signal from the memory cell. The output buffer included in the output buffer block 709 is for receiving the signal amplified by the sense amplifier and outputting it to the outside. A signal from the output buffer is output to the outside via the pad 703.
[0009]
When assembling into a product, that is, during assembly, the wafer 695 of FIG. 28 is cut along a dicing line 697. Here, the semiconductor memory device of FIG. 29 is a semiconductor memory device after cutting. A pad of the semiconductor memory device after cutting in FIG. 29 and a lead frame (not shown) are connected by a wire. In this way, a plurality of products operating at 1 Mbit × 4 = 4 Mbit are produced.
[0010]
As described above, after completion of the wafer process, the product obtained by cutting the dicing line 697 of the wafer 695 is only one type of product. That is, one type of product is made from one wafer 695.
[0011]
Conventionally, designing is performed for each type of product (for each type of semiconductor memory device), a mask is manufactured, and a wafer process is performed.
[0012]
[Problems to be solved by the invention]
As long as the configuration of the semiconductor memory device is as shown in FIG. 29, only one type of product can be obtained from one wafer 695. When a plurality of types of products having different memory capacities and functions are produced, an independent design and wafer are used. A process is required.
[0013]
For this reason, there are problems that the design period and the trial production period of the semiconductor memory device become long and the development cost becomes large.
[0014]
As long as the configuration of the semiconductor memory device is as shown in FIG. 29, the semiconductor memory device (product) in which memory cells that cannot be relieved by the redundancy function (redundancy) are discarded as defective products. The probability of being discarded as a defective product increases as the capacity of the semiconductor memory device (product) increases. In some cases, only a few good products can be obtained with one wafer. That is, since there is only one type of product corresponding to one wafer, a semiconductor memory device (product) that cannot relieve many defective memory cells is discarded.
[0015]
For this reason, there existed a problem that manufacturing cost became high.
Even if the semiconductor memory device (product) has a defective memory cell that cannot be remedied, for example, if the semiconductor memory device (product) has 4 Mbits, 1 Mbit or 2 Mbit may operate.
[0016]
For this reason, in spite of a large number of normal memory cells, there is a problem that it is not economically efficient to dispose of them as defective products.
[0017]
The redundancy function (redundancy) refers to a function for replacing a defective memory cell with a spare memory cell.
[0018]
The present invention has been made to solve the above-described problems, and provides a semiconductor memory device capable of reducing the design period and the prototype period of the semiconductor memory device and reducing the development cost. For the purpose.
[0019]
Another object of the present invention is to provide a semiconductor memory device capable of reducing the manufacturing cost.
[0020]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a first memory device, a second memory device, and a selection unit. The first and second storage devices read or write information.
[0021]
The first storage device includes a first buffer block, a second buffer block, a first pad block, and a second pad block. The first buffer block includes a plurality of first buffers for transmitting / receiving a plurality of first signals. The second buffer block includes a second buffer for transmitting / receiving the second signal.
[0022]
The first pad block is connected to a plurality of first buffers, and includes a plurality of first pads for transmitting and receiving a plurality of first signals to the outside. The second pad block is connected to the second buffer and includes a second pad for transmitting / receiving the second signal to / from the outside.
[0023]
The second storage device includes a third buffer block, a fourth buffer block, a third pad block, and a fourth pad block. The third buffer block includes a plurality of third buffers for transmitting / receiving a plurality of third signals. The fourth buffer block includes a fourth buffer for exchanging the fourth signal.
[0024]
The third pad block is connected to a plurality of third buffers, and includes a plurality of third pads for transmitting and receiving a plurality of third signals to the outside. The fourth pad block is connected to the fourth buffer and includes a fourth pad for exchanging the fourth signal to the outside.
[0025]
When assembly is performed using the first and second storage devices as separate storage devices (hereinafter, referred to as “first mode”), the first storage device and the second storage device are disconnected.
[0026]
When the first and second storage devices are assembled and used as one storage device (hereinafter referred to as a “second aspect”), the second buffer and the fourth buffer have the corresponding third Connected to the pad. In the case of the second mode, the corresponding third pad is used for transmission / reception of the second signal and the fourth signal. In the case of the second mode, a plurality of first buffers and a plurality of first pads are used to exchange the plurality of first signals and the plurality of third signals.
[0027]
The selection means selects whether the third pad is used for the second signal or the fourth signal. This selection means is used in the case of the second mode.
[0028]
In the case of the second mode, when the first storage device is selected by an external selection signal, the plurality of first pads are used for transmission / reception of the plurality of first signals. When the second storage device is selected by the selection signal, the plurality of first pads are used for sending and receiving the plurality of third signals.
[0029]
As described above, in the semiconductor memory device according to the present invention, the first memory device and the second memory device can be assembled as separate memory devices, or the first memory device and the second memory device can be assembled. It is also possible to assemble the storage device as one storage device. That is, when the semiconductor memory device according to the present invention is formed on a wafer, the storage capacity can be made variable during assembly.
[0030]
Therefore, in the semiconductor memory device according to the present invention, a plurality of products can be manufactured from one wafer, the design period and the trial production period can be shortened, and the development cost can be reduced. it can.
[0031]
In addition, even if the semiconductor memory device is a defective product as a whole, if either the first storage device or the second storage device is a non-defective product, the non-defective first storage device or the second storage device Either can be commercialized. For this reason, it is not necessary to discard the entire semiconductor memory device as a defective product, and the manufacturing cost can be reduced.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor memory device according to the present invention will be described with reference to the drawings.
[0033]
(Embodiment 1)
FIG. 1 is a schematic block diagram showing a semiconductor memory device according to the first embodiment of the present invention. Note that the semiconductor memory device of FIG. 1 is formed on a wafer and before the wafer is cut along a dicing line. In other words, the semiconductor memory device of FIG. 1 is the one before assembly. Such a semiconductor memory device shown in FIG. 1 may be called a “basic chip”.
[0034]
Referring to FIG. 1, the semiconductor memory device according to the first embodiment includes a first memory device 100, a second memory device 200, a third memory device 300, and a fourth memory device 400. The first storage device 100 is formed in a region surrounded by dicing lines 1, 17, 23, 15. The first storage device 100 includes a plurality of pads 101, two pads 103, an address buffer block 105, a 1M bit memory cell matrix M1, a decoder 107, a sense amplifier block 109, an output buffer block 111, a plurality of fuses 115, and a plurality of fuses. The pad 113 is included.
[0035]
The address buffer block 105 includes a plurality of address buffers (not shown). The plurality of address buffers are connected to a plurality of pads 101 and two pads 103. The output buffer block 111 includes a plurality of output buffers (not shown). The plurality of output buffers are connected to the plurality of pads 113 through the plurality of fuses 115. The sense amplifier block 109 includes a plurality of sense amplifiers (differential amplifiers).
[0036]
The plurality of pads 101 and 103, the plurality of address buffers included in the address buffer block 105, the plurality of pads 113, and the plurality of output buffers included in the output buffer block 111 are all arranged in the same direction. Further, the plurality of pads 101 and 103 and the plurality of address buffers included in the address buffer block 105 are close to each other. The plurality of pads 113 and the plurality of output buffers included in the address buffer block 111 are close to each other.
[0037]
The second storage device 200 is formed in a region surrounded by the dicing lines 23, 19, 11, and 13. The second storage device 200 is different from the first storage device 100 in the following points.
[0038]
The second storage device 200 does not have the pads and address buffers corresponding to the two pads 103 of the first storage device 100 and the two corresponding address buffers. The pad 201 of the second storage device 200 is connected to the address buffer block 205 via the fuse 217, whereas the pad 101 of the first storage device corresponding to the pad 201 is connected to the address buffer block 105. It differs in that it is directly connected. In addition, the fuse 219 is connected to the pad 201 of the second storage device 200, whereas the fuse 101 is not connected to the pad 101 of the first storage device 100 corresponding to the pad 201. Yes.
[0039]
Further, one output buffer of the output buffer block 111, one output buffer of the output buffer block 211, one output buffer of the output buffer block 311, and one output buffer of the output buffer block 411 are included in the second storage device 200. The difference is that the connection is made to one pad 201 via one fuse 219, whereas such a connection is not made to the pad 101 of the first storage device 100 corresponding to the pad 201. Yes. This connection will be described in detail with an example.
[0040]
First, it is assumed that each of the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 includes four data input / output line pairs. In this case, each of the sense amplifier blocks 109, 209, 309, and 409 includes four sense amplifiers. Four output buffers are included in each of the output buffer blocks 111, 211, 311, and 411. There are also four fuses 115, 215, 315, and 415, respectively. There are also four pads 113, 213, 313, and 413, respectively.
[0041]
The leftmost output buffer of the output buffer block 111, the leftmost output buffer of the output buffer block 211, the leftmost output buffer of the output buffer block 311 and the leftmost output buffer of the output buffer block 411 are The leftmost pad 201 is connected through a fuse 219.
[0042]
The second output buffer from the left of the output buffer block 111, the second output buffer from the left of the output buffer block 211, the second output buffer from the left of the output buffer block 311 and the second output from the left of the output buffer block 411 The buffer is connected to the second pad 201 from the left via the fuse 219.
[0043]
The third output buffer from the left of the output buffer block 111, the third output buffer from the left of the output buffer block 211, the third output buffer from the left of the output buffer block 311 and the third output from the left of the output buffer block 411 The buffer is connected to the third pad 201 from the left via a fuse 219.
[0044]
The fourth output buffer from the left of the output buffer block 111, the fourth output buffer from the left of the output buffer block 211, the fourth output buffer from the left of the output buffer block 311 and the fourth output from the left of the output buffer block 411 The buffer is connected to the fourth pad 201 from the left through the fuse 219.
[0045]
The third storage device 300 is formed in a region surrounded by the dicing lines 3, 5, 21, and 17. The third storage device 300 is different from the first storage device 100 in the following points. The third storage device 300 does not have pads corresponding to the two pads 103 of the first storage device 100. In other respects, the third storage device 300 is the same as the first storage device 100.
[0046]
The fourth storage device 400 is formed in a region surrounded by the dicing lines 21, 7, 9, and 19. The fourth storage device 400 is the same as the second storage device 200.
[0047]
Arrows A 1, A 2, A 3, and A 4 indicate that the plurality of output buffers included in the output buffer blocks 111, 211, 311, and 411 are connected to the plurality of fuses 219 or the plurality of fuses 419. In the above-described example, the plurality of output buffers are connected to the plurality of fuses 219, but the plurality of output buffers may be connected to the plurality of fuses 419.
[0048]
Next, how to use and operate this semiconductor memory device will be described.
In the semiconductor memory device according to the present embodiment, the first memory device 100, the second memory device 200, the third memory device 300, and the fourth memory device 400 can be divided and commercialized separately. The first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 may be commercialized without being divided.
[0049]
Here, when the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 are divided and commercialized separately, the first storage device 100, the first storage device 100, Each of the second storage device 200, the third storage device 300, and the fourth storage device 400 is referred to as a “divided chip”.
[0050]
The semiconductor memory device in the case where the first memory device 100, the second memory device 200, the third memory device 300, and the fourth memory device 400 are commercialized without being divided is an original chip (with dicing lines 1 to 15). It will be called the enclosed part). In the case of the original chip, the part corresponding to the first storage device (the part surrounded by the dicing lines 1, 17, 23, and 15) may be referred to as the unit chip 100. Similarly, portions corresponding to each of the second storage device 200, the third storage device 300, and the fourth storage device 400 may be referred to as a unit chip 200, a unit chip 300, and a unit chip 400.
[0051]
A case where the first memory device 100, the second memory device 200, the third memory device 300, and the fourth memory device 400 included in the semiconductor memory device according to the first embodiment are divided chips will be described. That is, a case where assembly (assembly work) is performed using the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 as separate storage devices will be described.
[0052]
The basic chip is cut along dicing lines 1 to 23. Thus, in the basic chip, the decoders 107, 207, 307, and 407, the sense amplifier blocks 109, 209, 309, and 409 and the pads 113, 213, 313, and 413, which are located in the middle of the basic chip, are divided. The chip is located at the end of the divided chip.
[0053]
The plurality of fuses 219 and the plurality of fuses 419 are cut. That is, the output buffer blocks 111, 211, 311, 411 are not connected to the plurality of pads 201, 401. On the other hand, the output buffer blocks 1111, 211, 311 and 411 are still connected to the pads 113, 213, 313 and 413 via the fuses 115, 215, 315 and 415. The address buffer blocks 205 and 405 and the plurality of pads 201 and 401 are also connected via the plurality of fuses 217 and 417. The two pads 103 are not used in the case of a divided chip.
[0054]
The operation of the divided chip corresponding to the first storage device 100 will be described.
The plurality of address buffers included in the address buffer block 105 receive an address signal from the outside via the plurality of pads 101. Memory cell matrix M1 includes a plurality of memory cells that store information. The decoder 107 receives an address signal from the address buffer block 105. Based on the address signal, a memory cell included in the memory cell matrix M1 is selected.
[0055]
The sense amplifier block 109 amplifies a minute signal from the selected memory cell. The output buffer block 111 receives the signal amplified by the sense amplifier block 109 and outputs the signal to the outside through the plurality of pads 113. The operation of the divided chip corresponding to each of the second storage device 200, the third storage device 300, and the fourth storage device 400 is the same as the operation of the divided chip corresponding to the first storage device 100.
[0056]
As described above, the divided chip (the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400) has a divided chip as a storage device (memory). Includes all the circuitry necessary to function.
[0057]
The case where the basic chip of FIG. 1 is used as the original chip will be described. That is, a case where assembly is performed using the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 as one storage device (memory) will be described.
[0058]
Cut along dicing lines 1-15. The plurality of fuses 115, the plurality of fuses 215, the plurality of fuses 315, and the plurality of fuses 415 are cut. Accordingly, in the case of the original chip, the plurality of pads 113, 213, 313, and 413 are not used. On the other hand, the output buffer blocks 1111, 211, 311 and 411 remain connected to the pads 201 and 401 via the fuses 219 and 419, respectively.
[0059]
As described above, the pads 113, 213, 313, and 413 that are not used in the original chip but are used only in the divided chip are arranged at the center of the basic chip. On the other hand, the pads 101, 201, 301, 401 used in both the original chip and the divided chip are arranged at the end of the basic chip.
[0060]
The plurality of fuses 217 and the plurality of fuses 417 are cut. That is, in the case of the original chip, the address buffer blocks 205 and 405 are not used. The plurality of pads 101 and the address buffer block 105 are shared by the four unit chips 100, 200, 300, and 400.
[0061]
Instead of sharing the plurality of pads 101 and the address buffer block 105, the plurality of pads 301 and the address buffer block 305 may be shared. In this case, the pad 103 and the buffer connected thereto may be used as the pad and the buffer for the selection signal, or 2 corresponding to the two pads 103 and the two buffers connected to the unit chip 300 may be used. One pad and a buffer connected thereto may be provided.
[0062]
The operation when the basic chip of FIG. 1 is the original chip will be described.
Address signals for selecting a memory cell in each of the memory cell matrices M1 to M4 are input to the plurality of pads 101. To the two pads 103, a selection signal for selecting which memory cell matrix of the memory cell matrices M1 to M4 the address signal input to the plurality of pads 101 is input. For example, when the memory cell matrix M1 is selected by the selection signal, the address signal input to the address buffer block 105 is input to the decoder 107.
[0063]
Signals from the output buffer blocks 111, 211, 311, 411 are output to the outside via a plurality of pads 201, 401. In this case, one output buffer in the output buffer block 111, one output buffer in the output buffer block 211, one output buffer in the output buffer block 311 and one output buffer in the output buffer block 411 Are connected to one pad 201 via one fuse 219.
[0064]
For this reason, it is necessary to select which memory cell matrix of the four is to be output from one pad 201. The circuit responsible for this selection is a selection circuit. Although not shown, this selection circuit is disposed inside the original chip. The selection circuit generates signals BS1, BS2, BS3, BS4. For example, the signal BS1 is a signal for activating or deactivating the decoder 107 and the output buffer block 111.
[0065]
A plurality of signals from the output buffer block activated by such signals BS1 to BS4 are output to the outside through the plurality of pads 201 and 401. Note that the output buffer included in each of the output buffer blocks 111, 211, 311, 411 may be connected to either the fuse 219 or the fuse 419. The selection circuit will be described in detail later.
[0066]
The characteristic operation of the original chip has been described above. The decoders 107, 207, 307, and 407, the sense amplifier blocks 109, 209, 309, and 409, and the output buffer blocks 111, 211, 311, and 411 are divided chips. The operation is the same as in the case of.
[0067]
FIG. 2 is a diagram for explaining the semiconductor memory device of FIG. 1 in detail. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
[0068]
In the description of FIG. 1, the number of data input / output line pairs provided in each of the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 is defined. In FIG. 2, the number of data input / output line pairs provided in each of the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 in FIG. There are four.
[0069]
For this reason, the memory cell matrix M1 is divided into four memory cell blocks IO1, IO2, IO3, and IO4. Correspondingly, the sense amplifier block 109 is provided with four sense amplifiers 116, the output buffer block 111 is provided with four output buffers 118, four fuses 115 are provided, and four pads 113 are provided. It is done.
[0070]
Although not shown in FIG. 1, the first storage device 100 includes a column selection circuit block 123 and a data input / output line unit 121 as shown in FIG. The column selection block 123 includes four column selection circuits 126. The column selection circuit block 123 receives the column selection signal S from the decoder 107 and selects a column of the memory cell matrix M1. A signal from the column (bit line pair) selected by the column selection signal S is input to the sense amplifier block 109 via the data input / output line unit 121. The operation of the column selection circuit block 123 is the same in the case of the divided chip and the original chip.
[0071]
The configurations and operations of the second storage device 200, the third storage device 300, and the fourth storage device 400 are the same as the configuration and operation of the first storage device 100.
[0072]
The leftmost output buffer 118 of the output buffer block 111, the leftmost output buffer 218 of the output buffer block 211, the leftmost output buffer 318 of the output buffer block 311 and the leftmost output buffer of the output buffer block 411 418 is connected to the leftmost fuse 219.
[0073]
The second output buffers 118, 218, 318, 418 from the left of the output buffer blocks 111, 211, 311, 411 are connected to the second fuse 219 from the left. The third output buffers 118, 218, 318, 418 from the left of the output buffer blocks 111, 211, 311, 411 are connected to the third fuse 219 from the left.
[0074]
The fourth output buffers 118, 218, 318, 418 from the left of the output buffer blocks 111, 211, 311, 411 are connected to the fourth fuse 219 from the left. Note that the output buffers 118, 218, 318, and 418 may be connected to the fuse 419 instead of the fuse 219.
[0075]
When the basic chip of FIG. 2 is a divided chip, each divided chip has four data input / output line pairs, and four signals from the memory cell blocks IO1 to IO4 are also output from the four pads 113 to the outside. Will be. That is, the divided chip has a memory capacity of 1M and a 4-bit configuration. That is, the divided chip is a 256 k × 4 bit storage device (memory).
[0076]
On the other hand, in the case of the original chip, four signals output from the memory cell blocks IO1 to IO4 of the unit chip selected by a selection circuit (not shown) are output from the four pads 201. That is, the original chip has a memory capacity of 4M and becomes a 4-bit memory. That is, it is a 1M × 4 bit memory.
[0077]
As described above, the semiconductor memory device of FIG. 2 has a 4-bit configuration in both the original chip and the divided chip. However, the memory capacity of the divided chip is a quarter of the memory capacity of the original chip.
[0078]
FIG. 3 is a circuit diagram showing details of a part of the semiconductor memory device of FIG. The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.
[0079]
FIG. 3 shows a part of the semiconductor memory device of FIG. 2, that is, a memory cell block IO1, a column selection circuit 126, a data input / output line unit 121, a sense amplifier 116, and an output buffer 118. Referring to FIG. 3, memory cell block IO1 includes a plurality of bit line pairs B and / B. A plurality of memory cells 124 are connected to the bit line pair B, / B. A plurality of word lines 125 are connected to the plurality of memory cells 124. A signal is read from bit line pair B and / B from memory cell 124 connected to activated word line 125.
[0080]
The column selection circuit 126 includes a plurality of switching gates composed of NMOS transistors 129 and NMOS transistors 131. One source / drain electrode of NMOS transistor 129 is connected to bit line B, and the other source / drain electrode is connected to data input / output line IO1. One source / drain electrode of NMOS transistor 131 is connected to bit line / B, and the other source / drain electrode is connected to data input / output line / IO1.
[0081]
The gate electrode of the NMOS transistor 129 and the gate electrode of the NMOS transistor 131 are connected to the column selection line 127. Column selection signals S <b> 1 to Sn are input to the plurality of column selection lines 127. The NMOS transistors 129 and 131 to which the “H” level column selection signal is input are turned on. Therefore, the bit line pair B and / B and the data input / output lines IO1 and / IO1 are connected through the NMOS transistors 129 and 131 that are turned on.
[0082]
For this reason, the signal from the memory cell 124 read to the bit line pair B and / B is input to the sense amplifier 116. Then, the signal from the bit line pair B, / B input to the sense amplifier 116 is amplified and input to the output buffer 118.
[0083]
FIG. 3 shows the column selection circuit 126, the data input / output line unit 121, the sense amplifier 116, and the output buffer 111 corresponding to the memory cell block IO1 of FIG. 2, but corresponds to the memory cell blocks IO2 to IO4. The column selection circuit 126, the data input / output line unit 121, the sense amplifier 116, and the output buffer 111 are the same as those in FIG.
[0084]
FIG. 4 is a schematic block diagram showing a part of a selection circuit used when the semiconductor memory device of FIG. 2 is an original chip. As described above, the column selection circuit, in the case of the original chip, activates / deactivates the decoders 107, 207, 307, 407 and the output buffer blocks 111, 211, 311, 411 included in the unit chips 100, 200, 300, 400. It is a circuit for controlling inactivity. A signal from the unit chip activated by the column selection circuit is output from the pad 201 to the outside.
[0085]
Referring to FIG. 4, the selection circuit includes fuses 27 and 33 and buffers 29 and 35. The pad 25 and the buffer 29 are connected via a fuse 27. The pad 31 and the buffer 35 are connected via a fuse 33. When the basic chip is a divided chip, the fuses 27 and 33 are cut. That is, in the case of a divided chip, the selection circuit is not used.
[0086]
A case where the basic chip is the original chip will be described.
The buffer 29 and the pad 25 and the buffer 35 and the pad 31 are still connected. A signal Z 0 is input to the pad 25. Buffer 29 receives signal Z0 and outputs signal Z0 and signal / Z0. Signal / Z0 indicates that it is an inverted signal of signal Z0. For example, when “L” level signal Z 0 is input, “H” level signal / Z 0 and “L” level signal Z 0 are output from buffer 29.
[0087]
A signal Z1 is input to the pad 31. Buffer 35 receives signal Z1 and outputs signal Z1 and signal / Z1. Signal / Z1 indicates that it is an inverted signal of signal Z1.
[0088]
FIG. 5 is a circuit diagram showing in detail another part of the selection circuit of FIG. Note that portions similar to those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0089]
Referring to FIG. 5, another part of the selection circuit includes NAND circuits 37, 41, 45, 49 and inverters 39, 43, 47, 51. NAND circuit 37 receives signals / Z0 and / Z1. In response to signal / Z0 and signal / Z1, inverter 39 outputs signal BS1. The signal BS1 is input to the decoder 107 and the output buffer block 111 in FIG.
[0090]
NAND circuit 41 receives signals Z0 and / Z1. Signal BS2 is output from inverter 43 in response to signal Z0 and signal / Z1. The signal BS2 is input to the decoder 207 and the output buffer block 211 in FIG.
[0091]
NAND circuit 45 receives signal / Z0 and signal Z1. Signal BS3 is output from inverter 47 in response to signal / Z0 and signal Z1. The signal BS3 is input to the decoder 307 and the output buffer block 311 in FIG.
[0092]
The NAND circuit 49 receives the signal Z0 and the signal Z1. In response to signal Z0 and signal Z1, inverter 51 outputs signal BS4. The signal BS4 is input to the decoder 407 and the output buffer block 411 in FIG.
[0093]
For example, a case where the decoder 107 and the output buffer block 111 are activated, that is, a case where the unit chip 100 is selected will be described.
[0094]
In this case, an “L” level signal Z 0 is input to the pad 25 in FIG. 4, and an “L” level signal Z 1 is input to the pad 31. Signal Z0 output from buffer 29 is at "L" level, and signal / Z0 is at "H" level. Signal Z1 output from buffer 35 is at "L" level, and signal / Z1 is at "H" level. The NAND circuit 37 of FIG. 5 receives the “H” level signal / Z0 and the signal / Z1. Therefore, the signal BS1 is at the “H” level.
[0095]
Therefore, NAND circuit 41 in FIG. 5 receives “Z” level signal Z0 and “H” level signal / Z1. Therefore, the signal BS2 becomes “L” level. NAND circuit 45 receives “H” level signal / Z0 and “L” level signal Z1. Therefore, the signal BS3 becomes “L” level. The NAND circuit 49 receives the “Z” level signal Z0 and the signal Z1. For this reason, the signal BS4 becomes the “L” level.
[0096]
As described above, only the signal BS1 becomes “H” level. Decoder 107 and output buffer block 111 are activated by this “H” level signal BS1. Then, signals corresponding to the four output buffers 118 are output from the four pads 201.
[0097]
Here, the decoders 207, 307, and 407 and the output buffer blocks 211, 311, and 411 to which the “L” level signals BS2, BS3, and BS4 are input are inactive. The same operation is performed when the unit chip 200, the unit chip 300, and the unit chip 400 are selected.
[0098]
As described above, in the semiconductor memory device according to the first embodiment, the original chip can be commercialized or the divided chip can be commercialized. That is, the memory capacity of the product can be made variable during assembly. Therefore, a plurality of types of products can be manufactured from one wafer, and the design and wafer process for each product type are not required. Therefore, the design period and the trial production period can be shortened and the development cost can be reduced.
[0099]
In addition, when there is a memory cell that cannot be relieved by the redundancy function (redundancy) in any of the memory cell matrices M1 to M4, the memory cell matrix in which the memory cell that cannot be relieved cannot be used. Cannot be commercialized. However, among the memory cell matrices M1 to M4, a memory cell matrix that can be relieved by a redundancy function (redundancy) or a normal memory cell matrix can be commercialized as a divided chip. For this reason, it is not necessary to discard the entire original chip, and it is only necessary to discard the divided chip including the memory cell matrix including the memory cells that cannot be relieved, so that the manufacturing cost can be reduced.
[0100]
In the semiconductor memory device according to the first embodiment, the plurality of pads 101, 103, 113 of the first memory device 100 are all arranged in the same direction. For this reason, an area can be made small compared with the case where the pads are arranged in different directions. The pads are arranged in different directions when, for example, the pads 101 are arranged along the dicing line 15 and the dicing line 1. The same can be said for the second storage device 200, the third storage device 300, and the fourth storage device 400. Therefore, the chip area can be reduced both when the semiconductor memory device according to the first embodiment is used as an original chip and as a divided chip.
[0101]
In the semiconductor memory device according to the first embodiment, the plurality of pads 101 and 103 and the address buffer block 105 of the first memory device are close to each other, and the plurality of pads 113 and the output buffer block 111 are close to each other. ing. For this reason, compared with the case where the pad is not close to the address buffer or the output buffer, the distance between the pad and the address buffer or the output buffer can be shortened, so that the signal delay can be reduced.
[0102]
The case where the pads are separated from the address buffer or the output buffer is, for example, a case where a plurality of pads 101 for the address buffer block 105 are arranged along the dicing line 15. At this time, the upper pad 101 of the semiconductor memory device is close to the address buffer block 105, but the lower pad 101 of the semiconductor memory device is separated from the address buffer block 105. Therefore, an address signal input from a pad remote from the address buffer block 105 is delayed with respect to an address signal input from a pad adjacent to the address buffer block 105.
[0103]
1 and 2, the output buffer blocks 1111, 211, 311 and 411 are described. However, the same applies to an input buffer block including an input buffer to which a signal is input. In addition, the above-described effects are exhibited.
[0104]
1 and 2, each of the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 has a plurality of data input / output operations. Although the case where the line pair is provided has been described, each of the first storage device 100, the second storage device 200, the third storage device 300, and the fourth storage device 400 has one data input / output line pair. You may have. In this case, the same effect as described above can be obtained.
[0105]
FIG. 6 is a schematic block diagram showing a modification of the semiconductor memory device according to the first embodiment. The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Therefore, the characteristic part will be mainly described.
[0106]
In the semiconductor memory device of FIG. 2, each of the first memory device 100, the second memory device 200, the third memory device 300, and the fourth memory device 400 includes four data input / output line pairs. In contrast, in the semiconductor memory device of FIG. 6, each of the first memory device 100, the second memory device 200, the third memory device 300, and the fourth memory device 400 has one data input / output line. Has a pair.
[0107]
Therefore, referring to FIG. 6, in the first storage device 100, the column selection circuit block 123 includes one column selection circuit 126, the sense amplifier block 109 includes one sense amplifier 116, and an output buffer block 111 includes one output buffer 118, one fuse 115, and one pad 113. The memory cell matrix M1 is not divided into memory cell blocks. The configurations of the second storage device 200, the third storage device 300, and the fourth storage device 400 are the same as the configuration of the first storage device 100.
[0108]
The output buffer 118 is connected to the node B1. The output buffer 218 is connected to the node B2. As described above, the output buffers 118 and 218 are connected to the pad 201 via the fuse 219. The output buffer 318 is connected to the node B3. The output buffer 418 is connected to the node B4. As described above, the output buffers 318 and 418 are connected to the pad 401 through the fuse 419.
[0109]
Note that the fuses connecting the output buffers 118, 218, 318, and 418 may be any of the plurality of fuses 219 and the plurality of fuses 419. However, the four output buffers 118, 218, 318, 418 need to be connected to different fuses.
[0110]
The operation in the case of using the basic chip as the divided chip is the same as that in the case of dividing the basic chip in FIG. However, in the semiconductor memory device of FIG. 6, the memory capacity of the divided chip is 1M, which is a 1-bit configuration. That is, the divided chip is a 1M × 1 bit memory.
[0111]
A case where the basic chip is the original chip will be described.
The operation when the basic chip of FIG. 6 is used as the original chip is the same as the operation when the basic chip of FIG. 2 is used as the original chip. However, the selection circuit provided in the semiconductor memory device in FIG. 2 is not provided in the semiconductor memory device in FIG. This is because the four output buffers 118, 218, 318, 418 are connected to different fuses 219, 419. That is, the memory capacity of the original chip is 4M, which is a 4-bit configuration. That is, the original chip is a 1M × 4 bit memory.
[0112]
As described above, the modification of the semiconductor memory device according to the first embodiment has a 1-bit configuration in the case of a divided chip and a 4-bit configuration in the case of an original chip. The original chip is also different from the semiconductor memory device (FIG. 2) according to the first embodiment having a 4-bit configuration.
[0113]
As described above, in the modified example of the semiconductor memory device according to the first embodiment, the basic chip can be an original chip or a divided chip. Furthermore, in the modification of the semiconductor memory device according to the first embodiment, the arrangement of the pads, address buffer blocks, and output buffer blocks is the same as the arrangement of the pads, address buffer blocks, and output buffer blocks of the semiconductor memory device according to the first embodiment. It is the same. Therefore, the modification of the semiconductor memory device according to the first embodiment also has the same effect as the semiconductor memory device according to the first embodiment.
[0114]
FIG. 7 is a schematic block diagram showing another modification of the semiconductor memory device according to the first embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
[0115]
The semiconductor memory device of FIG. 7 uses the first memory device 100 and the second memory device 200 of the semiconductor memory device of FIG. 1 as basic chips. Therefore, in the case of the original chip, the memory capacity is 2M. In the case of a divided chip, the memory capacity is 1M.
[0116]
A case where the basic chip is a divided chip will be described.
In this case, cutting is performed along dicing lines 1, 17, 19, 11, 13, 15, and 23. Other operations are the same as those in FIG.
[0117]
A case where the basic chip is the original chip will be described.
In this case, cutting is performed along dicing lines 1, 17, 19, 11, 13, 15. Other operations are the same as those in FIG. Since there are two unit chips 100 and 200, only one pad 103 for inputting a selection signal and one buffer connected thereto are required. The selection circuit is the same as the selection circuit in FIGS.
[0118]
As described above, also in another modification example of the semiconductor memory device according to the first embodiment, the basic chip can be the original chip or the divided chip. Furthermore, the arrangement of pads, address buffer blocks, and output buffer blocks in another modification of the semiconductor memory device according to the first embodiment is the same as the arrangement of pads, address buffer blocks, and output buffer blocks of the semiconductor memory device according to the first embodiment. It is the same. Therefore, the other modification of the semiconductor memory device according to the first embodiment also has the same effect as the semiconductor memory device according to the first embodiment.
[0119]
(Embodiment 2)
FIG. 8 is a schematic block diagram showing a semiconductor memory device according to the second embodiment of the present invention. Note that the semiconductor memory device of FIG. 8 is formed on a wafer, and is before the wafer is cut along a dicing line. In other words, the semiconductor memory device of FIG. 8 is the one before assembly. The semiconductor memory device before assembly as shown in FIG. 8 may be referred to as a “basic chip”.
[0120]
The semiconductor memory device according to the second embodiment includes a first memory device 525 and a second memory device 527. The first storage device 525 is formed in an area surrounded by the dicing lines 501, 513, 509, and 511. The second storage device 527 is formed in a region surrounded by dicing lines 503, 505, 507, and 513.
[0121]
The first storage device 525 includes an output buffer 515 and pads 517 and 523. Note that the first storage device 525 includes all the circuits necessary for the first storage device 525 alone to function as a memory. For example, a pad, an address buffer, a decoder, a memory cell matrix, a sense amplifier, and an output buffer.
[0122]
The second storage device 527 includes an output buffer 519 and a pad 521. Although not illustrated, the second storage device 527 includes all circuits necessary for the second storage device 527 alone to function as a memory.
[0123]
The output buffer 515 is connected to the pad 517. The output buffer 519 is connected to the pad 521. Pad 517 and pad 521 are connected to pad 523.
[0124]
A method of using the semiconductor memory device according to the second embodiment will be described.
In the semiconductor memory device according to this embodiment, the first memory device 525 and the second memory device 527 can be divided and manufactured separately, or the first memory device 525 and the second memory device 527 can be separately manufactured. It is also possible to commercialize the product without dividing it. Here, each of the first storage device 525 and the second storage device 527 when the first storage device 525 and the second storage device 527 are divided and commercialized separately is referred to as a “divided chip”. I will decide.
[0125]
The semiconductor memory device in FIG. 8 in the case where the first memory device 525 and the second memory device 527 are commercialized without being divided is referred to as an original chip. In the case of the original chip, the first storage device 525 may be referred to as a unit chip 525 and the second storage device 527 may be referred to as a unit chip 527.
[0126]
A case where the first memory device 525 and the second memory device 527 of the semiconductor memory device in FIG. 8 are divided chips will be described. That is, a case where assembly (assembly work) is performed using the first storage device 525 and the second storage device 527 as separate storage devices will be described.
[0127]
The base chip is cut along dicing lines 501, 503, 505, 507, 509, 511, and 513. In the divided chip corresponding to the first storage device 525, the signal from the output buffer 515 is output from the pad 517 to the outside. The output buffer 515 is the same as the output buffer 118 in FIG. In the divided chip corresponding to the second storage device 527, the signal from the output buffer 519 is output from the pad 521 to the outside.
[0128]
A case where the semiconductor memory device according to the second embodiment is used as the original chip will be described. That is, a case where assembly is performed using the first storage device 525 and the second storage device 527 as one storage device will be described.
[0129]
The base chip is cut along dicing lines 501, 503, 505, 507, 509, and 511. In this case, the pad 523 is used, and the signal from the output buffer 515 or the output buffer 519 is output from the pad 523 to the outside. Further, although not shown, the original chip includes a selection circuit similar to the selection circuit shown in FIGS. Therefore, signal BS1 and signal BS2 are the same as signal BS1 and signal BS2 of FIG.
[0130]
As described above, the semiconductor memory device according to the second embodiment can be commercialized as a divided chip or can be commercialized as an original chip. Therefore, the same effect as the semiconductor memory device according to the first embodiment can be obtained.
[0131]
Although not shown in FIG. 8, the plurality of pads are all arranged in the same direction as in FIG. Further, although not shown in FIG. 8, a plurality of address buffers and a plurality of pads connected to the plurality of address buffers are arranged close to each other. Therefore, the semiconductor memory device according to the second embodiment has the same effects as the semiconductor memory device according to the first embodiment.
[0132]
When there are a plurality of output buffers 515 and 519, a plurality of pads 517, 521, and 523 are provided correspondingly. Then, pads to which signals of the same system are input are connected. By doing so, the same effects as described above can be obtained.
[0133]
FIG. 9 is a schematic block diagram showing a modification of the semiconductor memory device according to the second embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. In FIG. 1, each of the output buffer blocks 111, 211, 311, 411 includes a plurality of output buffers. However, in FIG. 9, the output buffer blocks 111, 211, 311, 411 include one output buffer block. An example including an output buffer is shown. Here, the meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as those described in the first embodiment.
[0134]
A case where the semiconductor memory device (basic chip) of FIG. 9 is a divided chip will be described.
[0135]
Cut along dicing lines 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23. A divided chip corresponding to the first storage device 100 will be described. A plurality of address signals are input to the plurality of address pads 101 from the outside. The address buffer block 105 receives a plurality of address signals and inputs them to the decoder 107. A signal from the output buffer block 111 is output to the outside through the pad 113. The operation of the divided chip is the same as the operation of the divided chip in FIG. Note that the divided chips corresponding to the second storage device 200, the third storage device 300, and the fourth storage device 400 are the same as the divided chips corresponding to the first storage device 100.
[0136]
A case where the semiconductor memory device (basic chip) of FIG. 9 is used as the original chip will be described.
[0137]
Cut along dicing lines 1, 3, 5, 7, 9, 11, 13, 15. Signals from the output buffer blocks 111, 211, 311, 411 are output from the pad 523 to the outside. Although not shown, the original chip includes a selection circuit similar to the selection circuit shown in FIGS. Therefore, for example, when decoder 107 and output buffer 111 are activated by the selection circuit, a signal from output buffer 111 is output from pad 523 to the outside.
[0138]
Although the characteristic part in the case of the original chip has been described above, a plurality of pads 101, 201, 301, 401, address buffer blocks 100, 200, 300, 400, decoders 107, 207, 307, 407 and output buffers Blocks 111, 211, 311, and 411 are the same as in the case of the divided chip.
[0139]
Thus, in the modification of the semiconductor memory device according to the second embodiment, it can be a divided chip or an original chip. Further, the arrangement of a plurality of pads, address buffer blocks, and output buffer blocks is the same as that shown in FIG. Therefore, the modification of the semiconductor memory device according to the second embodiment has the same effect as the semiconductor memory device according to the first embodiment.
[0140]
(Embodiment 3)
FIG. 10 is a schematic block diagram showing a semiconductor memory device according to the third embodiment. Note that portions similar to those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted as appropriate. The meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as those described in the second embodiment.
[0141]
The characteristic part will be described. Referring to FIG. 10, the first storage device 525 includes an output buffer 515, a pad 517, a fuse 529 and a pad 523. The second storage device 527 includes an output buffer 519, a pad 521, and a fuse 531.
[0142]
The output buffers 515 and 519 are connected to the pad 523. The pad 517 is connected to the pad 523 through the fuse 529. The pad 521 is connected to the pad 523 through the fuse 531.
[0143]
A case where the semiconductor memory device (base chip) in FIG. 10 is a divided chip will be described.
[0144]
The cutting of the dicing line is the same as in the semiconductor memory device of FIG. In a divided chip corresponding to the first storage device 525, a pad 517 is used, and a signal from the output buffer 515 is output from the pad 517 to the outside. The same applies to the divided chips corresponding to the second storage device 527.
[0145]
A case where the semiconductor memory device (basic chip) of FIG. 10 is used as the original chip will be described.
[0146]
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. The fuses 529 and 531 are cut. Therefore, in the case of the original chip, the pad 523 is used, and signals from the output buffers 515 and 519 are output to the outside through the pad 523. Although not shown, the same selection circuit as in FIGS. 4 and 5 is used when the original chip is used.
[0147]
Thus, the semiconductor memory device according to the third embodiment can be a divided chip or an original chip. Further, the configuration is the same as that of the semiconductor memory device of FIG. Therefore, the semiconductor memory device according to the third embodiment has the same effect as the semiconductor memory device according to the second embodiment.
[0148]
When there are a plurality of output buffers 515 and output buffers 519, a plurality of pads 517, 521, 523 and fuses 529, 531 are provided correspondingly. The connection is the same as when one output buffer 515 and one output buffer 519 are provided.
[0149]
FIG. 11 is a schematic block diagram showing a modification of the semiconductor memory device according to the third embodiment. The same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Therefore, the characteristic part will be mainly described. Here, the meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as those described in the first embodiment.
[0150]
A case where the semiconductor memory device (base chip) of FIG. 11 is a divided chip will be described.
[0151]
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. 9 is divided into chips. In the divided chip corresponding to the first storage device 100, the pad 113 is used, and a signal from the output buffer block 111 is output to the outside through the pad 113. Note that the divided chips corresponding to the second storage device 200, the third storage device 300, and the fourth storage device 400 are the same as the divided chips corresponding to the first storage device 100.
[0152]
A case where the semiconductor memory device (basic chip) of FIG. 11 is used as the original chip will be described.
[0153]
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. 9 is used as the original chip. The fuses 115, 215, 315, and 415 are cut. Signals from the output buffer blocks 111, 211, 311, and 411 are output to the outside via the pad 523. Although not shown, the original chip includes a selection circuit similar to the selection circuit shown in FIGS.
[0154]
As described above, the modification of the semiconductor memory device according to the third embodiment can be an original chip or a divided chip. Further, the configuration is the same as that of the semiconductor memory device of FIG. For this reason, the modification of the semiconductor memory device according to the third embodiment has the same effect as the modification of the semiconductor memory device according to the second embodiment.
[0155]
(Embodiment 4)
FIG. 12 is a schematic block diagram showing a semiconductor memory device according to the fourth embodiment. The same parts as those in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Here, the meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as those described in the second embodiment.
[0156]
Referring to FIG. 12, a first storage device 525, an output buffer 515, and a pad 517 are included. The second storage device 527 includes an output buffer 519 and a pad 521. Note that, although the lead frame 533 and the wire 535 are shown, they are used for later explanation and are not provided in the semiconductor memory device according to the fourth embodiment.
[0157]
The output buffer 515 is connected to the pad 517. The output buffer 519 is connected to the pad 521. Pad 517 is connected to pad 521.
[0158]
A case where the semiconductor memory device (base chip) of FIG. 12 is a divided chip will be described.
[0159]
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. 8 is divided into chips. In a divided chip corresponding to the first storage device 525, a pad 517 is used, and a signal from the output buffer 515 is output from the pad 517. The divided chip corresponding to the second storage device 527 is the same as the divided chip corresponding to the first storage device 525.
[0160]
A case where the semiconductor memory device of FIG. 12 is used as the original chip will be described.
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. Signals from the output buffer 515 and the output buffer 519 are output to the outside via either the pad 517 or the pad 521. For example, when the lead frame 533 is not in the pad 517 but in the vicinity of the pad 521, the pad 521 and the lead frame 533 can be connected by the wire 535. On the other hand, when the lead frame is in the vicinity of the pad 517 and away from the pad 521, the lead frame 533 and the pad 517 can be connected by a wire. Thus, in the case of the original chip, either the pad 517 or the pad 521 can be used in accordance with the position of the lead frame.
[0161]
As described above, the semiconductor memory device according to the fourth embodiment can be a divided chip or an original chip. Further, the configuration is the same as that of the semiconductor memory device of FIG. Therefore, the semiconductor memory device according to the fourth embodiment has the same effects as the semiconductor memory device according to the second embodiment.
[0162]
In the semiconductor memory device according to the fourth embodiment, when the original chip is used, either pad 517 or pad 521 is used as a pad for outputting signals from output buffers 515 and 519 to the outside. it can. This increases the degree of freedom in using the lead frame connected to the pad. That is, a lead frame that is easy to wire can be used for the pad 517, and a lead frame that is easy to wire can be used for the pad 521.
[0163]
When there are a plurality of output buffers 515 and output buffers 519, a plurality of pads 517 and pads 521 are provided correspondingly. Then, pads to which signals of the same system are input are connected.
[0164]
FIG. 13 is a schematic block diagram showing a modification of the semiconductor memory device according to the fourth embodiment of the present invention. Note that portions similar to those in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted as appropriate. Therefore, the characteristic part will be mainly described. Here, the meanings of the basic chip, the original chip, the divided chip, and the unit chip are the same as those described in the first embodiment.
[0165]
Referring to FIG. 13, output buffer block 111 is connected to pad 113. The output buffer block 211 is connected to the pad 213. The output buffer block 311 is connected to the pad 313. The output buffer block 411 is connected to the pad 413. The pad 113, pad 213, pad 313, and pad 413 are connected.
[0166]
A case where the semiconductor memory device of FIG. 13 is a divided chip will be described.
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. 9 is divided into chips. The divided chip corresponding to the first storage device 100 uses the pad 113, and a signal from the output buffer block 111 is output to the outside through the pad 113. The same applies to the divided chips corresponding to the second storage device 200, the third storage device 300, and the fourth storage device 400.
[0167]
A case where the semiconductor memory device (basic chip) of FIG. 13 is used as the original chip will be described.
[0168]
Any of the pad 113, the pad 213, the pad 313, and the pad 413 can be used to output signals from the output buffer blocks 111, 211, 311, and 411 to the outside. Although not shown, the original chip includes a selection circuit similar to the selection circuit shown in FIGS.
[0169]
As described above, in the modification of the semiconductor memory device according to the fourth embodiment, it can be a divided chip or an original chip. Furthermore, the modification of the semiconductor memory device according to the fourth embodiment has the same configuration as the modification of the semiconductor memory device according to the second embodiment. For this reason, the modification of the semiconductor memory device according to the fourth embodiment has the same effect as the modification of the semiconductor memory device according to the second embodiment.
[0170]
In the modification of the semiconductor memory device according to the fourth embodiment, in the case of the original chip, the pad 113 and the pad 213 are used as pads for outputting signals from the output buffer blocks 111, 211, 311 and 411 to the outside. Either the pad 313 or the pad 413 can be used. For this reason, the modification of the semiconductor memory device according to the fourth embodiment has the same effect as the semiconductor memory device according to the fourth embodiment.
[0171]
(Embodiment 5)
FIG. 14 is a schematic block diagram showing a semiconductor memory device according to the fifth embodiment. Note that the semiconductor memory device of FIG. 14 is formed on a wafer, and is the one before the wafer is cut along a dicing line. In other words, the semiconductor memory device of FIG. 14 is the one before assembly. Such a semiconductor memory device shown in FIG. 14 may be referred to as a “basic chip”.
[0172]
Referring to FIG. 14, the semiconductor memory device according to the fifth embodiment includes a first memory device 585, a second memory device 587, a third memory device 589, and a fourth memory device 591. The first storage device 585 is formed in an area surrounded by dicing lines 537, 553, 559, and 551. The second storage device 587 is formed in an area surrounded by dicing lines 559, 555, 547, and 549. The third storage device 589 is formed in an area surrounded by dicing lines 539, 541, 557, and 553. The fourth storage device 591 is formed in an area surrounded by dicing lines 557, 543, 545, and 555.
[0173]
The first storage device 585 includes an output buffer 561, a pad 569, and a fuse 577. The output buffer 561 is the same as the output buffer included in the output buffer block 111 of FIG. Although not illustrated, the first storage device 585 includes all circuits necessary for the first storage device 585 alone to function as a memory. Although not shown, the arrangement of the address buffer block and a plurality of pads corresponding to the address buffer block is the same as in FIG. Note that the configurations of the second storage device 587, the third storage device 589, and the fourth storage device 591 are the same as those of the first storage device 585.
[0174]
The output nodes N of the four output buffers 561, 565, 563, and 567 are common. Pad 569 is connected to output node N via fuse 577. Pad 573 is connected to output node N via fuse 583. Pad 571 is connected to output node N via fuse 579. Pad 575 is connected to output node N through fuse 581.
[0175]
A method of using the semiconductor memory device of FIG. 14 will be described.
In the semiconductor memory device in FIG. 14, the first memory device 585, the second memory device 587, the third memory device 589, and the fourth memory device 591 can be divided and commercialized separately. The first storage device 585, the second storage device 587, the third storage device 589, and the fourth storage device 591 can be commercialized without being divided.
[0176]
Here, when the first storage device 585, the second storage device 587, the third storage device 589, and the fourth storage device 591 are divided and commercialized separately, the first storage device 585, Each of the second storage device 587, the third storage device 589, and the fourth storage device 591 is referred to as a “divided chip”.
[0177]
A semiconductor memory device in the case where the first memory device 585, the second memory device 587, the third memory device 589, and the fourth memory device 591 are commercialized without being divided is referred to as an original chip. In the case of the original chip, the first storage device 585 is called a unit chip 585, the second storage device 587 is called a unit chip 587, the third storage device 589 is called a unit chip 589, and the fourth chip The storage device 591 may be referred to as a unit chip 591.
[0178]
A case where the semiconductor memory device (basic chip) of FIG. 14 is a divided chip will be described. That is, a case where assembly is performed using the first storage device 585, the second storage device 587, the third storage device 589, and the fourth storage device 591 as separate storage devices will be described.
[0179]
The base chip is cut along dicing lines 537, 539, 541, 543, 545, 547, 549, 551, 553, 555, 557, 559. The divided chip corresponding to the first storage device 585 uses the pad 569, and a signal from the output buffer 561 is output from the pad 569 to the outside. The same applies to the divided chips corresponding to the second storage device 587, the third storage device 589, and the fourth storage device 591.
[0180]
A case where the semiconductor memory device (basic chip) of FIG. 14 is used as the original chip will be described.
[0181]
Cut along dicing lines 537, 539, 541, 543, 545, 547, 549, 551. In this case, any of the pads 569, 573, 571, and 575 can be used for outputting the signals from the output buffers 561, 565, 563, and 567 to the outside. For example, when signals from the output buffer blocks 561, 565, 563, 567 are output to the outside via the pad 573, the fuses 577, 579, 581 are cut.
[0182]
As described above, the semiconductor memory device according to the fifth embodiment can be a divided chip or an original chip. Further, although not shown, the arrangement of the address buffer block and the plurality of pads corresponding to the address buffer block is the same as that of the semiconductor memory device of FIG. Therefore, the semiconductor memory device according to the fifth embodiment has the same effect as the semiconductor memory device according to the first embodiment.
[0183]
If a plurality of output buffers 561, output buffers 565, output buffers 563, and output buffers 567 are provided, pads 569, 573, 571, and 575 and fuses 577, 583, 579, and 581 are correspondingly provided. A plurality are also provided. The connection is the same as when one output buffer 561, 565, 563, 567 is provided.
[0184]
FIG. 15 is a schematic block diagram showing a modification of the semiconductor memory device according to the fifth embodiment. The same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Therefore, the characteristic part will be described. Here, the meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as those described in the first embodiment.
[0185]
Referring to FIG. 15, output buffer block 111, output buffer block 211, output buffer block 311, and output buffer block 411 share output node N. Pad 113 is connected to output node N via fuse 115. Pad 213 is connected to output node N via fuse 215. Pad 313 is connected to output node N through fuse 315. Pad 413 is connected to output node N via fuse 415.
[0186]
A case where the semiconductor memory device (basic chip) of FIG. 15 is a divided chip will be described.
[0187]
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. 9 is divided into chips. In the divided chip corresponding to the first storage device 100, the pad 113 is used, and a signal from the output buffer block 111 is output to the outside through the pad 113. The same applies to the divided chips corresponding to the second storage device 200, the third storage device 300, and the fourth storage device 400.
[0188]
A case where the semiconductor memory device (basic chip) of FIG.
[0189]
The cutting of the dicing line is the same as when the semiconductor memory device of FIG. 9 is used as the original chip. Any of pads 113, 213, 313, and 413 can be used as a pad for outputting signals from the output buffers 111, 211, 311 and 411 to the outside. For example, when signals from the output buffer blocks 111, 211, 311 and 411 are output to the outside via the pad 213, the fuses 115, 315 and 415 are cut. The original chip includes a selection circuit similar to the selection circuit shown in FIGS.
[0190]
As described above, in the modification of the semiconductor memory device according to the fifth embodiment, it can be a divided chip or an original chip. Further, the modification of the semiconductor memory device according to the fifth embodiment has the same configuration as that of the semiconductor memory device of FIG. For this reason, the modification of the semiconductor memory device according to the fifth embodiment has the same effect as the modification of the semiconductor memory device according to the second embodiment.
[0191]
(Embodiment 6)
FIG. 16 is a schematic block diagram showing a semiconductor memory device according to the sixth embodiment.
[0192]
FIG. 16A is a plan view of the semiconductor memory device according to the sixth embodiment. FIG. 16B is a cross-sectional view of the semiconductor memory device shown in FIG.
[0193]
Note that the semiconductor memory device of FIG. 16 is formed on a wafer, and is the one before cutting the wafer along a dicing line. That is, the semiconductor memory device of FIG. 16 is the one before assembly. Such a semiconductor memory device of FIG. 16 may be called a “basic chip”.
[0194]
Referring to FIG. 16A, the semiconductor memory device according to the sixth embodiment includes a first memory device 603, a second memory device 605, and an original chip dedicated circuit 607. Although not shown, the first storage device 603 includes all circuits and pads necessary for functioning as a memory only by the first storage device 603. For example, the circuits necessary to function as a memory are the address buffer block, decoder, sense amplifier block, output buffer block, memory cell matrix, and the like shown in FIG. Note that the second storage device 605 has the same configuration as the first storage device 603.
[0195]
Referring to FIG. 16B, the first storage device 603, the second storage device 605, and the original chip dedicated circuit 607 are formed on the silicon substrate 611. A glass coat 609 is formed on the first storage device 603, the second storage device 605, and the original chip dedicated circuit 607.
[0196]
The meanings of the divided chip, the original chip, and the unit chip are the same as those described in the second embodiment.
[0197]
Referring to FIG. 16, original chip dedicated circuit 607 used only in the original chip is formed on a dicing line 595 that is cut to form a divided chip. That is, the original chip dedicated circuit 607 is formed in a region that can be broken when cutting along the dicing line 95 to form a divided chip.
[0198]
When the semiconductor memory device of FIG. 16 is divided into chips, it is cut along dicing lines 593, 595, 597, 599, and 601. Since cutting is performed along the dicing line 595, the original chip dedicated circuit 607 is also cut at the same time.
[0199]
When the semiconductor memory device (basic chip) of FIG. 16 is used as the original chip, cutting is performed along dicing lines 593, 597, 599, and 601.
[0200]
As described above, the semiconductor memory device according to the sixth embodiment can be a divided chip or an original chip. Further, although not shown, like the semiconductor memory device (base chip) of FIG. 1, the plurality of pads are arranged in the same direction, the address buffer block and the plurality of pads connected thereto are close to each other, and output The buffer block and a plurality of pads connected thereto are close to each other. Therefore, the semiconductor memory device according to the sixth embodiment has the same effect as the semiconductor memory device according to the first embodiment.
[0201]
Further, in the semiconductor memory device according to the sixth embodiment, when the basic chip is a divided chip, the original chip dedicated circuit 607 is not necessary, so that the original chip is formed on the dicing line 595 to be cut to form the divided chip. A chip dedicated circuit 607 is arranged. For this reason, the chip area of the divided chip can be reduced.
[0202]
The original chip dedicated circuit 607 is formed on the dicing line 595 that is cut to make a divided chip, but the original chip dedicated pad that is used only on the original chip is cut to make a divided chip. The same effect as described above can be obtained by disposing it on 595.
[0203]
FIG. 17 is a schematic block diagram showing a part of a modification of the semiconductor memory device according to the sixth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. Note that the semiconductor memory device of FIG. 17 is based on the semiconductor memory device of FIG. Therefore, the modification of the semiconductor memory device according to the sixth embodiment has the same effect as the semiconductor memory device according to the first embodiment. Mainly characteristic parts will be described.
[0204]
Referring to FIG. 17, pads 25 and 31 are provided on dicing line 23. A selection circuit 613 is provided on the dicing lines 23 and 21. Note that the selection circuit 613 is the same as the selection circuit shown in FIGS. The pads 25 and 31 are the same as the pads 25 and 31 shown in FIG.
[0205]
As described above, in the modification of the semiconductor memory device according to the sixth embodiment, the pads 25 and 31 and the selection circuit 613 used only in the original chip are divided chips in the modification of the semiconductor memory device according to the sixth embodiment. It is provided on the dicing lines 23 and 21 to be cut. Therefore, the modification of the semiconductor memory device according to the sixth embodiment has the same effect as the semiconductor memory device according to the sixth embodiment.
[0206]
7 to 15, a circuit or pad used only in the original chip, such as a selection circuit or a pad used in the selection circuit, can also be provided on a dicing line that is cut when the divided chip is used. In this case, the same effect as described above can be obtained.
[0207]
(Embodiment 7)
FIG. 18 is a schematic block diagram showing a semiconductor memory device according to the seventh embodiment. The meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as those described in the second embodiment.
[0208]
Referring to FIG. 18, the semiconductor memory device according to the seventh embodiment includes a first memory device 626, a second memory device 628, and a shared circuit 627. The first storage device 626 includes a memory cell matrix M1. This memory cell matrix M1 is the same as the memory cell matrix M1 of FIG. Second storage device 628 includes a memory cell matrix M2. This memory cell matrix M2 is the same as the memory cell matrix M2 of FIG.
[0209]
The shared circuit 627 is a circuit that can be used in common by the first storage device 626 and the second storage device 628. For example, a decoder for selecting a memory cell in the memory cell matrix.
[0210]
The first storage device 626 includes all of the circuits necessary for the first storage device 626 alone to function as a memory. However, a circuit overlapping with the shared circuit 627 is not provided. Note that the second storage device 628 is similar to the first storage device 628.
[0211]
When the semiconductor memory device of FIG. 18 is used as the original chip, it is cut along dicing lines 615, 617, 619, and 621. The shared circuit 627 is shared by the first storage device 626 and the second storage device 628.
[0212]
When there is a defective bit (defective memory cell) in the memory cell matrix M1, cutting is performed along dicing lines 623, 617, 619, and 621. Then, a divided chip including the shared circuit 627 and the second storage device 628 is commercialized.
[0213]
On the other hand, when there is a defective bit (defective memory cell) in the memory cell matrix M2, cutting is performed along dicing lines 625, 615, 621, and 617. Then, a divided chip including the first storage device 626 and the shared circuit 627 is commercialized.
[0214]
FIG. 19 is a circuit diagram showing a specific example of the shared circuit 627 of FIG. Note that portions similar to those in FIG. 18 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0215]
In FIG. 19, the shared circuit 627 in FIG. 18 is a decoder. Decoder 627 includes an inverter 629 and a NAND circuit 631. Inverter 629 and NAND circuit 631 are connected in series. An output node of inverter 629 is connected to a memory cell selection line (word line) for selecting a memory cell in memory cell matrix M1 and a memory cell selection line (word line) for selecting a memory cell in memory cell matrix M2. Is done.
[0216]
In the case of the original chip, the decoder 627 is shared by the memory cell matrix M1 and the memory cell matrix M2.
[0217]
When there is a defective memory cell that cannot be relieved in the memory cell matrix M1, it is cut along the dicing line 623, and a divided chip composed of the decoder 627 and the second memory device 628 is commercialized. When there is a defective memory cell that cannot be relieved in the memory cell matrix M2, it is cut along the dicing line 625. Then, a divided chip including the decoder 627 and the first storage device 626 is commercialized.
[0218]
As described above, the semiconductor memory device according to the seventh embodiment can be a divided chip or an original chip. Further, in the semiconductor memory device according to the seventh embodiment, although not shown, the address buffer block and a plurality of pads connected thereto are arranged close to each other as shown in FIG. The plurality of pads to be connected are arranged close to each other, and the plurality of pads connected to the address buffer block and the plurality of pads connected to the output buffer block are all arranged in the same direction. Therefore, the semiconductor memory device according to the seventh embodiment has the same effect as the semiconductor memory device according to the first embodiment.
[0219]
Further, in the case where the semiconductor memory device according to the seventh embodiment is used as an original chip, circuits that can be shared by the two unit chips 626 and 628 are shared. Therefore, when the semiconductor memory device according to the seventh embodiment is used as the original chip, the area of the original chip can be reduced.
[0220]
In the case of the original chip, a pad that can be shared by the two unit chips 626 and 628 can be provided between the unit chip 626 and the unit chip 628. In this case, the same effect as described above can be obtained.
[0221]
1, 2, 6, 9, 11, 13, and 15, the decoder 107 and the decoder 307 are replaced with a decoder 627 as illustrated in FIG. 19, and the decoder 207 and the decoder 407 are illustrated in FIG. 19. A decoder 627 as shown can also be used. In this case, the same effect as described above is obtained. In the first to sixth embodiments, a circuit and a pad that can be shared by the two unit chips in the case of the original chip can be provided between the two unit chips. The effect of.
[0222]
FIG. 20 is a schematic block diagram showing a modification of the semiconductor memory device according to the seventh embodiment of the present invention. Note that portions similar to those in FIG. 18 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0223]
Referring to FIG. 20, the modification by the semiconductor memory device of the seventh embodiment includes a first memory device 626, a second memory device 628, a shared circuit 627, a plurality of fuses 633 and a plurality of fuses 635. The memory cell matrix M1 and the shared circuit 627 are connected via a plurality of fuses 633. Memory cell matrix M2 and shared circuit 627 are connected via a plurality of fuses 635.
[0224]
When there is a defective bit (defective memory cell) in the memory cell matrix M1, the plurality of fuses 633 are cut. Then, a divided chip including the first memory device 626, the shared circuit 627, the plurality of fuses 635, and the second memory device 628 is commercialized. However, since the plurality of fuses 633 are cut, the first storage device 626 does not function.
[0225]
When a defective bit (defective memory cell) exists in the memory cell matrix M2, the plurality of fuses 635 are cut. Then, a divided chip including the first memory device 626, the plurality of fuses 633, the shared circuit 627, and the second memory device 628 is commercialized. However, since the plurality of fuses 635 are cut, the second storage device 628 does not function.
[0226]
When the semiconductor memory device of FIG. 20 is used as the original chip, the plurality of fuses 633 and the plurality of fuses 635 are not cut.
[0227]
As described above, the modification of the semiconductor memory device according to the seventh embodiment has all the configurations of the semiconductor memory device according to the seventh embodiment. For this reason, the modification of the semiconductor memory device according to the seventh embodiment has the same effect as the semiconductor memory device according to the seventh embodiment.
[0228]
Note that the decoder 627 illustrated in FIG. 19 can be used as the shared circuit 627.
[0229]
FIG. 21 is a schematic block diagram showing another modification of the semiconductor memory device according to the seventh embodiment. Note that portions similar to those in FIG. 20 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0230]
Referring to FIG. 21, another modification example of the semiconductor memory device according to the seventh embodiment includes a first memory device 626, a plurality of fuses 633, a plurality of pads 637, a plurality of fuses 635, and a second memory device 628. including. The plurality of pads 637 are connected to the memory cell matrix M1 through the plurality of fuses 633. The plurality of pads 637 are connected to the memory cell matrix M2 through the plurality of fuses 635.
[0231]
The plurality of pads 637 are pads that can be shared by the memory cell matrix M1 and the memory cell matrix M2.
[0232]
When there is a defective bit (defective memory cell) in the memory cell matrix M1, a plurality of fuses 633 are cut. Then, a divided chip including the first storage device 626, the plurality of pads 637, the plurality of fuses 635, and the second storage device 628 is commercialized. However, since the plurality of fuses 633 are cut, the first storage device 626 does not function.
[0233]
When there is a defective bit (defective memory cell) in the memory cell matrix M2, the plurality of fuses 635 are cut. Then, a divided chip including the second memory device 628, the plurality of pads 637, the plurality of fuses 633, and the first memory device 626 is commercialized. However, since the plurality of fuses 635 are cut, the second storage device 628 does not function.
[0234]
When the semiconductor memory device of FIG. 21 is used as the original chip, the plurality of fuses 633 and the plurality of fuses 635 are not cut. A plurality of pads 637 are shared by the memory cell matrix M1 and the memory cell matrix M2.
[0235]
As described above, in another modification of the semiconductor memory device of the seventh embodiment, in the case of the original chip, the pads that can be shared by the two unit chips 626 and 628 are shared. For this reason, the area of the original chip can be reduced.
[0236]
Further, the first and second storage devices 626 and 628 of the semiconductor storage device in FIG. 21 are the same as the first and second storage devices 626 and 628 in FIG. Therefore, in another modification of the semiconductor memory device according to the seventh embodiment, the same effect as that of the semiconductor memory device according to the seventh embodiment is obtained.
[0237]
(Embodiment 8)
The semiconductor memory device according to the eighth embodiment is premised on the semiconductor memory device according to the first to seventh embodiments. Therefore, the semiconductor memory device according to the eighth embodiment has the same effects as the semiconductor memory devices according to the first to seventh embodiments. The characteristic part of the semiconductor memory device according to the eighth embodiment will be described below.
[0238]
FIG. 22 is a schematic diagram showing a characteristic part of the semiconductor memory device according to the eighth embodiment. The meanings of the basic chip, the divided chip, the original chip, and the unit chip are the same as described in the first to seventh embodiments.
[0239]
Referring to FIG. 22, first storage device 639 and second storage device 641 are formed in a region surrounded by a corresponding section of dicing line 643 and dicing line 645. The first storage device 639 and the second storage device 641 are the same as the first storage device and the second storage device of the semiconductor storage device according to the first to seventh embodiments.
[0240]
The first storage device 639 includes a power supply pad 647 for supplying a power supply potential thereto. Second storage device 641 includes a power supply pad 649 for supplying a power supply potential thereto. The power supply pads 647 and 649 are arranged in the vicinity of one end point of the section of the dicing line 643 corresponding to the first storage device 639 and the second storage device 641.
[0241]
Therefore, when the dicing line 645 is cut and the semiconductor memory device of FIG. 22 is used as the original chip, since the power supply pad 647 and the power supply pad 649 are close to each other, A power supply potential can be supplied to the power supply pads 647 and 649. That is, the lead frame 533 and the power supply pad 647 can be connected by the wire 535. Further, the lead frame 533 and the power supply pad 649 can be connected by a wire 535.
[0242]
When the semiconductor memory device of FIG. 22 is divided into chips, dicing lines 643 and 645 are cut.
[0243]
FIG. 23 is a schematic diagram showing a modification of the semiconductor memory device according to the eighth embodiment. Note that portions similar to those in FIG. 22 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0244]
Referring to FIG. 23, first storage device 639 includes power supply pad 651 at the center of one side of first storage device 639 along dicing line 645. The power supply pad 651 is connected to the power supply pad 647. The second storage device 641 includes a power pad 653 at the center of one side of the second storage device 641 along the dicing line 645. The power supply pad 653 and the power supply pad 649 are connected.
[0245]
When the semiconductor memory device (basic chip) of FIG. 23 is a divided chip, it is cut along dicing lines 643 and 645. In the divided chip corresponding to the first memory device 639, the lead frame 655 and the pad 651 are connected by the wire 659, and the power supply potential is supplied. A lead frame 657 and a power supply pad 653 are connected to a divided chip corresponding to the second storage device 641 by a wire 661, and a power supply potential is supplied.
[0246]
FIG. 24 is a schematic diagram showing another modification of the semiconductor memory device according to the eighth embodiment. Note that portions similar to those in FIG. 23 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0247]
Referring to FIG. 24, power supply pad 647 and power supply pad 649 are connected by wire 667.
[0248]
24 is cut along the dicing line 645 when the semiconductor memory device of FIG. Either the pad 651 or the pad 653 can be used to supply the power supply potential to the original chip.
[0249]
When the semiconductor memory device of FIG. 24 is divided into chips, dicing lines 643 and 645 and wires 667 are cut. The supply of the power supply potential to the divided chip corresponding to the first memory device 639 and the divided chip corresponding to the second memory device 641 is the same as that of the semiconductor memory device in FIG.
[0250]
(Embodiment 9)
The semiconductor memory device according to the ninth embodiment is premised on the semiconductor memory device according to the first to eighth embodiments. Therefore, the semiconductor memory device according to the ninth embodiment has the same effects as the semiconductor memory devices according to the first to eighth embodiments.
[0251]
In the basic chip, the first storage device and the second storage device may be connected by a metal wiring such as aluminum. At this time, when cutting along the dicing line in order to make the basic chip into divided chips, damage may be caused by the cutting. That is, a crack or the like may occur on the cut surface cut along the dicing line. The semiconductor memory device according to the ninth embodiment has been made to solve such a problem.
[0252]
Hereinafter, the characteristic part will be described.
FIG. 25 is a schematic diagram showing a characteristic part of the semiconductor memory device according to the ninth embodiment.
[0253]
Referring to FIG. 25, first storage device 679 and second storage device 681 are formed in a region surrounded by dicing line 669 and dicing line 671. The first storage device 679 and the second storage device 681 are the same as the first storage device and the second storage device of the semiconductor storage device according to the first to eighth embodiments.
[0254]
Referring to FIG. 25, when the pad 673 included in the first storage device 679 and the pad 675 included in the second storage device 681 are connected by the metal wiring 677, a dicing line is included in the metal wiring 677. A predetermined portion on both sides of 669 (indicated by arrows A and B) is cut by a laser before cutting along the dicing line 669.
[0255]
As described above, in the semiconductor memory device according to the ninth embodiment, when divided chips are used, the first memory device 679 and the second memory device 681 are connected before cutting along the dicing line 669. Of the metal wiring 677, predetermined portions on both sides of the dicing line 669 are cut. By doing so, it is possible to prevent the occurrence of cracks and the like due to cutting along the dicing line.
[0256]
FIG. 26 is a schematic diagram showing a modification of the semiconductor memory device according to the ninth embodiment. Note that portions similar to those in FIG. 25 are denoted by the same reference numerals, and the connection thereof is omitted as appropriate.
[0257]
Referring to FIG. 26, predetermined portions (indicated by arrows A and B) on both sides of dicing line 699 in metal wiring 677 connecting first storage device 679 and second storage device 681 are as follows. Make it thinner than other parts. This is for facilitating cutting with a laser as shown in the description of FIG.
[0258]
Further, in order to facilitate the cutting with the laser as shown in the description of FIG. 25, the semiconductor memory device can be configured as follows.
[0259]
FIG. 27 is a schematic diagram showing another modification of the semiconductor memory device according to the ninth embodiment. Note that portions similar to those in FIG. 25 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0260]
Referring to FIG. 27, in the basic chip, first storage device 679 and second storage device 681 are connected as follows. Metal wiring 683 and polysilicon 689 are connected through contact hole 693. Polysilicon 689 and metal wiring 685 are connected through contact hole 693. Polysilicon 691 and metal wiring 685 are connected through contact hole 693. Polysilicon 691 and metal wiring 687 are connected through contact hole 693.
[0261]
Instead of polysilicon 689 and 691, a material that is more easily cut by heat than metal wiring such as aluminum can be used.
[0262]
Cutting with a laser as shown in the description of FIG. 25 is performed on polysilicon 689 and 691. That is, in the case of a divided chip, the polysilicon 689 and 691 are cut with a laser to prevent generation of cracks that may occur when the dicing line 669 is cut.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a semiconductor memory device according to a first embodiment of the present invention.
2 is a diagram for explaining in detail the semiconductor memory device of FIG. 1; FIG.
3 is a circuit diagram showing details of a part of the semiconductor memory device of FIG. 2;
4 is a schematic block diagram showing a part of a selection circuit used when the semiconductor memory device of FIG. 2 is used as an original chip;
5 is a detailed circuit diagram showing another part of the selection circuit used when the semiconductor memory device of FIG. 2 is used as the original chip; FIG.
FIG. 6 is a schematic block diagram showing a modification of the semiconductor memory device according to the first embodiment of the present invention.
FIG. 7 is a schematic block diagram showing another modification of the semiconductor memory device according to the first embodiment of the present invention.
FIG. 8 is a schematic block diagram showing a semiconductor memory device according to a second embodiment of the present invention.
FIG. 9 is a schematic block diagram showing a modification of the semiconductor memory device according to the second embodiment of the present invention.
FIG. 10 is a schematic block diagram showing a semiconductor memory device according to a third embodiment of the present invention.
FIG. 11 is a schematic block diagram showing a modification of the semiconductor memory device according to the third embodiment of the present invention.
FIG. 12 is a schematic block diagram showing a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 13 is a schematic block diagram showing a modification of the semiconductor memory device according to the fourth embodiment of the present invention.
FIG. 14 is a schematic block diagram showing a semiconductor memory device according to a fifth embodiment of the present invention.
FIG. 15 is a schematic block diagram showing a modification of the semiconductor memory device according to the fifth embodiment of the present invention.
FIG. 16 is a schematic block diagram showing a semiconductor memory device according to a sixth embodiment of the present invention.
FIG. 17 is a schematic block diagram showing a part of a modification of the semiconductor memory device according to the sixth embodiment of the present invention;
FIG. 18 is a schematic block diagram showing a semiconductor memory device according to a seventh embodiment of the present invention.
19 is a circuit diagram showing a specific example of the shared circuit of FIG. 18;
FIG. 20 is a schematic block diagram showing a modification of the semiconductor memory device according to the seventh embodiment of the present invention.
FIG. 21 is a schematic block diagram showing another modification of the semiconductor memory device according to the seventh embodiment of the present invention.
FIG. 22 is a schematic diagram showing a characteristic part of a semiconductor memory device according to an eighth embodiment of the present invention.
FIG. 23 is a schematic diagram showing a modification of the semiconductor memory device according to the eighth embodiment of the present invention.
FIG. 24 is a schematic diagram showing another modification of the semiconductor memory device according to the eighth embodiment of the present invention.
FIG. 25 is a schematic diagram showing a characteristic part of a semiconductor memory device according to a ninth embodiment of the present invention.
FIG. 26 is a schematic diagram showing a modification of the semiconductor memory device according to the ninth embodiment of the present invention.
FIG. 27 is a schematic diagram showing another modification of the semiconductor memory device according to the ninth embodiment of the present invention.
FIG. 28 is a schematic view showing a conventional semiconductor memory device formed on a wafer.
29 is an enlarged view of one of a plurality of conventional semiconductor memory devices formed on the wafer of FIG. 28. FIG.
[Explanation of symbols]
1-23, 501-513, 537-559, 593-601, 615-621, 643, 645, 663, 665, 669, 671, 697 dicing line, 29, 35 buffer, 37, 41, 45, 49, 631 NAND circuit, 39, 43, 47, 51, 629 Inverter, 100, 525, 585, 603, 626, 639, 679 First storage device, 25, 31, 101, 103, 113, 201, 213, 301, 303 , 313, 401, 413, 517, 521, 523, 569 to 575, 637, 673, 675, 701, 703 pad, 105, 205, 305, 405, 705 Address buffer block, 107, 207, 307, 407, 711 Decoder, 109, 209, 309, 409, 707 sense amplifier Block, 111, 211, 311, 411, 709 output buffer block, 27, 33, 115, 215, 217, 219, 315, 415, 417, 419, 529, 531, 577 to 583, 633, 635 fuse, 116, 216, 316, 416 Sense amplifier, 118, 218, 318, 418, 515, 519, 561 to 567 Output buffer, 121, 221, 321, 421 Data input / output line section, 123, 223, 323, 423 Column selection circuit block 124 memory cells, 125 word lines, 126, 226, 326, 426 column selection circuits, 127 column selection lines, 129, 131 NMOS transistors, 200, 527, 587, 605, 628, 641, 681 second storage device, 300,589 Third storage device 400, 91 Fourth memory device, 533, 655, 657 lead frame, 535, 659, 661, 667 wire, 607 original chip dedicated circuit, 609 glass coat, 661 silicon substrate, 613 selection circuit, 627 shared circuit, 647, 649, 651, 653 power supply pad, 677, 683-687 metal wiring, 689, 691 polysilicon, 693 contact hole, 695 wafer, 699 semiconductor memory device.

Claims (18)

A semiconductor memory device,
A first storage device for reading or writing information;
A second storage device for reading or writing information,
The first storage device
A first buffer block including a plurality of first buffers for transmitting and receiving a plurality of first signals;
A second buffer block including a second buffer for transmitting and receiving a second signal;
A first pad block connected to the plurality of first buffers and including a plurality of first pads for sending and receiving the plurality of first signals to the outside;
A second pad block connected to the second buffer and including a second pad for transmitting and receiving the second signal to the outside;
The second storage device
A third buffer block including a plurality of third buffers for transmitting and receiving a plurality of third signals;
A fourth buffer block including a fourth buffer for transmitting and receiving a fourth signal;
A third pad block connected to the plurality of third buffers and including a plurality of third pads for sending and receiving the plurality of third signals to the outside;
A fourth pad block connected to the fourth buffer and including a fourth pad for transmitting and receiving the fourth signal to the outside;
When assembly is performed using the first and second storage devices as separate storage devices, the first storage device and the second storage device are disconnected.
When the first and second storage devices are assembled and used as one storage device, the second buffer and the fourth buffer are connected to the corresponding third pad, and the corresponding The third pad is used for transmission / reception of the second signal and the fourth signal, and for transmission / reception of the plurality of first signals and the plurality of third signals, the plurality of first signals A buffer and the plurality of first pads are used;
The semiconductor memory device further includes selection means for selecting whether the third pad is used for the second signal or the fourth signal.
The selection means is used when the first and second storage devices are used as one storage device for assembly.
When the first and second storage devices are assembled and used as one storage device and the first storage device is selected by an external selection signal, the plurality of first pads are used. Is used for transmission / reception of the plurality of first signals, and when the second storage device is selected by the selection signal, the plurality of first pads are connected to the plurality of third signals. A semiconductor memory device used for giving and receiving. A semiconductor memory device,
A first storage device for reading or writing information;
A second storage device for reading or writing information,
The first storage device
A first buffer block including a plurality of first buffers for transmitting and receiving a plurality of first signals;
A second buffer block including a second buffer for transmitting and receiving a second signal;
A first pad block connected to the plurality of first buffers and including a plurality of first pads for sending and receiving the plurality of first signals to the outside;
A second pad block connected to the second buffer and including a second pad for transmitting and receiving the second signal to the outside;
The second storage device
A third buffer block including a plurality of third buffers for transmitting and receiving a plurality of third signals;
A fourth buffer block including a fourth buffer for transmitting and receiving a fourth signal;
A third pad block connected to the plurality of third buffers and including a plurality of third pads for sending and receiving the plurality of third signals to the outside;
A fourth pad block connected to the fourth buffer and including a fourth pad for transmitting and receiving the fourth signal to the outside;
The semiconductor memory device further includes a fifth pad,
The second pad and the fourth pad are connected to the fifth pad;
When assembling the first storage device and the second storage device as separate storage devices, the first storage device and the second storage device are disconnected, and the fifth pad is used. Not
When the first and second storage devices are assembled and used as one storage device, the fifth pad is used for transmission and reception of the second signal and the fourth signal when used.
The semiconductor memory device further includes selection means for selecting whether the fifth pad is used for the second signal or the fourth signal.
The selection means is used when the first and second storage devices are assembled and used as one storage device.
The plurality of first pads, the plurality of third pads, the plurality of first buffers, and the plurality of third buffers are arranged in a predetermined direction,
The first pad block and the first buffer block are close to each other,
The second pad block and the second buffer block are close to each other,
The third pad block and the third buffer block are close to each other,
The semiconductor memory device, wherein the fourth pad block and the fourth buffer block are close to each other. A semiconductor memory device,
A first storage device for reading or writing information;
A second storage device for reading or writing information,
The first storage device
A first buffer block including a plurality of first buffers for transmitting and receiving a plurality of first signals;
A second buffer block including a second buffer for transmitting and receiving a second signal;
A first pad block connected to the plurality of first buffers and including a plurality of first pads for sending and receiving the plurality of first signals to the outside;
A second pad block connected to the second buffer and including a second pad for transmitting and receiving the second signal to the outside;
The second storage device
A third buffer block including a plurality of third buffers for transmitting and receiving a plurality of third signals;
A fourth buffer block including a fourth buffer for transmitting and receiving a fourth signal;
A third pad block connected to the plurality of third buffers and including a plurality of third pads for sending and receiving the plurality of third signals to the outside;
A fourth pad block connected to the fourth buffer and including a fourth pad for transmitting and receiving the fourth signal to the outside;
The semiconductor memory device further includes a fifth pad,
The second buffer, the second pad, the fourth buffer, and the fourth pad are connected to the fifth pad;
When assembling the first storage device and the second storage device as separate storage devices, the first storage device and the second storage device are disconnected, and the fifth pad is used. Not
When the first and second storage devices are assembled and used as one storage device, the second pad and the second buffer are disconnected from each other, and the fourth pad and the second storage device are disconnected. 4 buffer is disconnected, and the fifth pad is used to send and receive the second signal and the fourth signal,
The semiconductor memory device further includes selection means for selecting whether the fifth pad is used for the second signal or the fourth signal.
The selection means is used when the first and second storage devices are assembled and used as one storage device.
The plurality of first pads, the plurality of third pads, the plurality of first buffers, and the plurality of third buffers are arranged in a predetermined direction,
The first pad block and the first buffer block are close to each other,
The second pad block and the second buffer block are close to each other,
The third pad block and the third buffer block are close to each other,
The semiconductor memory device, wherein the fourth pad block and the fourth buffer block are close to each other. A semiconductor memory device,
A first storage device for reading or writing information;
A second storage device for reading or writing information,
The first storage device
A first buffer block including a plurality of first buffers for transmitting and receiving a plurality of first signals;
A second buffer block including a second buffer for transmitting and receiving a second signal;
A first pad block connected to the plurality of first buffers and including a plurality of first pads for sending and receiving the plurality of first signals to the outside;
A second pad block connected to the second buffer and including a second pad for transmitting and receiving the second signal to the outside;
The second storage device
A third buffer block including a plurality of third buffers for transmitting and receiving a plurality of third signals;
A fourth buffer block including a fourth buffer for transmitting and receiving a fourth signal;
A third pad block connected to the plurality of third buffers and including a plurality of third pads for sending and receiving the plurality of third signals to the outside;
A fourth pad block connected to the fourth buffer and including a fourth pad for transmitting and receiving the fourth signal to the outside;
The second pad and the fourth pad are connected,
When assembling the first storage device and the second storage device as separate storage devices, the first storage device and the second storage device are disconnected,
When the first and second storage devices are assembled and used as a single storage device, when the first signal and the second signal are exchanged, the second pad or the fourth pad is used. Any of these can be used,
The semiconductor memory device further includes selection means for selecting whether the second pad or the fourth pad is used for the second signal or the fourth signal,
The selection means is used when the first and second storage devices are assembled and used as one storage device.
The plurality of first pads, the plurality of third pads, the plurality of first buffers, and the plurality of third buffers are arranged in a predetermined direction,
The first pad block and the first buffer block are close to each other,
The second pad block and the second buffer block are close to each other,
The third pad block and the third buffer block are close to each other,
The semiconductor memory device, wherein the fourth pad block and the fourth buffer block are close to each other. A semiconductor memory device,
A first storage device for reading or writing information;
A second storage device for reading or writing information,
The first storage device
A first buffer block including a plurality of first buffers for transmitting and receiving a plurality of first signals;
A second buffer block including a second buffer for transmitting and receiving a second signal;
A first pad block connected to the plurality of first buffers and including a plurality of first pads for sending and receiving the plurality of first signals to the outside;
A second pad block connected to the second buffer and including a second pad for transmitting and receiving the second signal to the outside;
The second storage device
A third buffer block including a plurality of third buffers for transmitting and receiving a plurality of third signals;
A fourth buffer block including a fourth buffer for transmitting and receiving a fourth signal;
A third pad block connected to the plurality of third buffers and including a plurality of third pads for sending and receiving the plurality of third signals to the outside;
A fourth pad block connected to the fourth buffer and including a fourth pad for exchanging the fourth signal to the outside;
The second buffer and the fourth buffer are connected;
When assembling the first storage device and the second storage device as separate storage devices, the first storage device and the second storage device are disconnected,
When the assembly is performed with the first and second storage devices as one storage device, the connection between the second buffer and the second pad or the fourth buffer and the fourth pad When the connection between the second buffer and the second pad is disconnected, the fourth pad transmits and receives the second signal and the fourth signal. And when the connection between the fourth buffer and the fourth pad is broken, the second pad is used for sending and receiving the second signal and the fourth signal,
The semiconductor memory device further includes selection means for selecting whether the second pad or the fourth pad is used for the second signal or the fourth signal,
The selection means is used when the first and second storage devices are assembled and used as one storage device.
The plurality of first pads, the plurality of third pads, the plurality of first buffers, and the plurality of third buffers are arranged in a predetermined direction,
The first pad block and the first buffer block are close to each other,
The second pad block and the second buffer block are close to each other,
The third pad block and the third buffer block are close to each other,
The semiconductor memory device, wherein the fourth pad block and the fourth buffer block are close to each other. A semiconductor memory device,
A first storage device for reading or writing information;
A second storage device for reading or writing information,
The first storage device
A first buffer block including a plurality of first buffers for transmitting and receiving a plurality of first signals;
A second buffer block including a second buffer for transmitting and receiving a second signal;
A first pad block connected to the plurality of first buffers and including a plurality of first pads for sending and receiving the plurality of first signals to the outside;
A second pad block connected to the second buffer and including a second pad for transmitting and receiving the second signal to the outside;
The second storage device
A third buffer block including a plurality of third buffers for transmitting and receiving a plurality of third signals;
A fourth buffer block including a fourth buffer for transmitting and receiving a fourth signal;
A third pad block connected to the plurality of third buffers and including a plurality of third pads for sending and receiving the plurality of third signals to the outside;
A fourth pad block connected to the fourth buffer and including a fourth pad for transmitting and receiving the fourth signal to the outside;
When assembling the first storage device and the second storage device as separate storage devices, the first storage device and the second storage device are disconnected,
When the first and second storage devices are assembled and used as one storage device, the second buffer is connected to the third pad, and the fourth buffer is connected to the second storage device. The third pad is connected to the third pad different from the third pad to which the buffer is connected, and the third pad to which the second buffer is connected is used for sending and receiving the second signal, The third pad connected to the fourth buffer is used for transmission / reception of the fourth signal, and for transmission / reception of the plurality of first signals and the plurality of third signals, The first buffer and the plurality of first pads are used, the second pad is not used for transferring the second signal, and the fourth pad is the fourth signal. The third buffer buffer is not used for Click is not used for transfer of the plurality of third signals,
The first pad block further includes a fifth pad for exchanging a selection signal for selecting the first storage device or the second storage device,
The first buffer block further includes a fifth buffer for exchanging the selection signal,
When the first and second storage devices are assembled and used as one storage device, the fifth pad and the fifth buffer are used, and the first storage device is determined by the selection signal. Is selected, the plurality of first pads are used for transmission / reception of the plurality of first signals. When the second storage device is selected by the selection signal, the plurality of first pads is used. 1 pad is used for sending and receiving the plurality of third signals,
The plurality of first pads, the plurality of third pads, the fifth pad, the plurality of first buffers, the plurality of third buffers, and the fifth buffer are arranged in a predetermined direction. And
The first pad block and the first buffer block are close to each other,
The second pad block and the second buffer block are close to each other,
The third pad block and the third buffer block are close to each other,
The semiconductor memory device, wherein the fourth pad block and the fourth buffer block are close to each other. The first storage device and the second storage device are arranged via a dicing line,
When the wiring connecting the first storage device and the second storage device passes on the dicing line, when cutting along the dicing line, before the cutting, the wiring 7. The semiconductor memory device according to claim 1, wherein portions on both sides of the dicing line are cut. The semiconductor memory device according to claim 7, wherein a portion of the wiring to be cut is thinner than other portions. The semiconductor memory device according to claim 7, wherein a portion of the wiring that performs the cutting is polysilicon. Between the first storage device and the second storage device, a circuit or a pad that can be shared by the first and second storage devices is disposed,
If either the first or second storage device is not required, the assembly is performed including the shareable circuit or pad as part of the required first or second storage device. Item 7. The semiconductor memory device according to any one of Items 1 to 6. The shareable circuit or pad and the first and second storage devices are connected by a fuse,
The semiconductor memory device according to claim 10, wherein assembly is performed by cutting a fuse between the unnecessary first or second memory device and the shared circuit or pad. The first storage device and the second storage device are arranged via a dicing line,
7. The circuit or pad according to claim 1, wherein a circuit or a pad used only when the assembly is performed and used is arranged on the dicing line with the first and second storage devices as one storage device. The semiconductor memory device described. The first storage device and the second storage device are arranged via corresponding sections of a dicing line,
The first storage device
A first power supply pad for supplying a power supply potential thereto;
The second storage device
A second power supply pad for supplying a power supply potential thereto;
The semiconductor memory device according to claim 1, wherein the first and second power supply pads are arranged in the vicinity of one end point of a corresponding section of the dicing line. The first storage device
A third power pad connected to the first power pad;
The second storage device
The semiconductor memory device according to claim 13, further comprising a fourth power supply pad connected to the second power supply pad. When using the first and second storage devices as a single storage device, the first power supply pad and the second power supply pad are connected,
The semiconductor memory device according to claim 14, wherein the power supply potential is supplied from the outside using either the second power supply pad or the fourth power supply pad. The second signal is first data output from the first storage device to the outside or input from the outside to the first storage device,
The fourth signal is second data output from the second storage device to the outside or input from the outside to the second storage device,
The first storage device further includes a first data input / output line pair for inputting / outputting the first data;
The semiconductor memory device according to claim 1, wherein the second memory device further includes a second data input / output line pair for inputting / outputting the second data. A plurality of the second buffer, the second pad, the fourth buffer, and the fourth pad are provided,
Each of the second signal and the fourth signal is plural,
The plurality of second signals are a plurality of first data output from the first storage device to the outside or input from the outside to the first storage device,
The plurality of fourth signals are a plurality of second data output from the second storage device to the outside or input from the outside to the second storage device,
The first storage device further includes a plurality of first data input / output line pairs for inputting / outputting the plurality of first data,
7. The device according to claim 1, wherein the second storage device further includes a plurality of second data input / output line pairs that input / output the plurality of second data. 8. The semiconductor memory device described. A plurality of the second buffer, the second pad, the fourth buffer, the fourth pad, and the fifth pad are provided,
The plurality of second buffers, the plurality of second pads, the plurality of fourth buffers, the plurality of fourth pads, and the plurality of fifth pads are arranged in the predetermined direction,
Each of the second signal and the fourth signal is plural,
The plurality of second signals are a plurality of first data output from the first storage device to the outside or input from the outside to the first storage device,
The plurality of fourth signals are a plurality of second data output from the second storage device to the outside or input from the outside to the second storage device,
The first storage device further includes a plurality of first data input / output line pairs for inputting / outputting the plurality of first data,
4. The semiconductor memory device according to claim 2, wherein the second memory device further includes a plurality of second data input / output line pairs for inputting / outputting the plurality of second data.

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