JP3703385B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus such as a digital camera.
[0002]
[Prior art]
An example of the configuration of a conventional solid-state imaging device is shown in FIG. In the figure, reference numeral 101 denotes a pixel having a photoelectric conversion unit such as a photodiode, and a pixel region 100 for capturing a subject image is formed by arranging the pixels in a two-dimensional manner.
[0003]
Reference numeral 103 denotes a vertical signal line from which a signal from the pixel 101 is read out, and reference numeral 104 denotes a pixel. From A storage capacitor for temporarily storing the signal read to the vertical signal line, 105 is a transfer MOS transistor for transferring the signal read to the vertical signal line 103 to the storage capacitor 104, and 106a and 106b are signals of the storage capacitor 104. Is a transfer MOS transistor for transferring to the horizontal signal line 107.
[0004]
Further, reference numeral 108 denotes a vertical scanning circuit which controls to read out signals from the pixels 101 to the vertical signal lines 103 for each row by sequentially scanning the pixels 101 in one row in the horizontal direction in the vertical direction, and 109a and 109b to transfer. By controlling the MOS transistors 106a and 106b, a horizontal scanning circuit for sequentially reading the signals accumulated in the storage capacitor 104 to the horizontal signal lines 107a and 107b, and 110a and 110b are resets for resetting the horizontal signal lines 107a and 107b. It is a MOS transistor. Reference numeral 107 denotes a load current source that forms a transistor and a source follower included in the pixel 101.
[0005]
Here, the arrangement of the color filters of the conventional solid-state imaging device will be described. FIG. 11 shows an example of the above. 121 is a first color filter that transmits red light, 122 is a second color filter that transmits green light, and 123 is a third color filter that transmits blue light. .
[0006]
The first color filter 121 and the second color filter 122 are alternately arranged in the odd-numbered columns starting from the first column of the pixels 101 corresponding to the pixels arranged two-dimensionally, and the pixels The second color filter 122 and the third color filter 123 are alternately arranged in the even columns starting from the second column. Furthermore, the second color filters 122 are arranged so as not to be adjacent to each other in the horizontal direction in the odd and even columns.
[0007]
[Problems to be solved by the invention]
However, the conventional solid-state image sensor has a pixel region 100 11 includes a plurality of color filters as shown in FIG. 11. However, in this method, for example, in the case of a solid-state image sensor having a pixel pitch of 10 μm and a pixel count of 640 horizontal pixels and 480 vertical pixels, the standard image is displayed. The focal length of the lens providing the angle is 8 mm, which is the diagonal length of the solid-state imaging device.
[0008]
For this reason, when manufacturing an imaging apparatus such as a digital camera using such a solid-state imaging device, there is a limit to reducing the thickness.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides: A first pixel region that outputs a signal of a first color component, a plurality of pixels that are arranged two-dimensionally in a horizontal direction and a vertical direction, and a plurality of pixels that outputs a signal of a second color component A second pixel region that is arranged two-dimensionally in a horizontal direction and a vertical direction, and that is provided in a direction perpendicular to the first pixel region; and a plurality of pixels in a direction perpendicular to the first pixel region And a plurality of first output lines provided one by one in common with a plurality of pixels in the vertical direction of the second pixel region, and common to the first pixel region and the second pixel region. And an output unit that sequentially outputs signals from the plurality of output lines on the same semiconductor chip, and after reading the first line signal of the first pixel region to the output unit, Read the signal of the first line of the second pixel area to the output unit, then The first pixel region and the first pixel region are read so that the second line signal of the first pixel region is read to the output unit and then the second line signal of the second pixel region is read to the output unit. The second pixel region is driven so as to read out signals to the output unit alternately for each line. It is characterized by that.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a schematic diagram showing the configuration of the solid-state imaging device according to the first embodiment of the present invention, which is formed on the same semiconductor chip by, for example, a CMOS process. In FIG. 1, reference numeral 905 denotes a pixel having a photodiode, reference numerals 901 to 904 denote an imaging region provided with R, G1, G2, and B filters that form a two-dimensionally arranged pixel 905, and 906a denotes an imaging region. A vertical shift register 906b outputs a control signal generated to control vertical pixel scanning 901 and 902 in accordance with an externally input clock signal VCLK2, and 906b controls vertical pixel scanning of the imaging regions 903 and 904. A vertical shift register 907, which is a signal supply means for outputting a control signal generated for this purpose in accordance with an externally input clock signal VCLK1, is charged from within the pixel 905 in accordance with the control signals output from the vertical shift registers 906a and 906b. Or includes a readout pulse that reads the amplified signal based on the charge A pulse signal output circuit for outputting a pulse signal for driving the element 905; 909, a horizontal signal line for transmitting the pulse signal output from the pulse signal output circuit 907 to each pixel 905; and 912, a charge read from each pixel 905. 910 is a line memory that holds the transmitted charge for each row, 911 a is a read from the imaging areas 901 and 903 among the charges held in the line memory 910. A horizontal shift register 911b that generates a control signal for sequentially outputting the signals to an external processing circuit and outputs the control signal according to an externally input clock signal HCLK1; A control signal for sequentially outputting the read data to an external processing circuit is generated and the clock input from the outside is generated. A horizontal shift register which is a reading means for outputting in accordance with the signal HCLK2, 913 is an amplifier which is an output unit for amplifying charges output from the line memory 910, and 914 is an output terminal for outputting the amplified charges etc. to the processing circuit. .
[0015]
In FIG. 1, 3 × 3 pixels are illustrated in the imaging regions 901 to 904 in order to avoid complication, but in actuality, depending on the resolution required in both the horizontal and vertical directions. A plurality of pixels are arranged. Further, the numbers given to the respective pixels 905 mean the order of reading out charges and the like as will be described later.
[0016]
FIG. 2 is a circuit diagram of the pixel 905, the pulse signal output circuit 907, and the line memory 910. In FIG. 2, reference numeral 921 denotes a photodiode for converting light into electric charge, 922 denotes a transfer switch for transferring the electric charge converted by the photodiode 921 to the floating diffusion region, and 923 denotes a MOS for obtaining an amplified signal based on the transferred electric charge. A transistor, 925 is a selection switch for selecting the pixel 905 for reading the amplified signal to the vertical signal line 912, and 924 is a reset switch for resetting the potential of the floating diffusion region and the photodiode 921 after reading the amplified signal.
[0017]
In FIG. 2, reference numerals 926 to 928 denote selection pulses for controlling ON / OFF of the selection switch 925, the reset switch 924, and the transfer switch 922, a selection pulse transmission line for transmitting the reset pulse and the transfer pulse, a reset pulse transmission line, and Transfer pulse transmission lines 931 to 933 are transfer pulse generation signals for inputting transfer pulse transmission lines 928, reset pulse transmission lines 927 and selection pulse transmission lines 926, and generation signals for generating reset pulses and selection pulses, respectively. An input terminal, a reset pulse generation signal input terminal and a selection pulse generation signal input terminal, 930 is a transfer pulse generation signal input terminal 931, each generation signal input from the reset pulse generation signal input terminal 932 and the selection pulse generation signal input terminal 933, and Vertical shift register AND gate for adding the control signal output from 06, 934 is an input control switch for controlling the input of the charges read to the vertical output line 912 to the line memory 910, and 937 is an on / off switch for the input control switch 934. A control pulse transmission line for transmitting a control pulse for controlling the voltage; 935, a capacitor for accumulating the charge read to each vertical output line 912; an output control switch for controlling an output of the electric charge accumulated in the capacitor 935; Reference numeral 915 denotes an input terminal for inputting a control signal from the horizontal shift register.
[0018]
Incidentally, the pixel having the MOS type image pickup device as shown in FIG. 2 is excellent in an automatic exposure mechanism (Auto Exposure), can realize low power consumption, can be formed with one chip, Although there is an advantage that nondestructive reading can be performed, in addition to the configuration shown in FIG. 2, for example, an amplified MOS imager (AMI) image sensor, a charge modulation device (CMD), a CCD image sensor, or the like can be used. For example, when a CCD imaging device is used, a vertical transfer CCD and a horizontal transfer CCD may be arranged instead of the vertical shift registers 906a and 906b and the horizontal shift registers 911a and 911b.
[0019]
The horizontal signal line 909 includes a transfer pulse transmission line 928, a reset pulse transmission line 927, and a selection pulse transmission line 926.
[0020]
Next, the operation of FIGS. 1 and 2 will be described. First, light from a subject is collected on a solid-state image sensor by an imaging lens. Then, when light enters each photodiode 921 disposed at a corresponding position in each of the R, G1, G2, and B imaging regions 901 to 904, electric charges are generated.
[0021]
In the present embodiment, as will be described later with reference to FIG. 9, the subject image is divided into a plurality of images, and each image is formed on each of the imaging regions 901 to 904.
[0022]
Thereafter, when the control signals output from the vertical shift registers 906b according to the clock signal VKLC1 are input to the pulse signal output circuit 907 through the input terminals 929, the control signal is output from the AND gate 930 in the pulse signal output circuit 907. Then, a transfer pulse signal for turning on each transfer switch 922 is generated based on the generated signal input through the transfer pulse generation signal input terminal 931 and transmitted to the pixel 905 side through the transfer pulse transmission line 928.
[0023]
Then, for example, the transfer switch 922 of the pixel 905 in each third row of the G2 imaging region 903 and the B imaging region 904 is turned on, and the charge in the photodiode 921 is transferred to the floating diffusion region. Thereby, the gate of each MOS transistor 923 is turned on by these charges.
[0024]
Next, when the control signals output from the vertical shift registers 906b according to the clock signal VKLC1 are input to the pulse signal output circuit 907 through the input terminals 929, the control signal is output from the AND gate 930 in the pulse signal output circuit 907. And a generation signal input through the selection pulse generation signal input terminal 933, a selection pulse signal for turning on the gate of each selection switch 925 of the pixel 905 from which the amplification signal based on the charge is read is generated, and the selection pulse is generated. Transmit through transmission line 926.
[0025]
Here, the pixels 905 in the third row and the first column of the G2 imaging region 903 and the third row and the first column of the B imaging region 904 are numbered as the pixels 905 in the third row of the imaging regions 901 to 904 are numbered. Eye pixel 905, pixel 905 in the third row and second column in the G2 imaging region 903, pixel 905 in the third row and second column in the B imaging region 904, pixel 905 in the third row and third column in the G2 imaging region 903, B imaging region The gate of each selection switch 925 of the pixel 905 in the third row and third column 904 is turned on.
[0026]
Thus, the amplified signal obtained by each MOS transistor 923 is read out to each vertical signal line 912. In each pixel 905 from which the amplified signal is read, an AND gate is based on the control signal output from each vertical shift register 906b according to the clock signal VKLC1 and the generation signal input through the reset pulse generation signal input terminal 932. Each reset switch 924 is turned on by the reset pulse signal generated by 930, and the potential of each floating diffusion region and each photodiode 921 is reset.
[0027]
On the other hand, the amplified signal read out to each vertical signal line 912 is stored in each capacitor 935 of the line memory 910 when the input control switch 934 is turned on according to the signal transmitted through the control pulse transmission line 937. .
[0028]
Thereafter, control signals for sequentially outputting the amplified signals accumulated in the capacitors 935 to the outside by the horizontal shift registers 911a and 911b are generated and output to the line memories 910 according to the clock signals HCLK1 and 2, respectively. Here, if the high / low of the clock signals HCLK1 and 2 are alternated with each other, the output control switches 936 are sequentially turned on and stored in the line memory 910 in the readout order of the amplified signal of each pixel 905. The amplified signal is output to the outside.
[0029]
Similarly, an amplified signal is read from each pixel 905 in the third row of the R imaging area 901 and the G1 imaging area 902. Subsequently, each pixel 905 in the second row of the G2 imaging region 903, B imaging region 904, each pixel 905 in the second row of the R imaging region 901, G1 imaging region 902, one of the G2 imaging region 903, and the B imaging region 904. The amplified signals from the pixels 905 in the row, the pixels 905 in the first row of the R imaging region 901 and the G1 imaging region 902 are output to the outside.
[0030]
As described above, in the present embodiment, two vertical shift registers 906a and 906b and two horizontal shift registers 911a and 911b are provided for every pixel 905, so that the correspondence between the imaging regions 901 to 904 is achieved. When each charge read from the pixel 905 arranged at the position to be output is output to the processing circuit, a time difference corresponding to the output of the control signal to the pixels 905 for one row is prevented. .
[0031]
That is, when a signal from one imaging area is output to an imaging area arranged in the vertical direction and then a signal from the next imaging area is output, between the two imaging areas in the vertical direction. The photocharge accumulation time is greatly deviated and adversely affects the final image.
[0032]
Specifically, the time loss caused in the processing circuit is, for example, when m pixels are arranged in each imaging region, that is, when 2 m pixels are arranged in the entire solid-state imaging device, i (1 ≦ i of the R imaging region). ≦ m) From the time when the control signal is output to the pixel in the row until the control signal is output to the pixel in the i (1 ≦ i ≦ m) row of the G2 imaging region Although the time difference is equivalent to the output of the control signal to the pixel, in this embodiment, the drive as described above eliminates the deviation of the photocharge accumulation time between the two imaging regions in the vertical direction.
[0033]
Further, in the present embodiment, when signals stored in the line memory are read, signals are output alternately for each pixel from different imaging areas, so that processing in the subsequent processing circuit is facilitated.
[0034]
Further, in this embodiment, an amplifier or the like is not provided for each imaging region, and the four imaging regions are provided in common. Na An image can be obtained.
[0035]
(Embodiment 2)
FIG. 3 is a schematic diagram showing the configuration of the solid-state imaging device according to the second embodiment of the present invention, which is formed on the same semiconductor chip by a CMOS process or the like. In FIG. 3, reference numerals 910a and 911b denote line memories that store charges read from the pixels 905 arranged in the R imaging area 901 and G1 imaging area 902, and 911c to 911f denote line memories 910a and 911b, respectively. This is a horizontal shift register that sequentially outputs the read charges from the R imaging area 901, G1 imaging area 902, G2 imaging area 903, and B imaging area 904 to an external processing circuit. In FIG. 3, the same parts as those shown in FIG.
[0036]
The operation of the solid-state imaging device shown in FIG. 3 is the same as that shown in FIG. 1, but the control signals generated by the vertical shift registers 906a and 906b are numbered in FIG. Focusing on the pixel 905 arranged in the third row of each imaging region 901 to 904, for example, the amplified signal from the pixel 905 in the third row and first column of the G2 imaging region 903 and the third row and first column of the R imaging region 901 And the amplified signal from the pixel 905 in the third row and first column of the B imaging region 904 and the amplified signal from the pixel 905 in the third row and first column of the G1 imaging region 902 at the same time. At the same time, the amplified signal from the pixel 905 in the third row and second column of the G2 imaging region 903 and the amplified signal from the pixel 905 in the third row and second column of the R imaging region 901 are simultaneously Pixel 90 in the third row and the second column Amplified signal and G1 and amplified signal from the third row second column pixel 905 in the imaging region 902 simultaneously, and is outputted to the processing circuit in that order from.
[0037]
Further, the amplified signal read from the pixels 905 arranged in the R imaging region 901 and accumulated in the line memory 910a is output to the processing circuit in accordance with the control signal generated by the horizontal shift register 911c. . The amplified signal read from the pixels 905 arranged in the G1 imaging region 902 and accumulated in the line memory 910a is output to the processing circuit in accordance with the control signal generated by the horizontal shift register 911d.
[0038]
Similarly, the amplified signal read from the pixels 905 arranged in the G2 imaging region 903 and accumulated in the line memory 901b is output to the processing circuit in accordance with the control signal generated by the horizontal shift register 911e. The The amplified signal read from the pixels 905 arranged in the B imaging region 904 and accumulated in the line memory 910f is output to the processing circuit in accordance with the control signal generated by the horizontal shift register 911d.
[0039]
As described above, in the present embodiment, the two vertical shift registers 906a and 906b and the four horizontal shift registers 911c to 911f are provided for all the pixels 905, so that the correspondence between the imaging regions 901 to 904 is achieved. A time difference is prevented from occurring when each charge read from the pixel 905 arranged at the position to be output is output to the processing circuit.
[0040]
That is, when a signal from one imaging area is output to an imaging area arranged in the vertical direction and then a signal from the next imaging area is output, between the two imaging areas in the vertical direction. The photocharge accumulation time is greatly deviated and adversely affects the final image.
[0041]
Specifically, the time loss caused in the processing circuit is, for example, when m pixels are arranged in each imaging region, that is, when 2 m pixels are arranged in the entire solid-state imaging device, i (1 ≦ i of the R imaging region). ≦ m) From the time when the control signal is output to the pixel in the row until the control signal is output to the pixel in the i (1 ≦ i ≦ m) row of the G2 imaging region Although there is a time difference corresponding to the output of the control signal to the pixel, in this embodiment, there is no shift in the photocharge accumulation time between the two imaging regions in the vertical direction.
[0042]
Further, in the present embodiment, when signals stored in the line memory are read, signals are output alternately for each pixel from different imaging areas, so that processing in the subsequent processing circuit is facilitated. In each of the embodiments of the present invention described above, the case where the imaging regions 901 to 904 are arranged in a so-called Bayer array has been described as an example. However, the position where the color filter is provided may be another array, or may be a complementary color filter. Also good.
[0043]
The number of vertical shift registers 906a and the like and horizontal shift registers 911a and the like is not limited to the case shown in FIGS. 1 and 3, and for example, four may be provided for each of the imaging regions 901 to 904, and the positions to be provided. For example, it is good also as between each imaging region 901-904.
[0044]
4 to 7 are diagrams showing examples of arrangement of the vertical shift register 906a and the like and the horizontal shift register 911a and the like with respect to the respective imaging regions 901 to 904. The solid-state imaging devices shown in FIGS. 4 to 7 are processing circuits that simultaneously process charges and the like from the pixels 905 in the same row and the same column in each imaging region 901 to 904, for example, in any order described in the first and second embodiments. Output to the.
[0045]
In FIG. 4, four vertical shift registers 906c to 906f and horizontal shift registers 911c to 911f are provided, and the vertical shift registers 906c to 906f are arranged on the left side of the imaging regions 901 to 904. A state in which the horizontal shift registers 911c to 911f are arranged on the lower side is illustrated.
[0046]
The solid-state imaging device shown in FIG. 4 is provided with vertical shift registers 906c to 906f and horizontal shift registers 911c to 911f for the imaging regions 901 to 904, respectively. The charge or the like can be simultaneously output from the pixel 905 to the processing circuit.
[0047]
In FIG. 5, vertical shift registers 906 c to 906 f and horizontal shift registers 911 c to 911 f are arranged so as to surround the imaging regions 901 to 904. Arrangement It shows how this was done.
[0048]
The solid-state imaging device shown in FIG. 5 is provided with vertical shift registers 906c to 906f and horizontal shift registers 911c to 911f for the imaging regions 901 to 904, respectively, similarly to the one shown in FIG. In addition, charges and the like can be simultaneously output from the pixels 905 in the same row and column in each of the imaging regions 901 to 904 to the processing circuit.
[0049]
In FIG. 6, four vertical shift registers 906c to 906f and the like and two horizontal shift registers 911e and 911f are provided. A state of being arranged between the area 902 and the B imaging area 904 is illustrated.
[0050]
Since the solid-state imaging device shown in FIG. 6 is provided with the horizontal shift registers 911e and 911f in common, charges and the like are simultaneously output from the pixels 905 to the processing circuit in the same order as shown in FIG. To be able to.
[0051]
In FIG. 7, the vertical shift registers 906e and 911f are arranged between the R imaging area 901 and the G1 imaging area 902 and between the G2 imaging area 903 and the B imaging area 904, respectively, and the horizontal shift registers 911e and 911f are arranged. Are shown between the R imaging area 901 and the G2 imaging area 903 and between the G1 imaging area 902 and the B imaging area 904, respectively.
[0052]
In the solid-state imaging device shown in FIG. 7, since the vertical shift registers 906e and 911f and the horizontal shift registers 911e and 911f are provided in common, the pixels 905 are arranged in the same order as shown in FIG. At the same time, charges or the like can be output to the processing circuit.
[0053]
(Embodiment 3)
FIG. 8 is a configuration diagram of an imaging apparatus using the solid-state imaging device described in the first and second embodiments. In FIG. 8, 1 is a barrier that serves as a lens protect and a main switch, and 2 is a lens that forms an optical image of the subject on the solid-state imaging device 4, and divides the subject image into a plurality of images as shown in FIG. Thus, it plays a role of forming an image on each imaging region described in the first or second embodiment. 3 is a diaphragm for varying the amount of light passing through the lens, 4 is a solid-state image sensor described in the first or second embodiment for capturing the subject imaged by the lens 2 as an image signal, and 5 is a solid-state image sensor. An image signal processing circuit that performs various corrections, clamps, and the like on the image signal output from 4, 6 an A / D converter that performs analog-digital conversion of the image signal output from the solid-state image sensor 4, and 7 A signal processing unit 8 performs various corrections on the image data output from the A / D converter 6, compresses the data, and synthesizes the image data from each imaging region. A timing generation unit which is a driving means for outputting various timing signals to the signal processing circuit 5, the A / D converter 6, and the signal processing unit 7, 9 is an overall control / calculation unit for controlling various calculations and the entire still video camera, 0 is a memory unit for temporarily storing image data, 11 is a recording medium control interface unit for performing recording or reading on a recording medium, and 12 is a semiconductor memory or the like for recording or reading image data. A possible recording medium 13 is an external interface (I / F) unit for communicating with an external computer or the like.
[0054]
Next, the operation of FIG. 8 will be described. When the barrier 1 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the diaphragm 3, and the signal output from the solid-state imaging device 4 passes through the imaging signal processing circuit 5 to the A / D converter 6. Is output. The A / D converter 6 performs A / D conversion on the signal and outputs it to the signal processing unit 7. The signal processing unit 7 performs an exposure calculation by the overall control / calculation unit 9 based on the data.
[0055]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, a high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not it is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
[0056]
Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is corrected in the imaging signal processing circuit 5, further A / D converted by the A / D converter 6, and totally controlled through the signal processing unit 7. Accumulated in the memory unit 10 by calculation 9 Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 13.
[0057]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the shift of the photocharge accumulation time between the imaging regions and to form a good image.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a configuration of a solid-state imaging element according to a first embodiment of the present invention.
2 is a circuit diagram of a pixel, a pulse signal output circuit, and a line memory in FIG. 1. FIG.
FIG. 3 is a schematic diagram illustrating a configuration of a solid-state imaging element according to a second embodiment of the present invention.
FIG. 4 is a schematic diagram illustrating a configuration example of another solid-state imaging device.
FIG. 5 is a schematic diagram illustrating a configuration example of another solid-state imaging device.
FIG. 6 is a schematic diagram illustrating a configuration example of another solid-state imaging device.
FIG. 7 is a schematic diagram illustrating a configuration example of another solid-state imaging device.
FIG. 8 is a configuration diagram of an imaging apparatus according to a third embodiment of the present invention.
FIG. 9 is a detailed view of a part of the imaging apparatus of FIG.
FIG. 10 is a schematic diagram showing a configuration of a conventional solid-state imaging device.
FIG. 11 is a diagram showing a part of a conventional solid-state image sensor.
[Explanation of symbols]
1 Barrier
2 Lens
3 Aperture
4 Solid-state image sensor
5 Imaging signal processing circuit
6 A / D converter
7 Signal processor
8 Timing generator
9 Overall control / calculation unit
10 Memory part
11 Recording medium control interface (I / F) section
12 Recording media
13 External interface (I / F) section
901 R imaging area
902 G1 imaging area
903 G2 imaging area
904 B imaging area
905 pixels
906a to 906d vertical shift register
907 pulse signal output circuit
909 Horizontal signal line
910, 910a, 910b line memory
911a to 911d horizontal shift register
912 Vertical signal line
913 amplifier
914 output terminal
921 Photodiode
922 Transfer switch
923 MOS transistor
924 Reset switch
925 selection switch

Claims (4)

A first pixel region that outputs a signal of a first color component and in which a plurality of pixels are arranged two-dimensionally in a horizontal direction and a vertical direction;
A second pixel region that outputs a signal of a second color component and that is arranged in a two-dimensional manner in a horizontal direction and a vertical direction, and that is provided in a direction perpendicular to the first pixel region When,
A plurality of first output lines provided one by one in common for the plurality of pixels in the vertical direction of the first pixel region and the plurality of pixels in the vertical direction of the second pixel region;
An output unit that is provided in common to the first pixel region and the second pixel region, and that sequentially outputs signals from the plurality of output lines;
On the same semiconductor chip,
After the first line signal of the first pixel region is read to the output unit, the first line signal of the second pixel region is read to the output unit, and then the first pixel region 2 of the first pixel region is read. After reading the signal of the line to the output unit, the first pixel region and the second pixel region so as to read the signal of the second line of the second pixel region to the output unit, An image pickup apparatus that is driven to alternately read out signals to the output unit for each line . The imaging device according to claim 1,
Furthermore, on the same semiconductor chip,
A plurality of pixels that output a signal of a third color component, arranged in a two-dimensional manner in a horizontal direction and a vertical direction, and a third pixel region provided in a horizontal direction with respect to the first pixel region; ,
A plurality of pixels that output the signal of the first color component are arranged two-dimensionally in a horizontal direction and a vertical direction, and the third pixel region is arranged in a horizontal direction with respect to the second pixel region. A fourth pixel region provided in a direction perpendicular to
A plurality of second output lines provided one by one in common to a plurality of pixels in the vertical direction of the third pixel region and a plurality of pixels in the vertical direction of the fourth pixel region;
Have
The output unit is further provided in common for the third pixel region and the fourth pixel region, and sequentially outputs signals from the plurality of first output lines and second output lines,
After reading the first line signal of the first pixel region and the third pixel region to the output unit, the first line signal of the second pixel region and the fourth pixel region is sent to the output unit. After reading, the second line signal of the first pixel area and the second pixel area is read to the output unit, and then the second line signal of the second pixel area and the fourth pixel area is read. As read to the output unit, signals are alternately read to the output unit for each line in the first pixel region, the third pixel region, the second pixel region, and the fourth pixel region. As well as driving
After reading the first pixel signal of the first line in the first pixel region, the first pixel signal of the first line in the third pixel region is read, and then the first pixel region The first pixel region and the second pixel are read so that the second pixel signal of the first line in the third pixel region is read after the second pixel signal of the first line is read out. Read signals to the output unit alternately for each pixel in the region,
After reading the first pixel signal of the first line of the second pixel region, the first pixel signal of the first line of the fourth pixel region is read, and then the second pixel region The second pixel region and the fourth pixel are read so that the second pixel signal of the first line of the fourth pixel region is read after the second pixel signal of the first line is read out. An image pickup apparatus that is driven so as to alternately read a signal to the output unit for each pixel in a region . The imaging apparatus according to claim 1 , further comprising: an optical system that focuses light on each imaging region; and a signal processing circuit that processes an output signal from each imaging region. . The imaging apparatus according to claim 3, wherein the optical system divides a subject image into a plurality of images and forms the images in respective imaging regions .

Images