JP3704976B2 - Liquid crystal display device and voltage correction circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a liquid crystal display. In particular, the present invention relates to a TFT liquid crystal display that realizes high-quality display using a low voltage driving circuit. The present invention also relates to the drive circuit.
[0002]
[Prior art]
  A conventional TFT liquid crystal display will be described with reference to FIGS.
  FIG. 2 is a block diagram of a conventional TFT liquid crystal display, and FIG. 3 is a drive waveform diagram of the conventional liquid crystal display.
[0003]
  In FIG. 2, 201 is an interface signal including display data and a synchronization signal transferred from a system (not shown). Reference numeral 202 denotes an interface circuit that generates display data and a control signal for driving a conventional liquid crystal display. A signal driving circuit 203 generates a gradation voltage corresponding to display data. Reference numeral 204 denotes a scan drive circuit that sequentially selects scan lines. Reference numeral 205 denotes a power supply circuit that generates a power supply necessary for the operation of each block. Reference numeral 206 denotes a liquid crystal panel, which performs display corresponding to display data input thereto.
[0004]
  Of the signals generated by the interface circuit 202, reference numeral 207 denotes a control signal for the signal driving circuit 203, which includes display data and a synchronization signal. Reference numeral 208 denotes a control signal for the scanning drive circuit 204, which transfers a timing signal for sequentially scanning the scanning lines. Reference numeral 209 denotes an alternating signal to be transferred to the power supply circuit 206.M 'It is.
[0005]
  Of the signals generated by the power supply circuit 205, reference numeral 210 denotes a gradation voltage signal to be transferred to the signal driving circuit 203, which transfers a voltage serving as a reference for the gradation voltage corresponding to display data to be transferred to the liquid crystal panel 206. Reference numeral 211 denotes a scanning voltage signal to be transferred to the scanning drive circuit 204, and reference numeral 212 denotes a counter electrode connected to the liquid crystal of the liquid crystal panel 206, which transfers the counter electrode voltage 'Vcom'. Reference numeral 213 denotes a signal line group for transferring a gradation voltage corresponding to display data generated by the signal drive circuit 203, and reference numeral 214 denotes a scan voltage for selecting and deselecting the scan line generated by the scan drive circuit 204. This is a scanning line group to be transferred. Reference numeral 215 denotes a pixel portion constituting the liquid crystal panel 205, which is formed at the intersection of the signal line group 213 and the scanning line group 214, so that the liquid crystal panel 205 has a matrix structure. The pixel portion 215 has a number corresponding to the resolution in the horizontal direction and the vertical direction. In general, in the case of a liquid crystal display for color display, when one pixel is composed of three primary colors of red, green, and blue and each color pixel portion is arranged in the horizontal direction, the number of pixels in the horizontal direction is three times the resolution. It becomes the number of. The pixel units 215 arranged in the horizontal direction share one scanning line in the scanning line group 214, and the pixel units 215 arranged in the vertical direction share one signal line in the signal line group 213. Is common. In the pixel portion 215, reference numeral 216 denotes a thin film transistor (hereinafter referred to as TFT) which is a switching element, 217 denotes a liquid crystal, 218 denotes a compensation capacitor, and 219 denotes a source electrode. 220 is a gate formed between a scanning line (also referred to as a gate line) 214 and a source electrode.−This is the parasitic capacitance between sources.
[0006]
  In FIG. 3, Vg (n) and Vg (n + 1) are driving waveforms of scanning lines for driving the nth and n + 1th lines in the scanning line group 214 shown in FIG. 2, respectively, and Vgon is a selection voltage. Vgoff indicates a non-selection voltage level. Vcom is an ideal drive waveform of the counter electrode 212, VcomH is a high potential voltage level, and VcomL is a low potential voltage level. Vd indicates the gradation voltage of the signal line group 213, and when it is on the negative polarity side with respect to the counter electrode voltage Vcom, a negative voltage is applied to the pixel 215 and it is on the positive polarity side. In this case, a positive voltage is applied to the pixel 215. The liquid crystal display operates such that the potential difference between the counter electrode voltage Vcom and the gradation voltage Vd becomes an effective voltage value applied to the liquid crystal 217, and the luminance changes. In this conventional example, when the potential difference from the counter electrode voltage Vcom is small, dark display (example: black display) is performed, and when the potential difference from the counter electrode voltage Vcom is large, light display (example: white display) is described. I do. In FIG. 3, the drain voltage Vd is a gradation voltage for performing white display, VdWH is a positive white display drain voltage, VdWL is a negative white display drain voltage, and the drain voltage with respect to the counter electrode voltage Vcom. Is on the negative side, the effective voltage value Vrms1 is applied, and when the drain voltage is on the positive side, the effective voltage value Vrms2 is applied.
[0007]
  Again, the operation of the conventional liquid crystal display will be described in detail with reference to FIG.
  Display data and a synchronization signal transferred by the interface signal 201 are input by the interface circuit 202. The interface circuit 202 supplies a control signal 207 to the signal drive circuit 203, a control signal 208 to the scan drive circuit 204, and a power supply. A liquid crystal alternating current signal M ′ 209 is generated and output to the circuit 205. The signal driving circuit 203 sequentially captures display data for one horizontal line using the display data and the synchronization signal transferred by the control signal 207, and when the display data for one horizontal line has been captured, The gradation voltage corresponding to the display data of the minute is simultaneously output from the signal line group 213. The signal driving circuit 203 continues to output the gradation voltage for one horizontal line during one horizontal period. At this time, the signal driving circuit 203 performs in parallel the operation of sequentially fetching the display data of the next horizontal line.
[0008]
  Therefore, the display data output from the interface circuit 202 is output as a gradation voltage to the liquid crystal panel 206 during the next horizontal period. The signal driving circuit 203 repeats this operation and outputs a gradation voltage corresponding to display data for one frame, that is, one screen, to the liquid crystal panel 206. The gradation voltage output from the signal driver circuit 203 is generated with reference to the gradation voltage transferred by the gradation voltage line 210. In general, the reference voltage of the gradation voltage transferred by the gradation voltage line 210 is a voltage of a plurality of levels from a black display voltage to a white display voltage. In the scanning drive circuit 204, a selection voltage is sequentially applied from the first line to the scanning line 214 in synchronization with the control signal 208. At this time, the TFT 216 of each pixel portion 215 is in a selected state when a selection voltage is applied, and applies the gradation voltage transferred from the signal line group 213 to the liquid crystal 217 and the compensation capacitor 218. Then, when a non-selection voltage is applied to the scanning line 214, the scanning line 214 is held until it is next selected. In this way, the liquid crystal display performs gradation control by performing line-sequential scanning control and controlling the amount of light transmitted at the voltage level of the voltage effective value applied to the liquid crystal 217.
[0009]
  The operation of applying a voltage to the liquid crystal 217 of the pixel portion 215 will be described in more detail with reference to FIG. As shown in FIG. 3, when the selection voltage Vgon is applied to the scanning line G (n), the TFT 216 shown in FIG. 2 is turned on, and the drain (grayscale) voltage Vd transferred through the signal line 213 is first described. As described above, when the non-selection voltage Vgoff is applied to the liquid crystal 217 of the pixel portion 215 and the scanning line G (n) is applied, the TFT 216 is turned off at this timing, and the voltage is held. At the timing when the selection voltage Vgon is applied to the scanning line G (n), since the voltage level of the counter electrode 212 is the low potential voltage VcomL (negative polarity), the voltage applied to the liquid crystal becomes a positive voltage (white display) The drain voltage is VdWH.) Similarly, at the timing when the selection voltage Vgon is applied to the scanning line G (n + 1), since the voltage level of the counter electrode 212 is the high potential voltage VcomH (positive polarity), the voltage applied to the liquid crystal is a negative polarity voltage. (White display drain voltage is VdWL.)
[0010]
  In general, it is necessary to apply an AC voltage to the liquid crystal at a cycle of about one frame (about 60 Hz). Therefore, in the line corresponding to each scanning line group 214, the voltage applied earlier is applied at the next voltage application timing. It is necessary to apply a reverse polarity voltage. Further, when the polarity of the gradation voltage applied to the entire screen is shifted to one side, a flicker phenomenon called flicker occurs. Therefore, in this conventional example, alternating drive for each line is realized so that positive and negative gradation voltages are applied to each line. Therefore, the voltage level of the counter electrode 212 is alternating between the high potential voltage VcomH (positive polarity) and the low potential voltage VcomL (negative polarity) for each line.
[0011]
  A feature of this conventional driving method is that, in general, when applying positive and negative gray scale voltages to a liquid crystal, a signal drive circuit having a dynamic range twice the gray scale voltage Vd shown in FIG. 3 is required. The counter electrode 212 is opposed toelectrodeSince the voltage Vcom is converted into an alternating current, the signal drive circuit 203 can have a dynamic range shown in FIG. 3, that is, a signal drive circuit 203 having a withstand voltage capable of generating a gradation voltage of one polarity.
[0012]
[Problems to be solved by the invention]
  The problem of the conventional liquid crystal display will be described with reference to FIGS. FIG. 4 is a drive waveform diagram of each part when white display is performed on a conventional liquid crystal display. FIG. 5 is a drive waveform diagram of each part when black display is performed on a conventional liquid crystal display. FIG. 6 is an example of a display screen when displayed on a conventional liquid crystal display. FIG. 7 is a drive waveform diagram when the display screen example shown in FIG. 6 is displayed on a conventional liquid crystal display.
[0013]
  In FIG. 4, FIG. 4 describes the operation of applying a white display voltage, (a) is an example in which a negative gradation voltage is applied, and (b) is a positive gradation voltage. It is an applied example. Vg in FIG. 4A is a voltage waveform applied to the scanning line, Vgon is a selection voltage level, and Vgoff is a non-selection voltage level. Vd is a gradation voltage waveform applied to the signal line, VdWH is a positive white display voltage, and VdWL is a negative white display voltage. Vcom1 is a counter electrode voltage waveform input to the liquid crystal panel 206, and Vcom2 is a counter electrode voltage waveform inside the liquid crystal panel 206. Vs is a source voltage waveform of the source electrode 219 of the pixel portion 215 inside the liquid crystal panel 206. The same applies to FIG.
[0014]
  FIG. 5 describes the operation of applying a black display voltage, (a) is an example in which a negative gradation voltage is applied, and (b) is an example in which a positive gradation voltage is applied. It is. Vd in FIG. 5A is a gradation voltage waveform applied to the signal line, VdBH is a positive black display voltage, and VdBL is a negative black display voltage. The other waveforms are the same as the drive voltage described in FIG. The same applies to FIG. 5B.
[0015]
  FIG. 6 shows an example in which intermediate luminance is displayed on the entire screen and a white rectangular shape is displayed at the center. This shows a phenomenon in which the luminance of the intermediate luminance display area (A) in the area not displaying the white rectangle and the luminance of the white rectangular right and left display areas (B) are different. This is a conventional liquid crystal display that is applied to the counter electrode.electrodeThis is image quality deterioration called lateral smear that occurs in the case of low-voltage driving in which the voltage is changed to AC.
[0016]
  FIG. 7 shows the drive waveform of each part in the display example shown in FIG. 6, and FIG. 7 (a) is a drive waveform diagram of the halftone display area (A) shown in FIG. FIG. 7B is a drive waveform diagram of the halftone display area (B) shown in FIG. 6. In this conventional example, an example in which a negative gradation voltage is applied is described. In FIG. 7A, Vd is a voltage waveform for intermediate luminance display, VdGH is a positive intermediate luminance display voltage, and VdGL is a negative intermediate luminance display voltage. The other waveforms are the same as the drive voltage described in FIG. The same applies to FIG. 7B.
[0017]
  The generation mechanism of the horizontal smear in which the luminance change occurs in the left and right areas of the white rectangular display area as shown in FIG. 6 will be described in detail.
[0018]
  Opposing to the counter electrodeelectrodeIn the case of low-voltage drive that converts the voltage to alternating current, the counter electrode is common to all pixel units, soelectrodeWhen the voltage is a high potential voltage (positive polarity), the negative gradation voltage is applied to all the pixel portions on the line where the gradation voltage is written. Also oppositeelectrodeWhen the voltage is a low potential voltage (negative polarity), a positive polarity voltage is applied to all the pixel portions on the line where the gradation voltage is written. Therefore, current concentration occurs such that the current of all the pixel portions flows into and out of the counter electrode in one direction via the liquid crystal 217 and the compensation capacitor 218 of the pixel portion 215. At this time, the influence of the time constant of the counter electrode occurs,electrodeThe voltage is distorted. FIG. 4 and FIG. 5 show this state.
[0019]
  4 and 5, each pixel portion 215 of the liquid crystal panel 205 has a gate as shown in FIG.−There is a parasitic capacitance 220 between the sources. The parasitic capacitance 220 is caused by the TFT 216, and the insulating film of the TFT 216 and silicon (both not shown) are involved. When the scanning line transitions from the selected state to the non-selected state, the TFT 216 is changed from the “on” state to the “off” state. Therefore, the voltage is also distributed to the parasitic capacitance 220.
[0020]
  Assuming that the parasitic capacitance 220 is Cgs, the equivalent capacitance of the liquid crystal 217 is Clc, the compensation capacitance 218 is Cstg, and the scanning line selection voltage is Vgon, (Equation 1) is obtained.
[0021]
[Expression 1]
  ΔVgs = (Cgs / (Cgs + Ccl + Cstg)) × Vgon (Equation 1)
  Therefore, the voltage applied to the liquid crystal 217 is dropped by the voltage moved to the parasitic capacitance 220. As a result, the counter applied to the counter electrodeelectrodeThe voltage Vcom1 needs to be shifted to a low potential level in advance due to the influence of the parasitic capacitance 220.
[0022]
  Next, the operation of each voltage waveform will be described over time. When the negative white display voltage VdWL shown in FIG. 4A is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the voltage level of the drain voltage Vd of the previous line during the 'T1' period. (Shifts to high potential). After that, when the counter electrode voltage is changed to AC in the “T2” period, the change of the counter electrode voltage is steeper than the writing speed of the TFT 216. Therefore, the potential of the source voltage Vs is shown in FIG. As shown, it shifts to a high potential according to the counter electrode voltage being changed to AC. After that, the source voltage Vs transitions to the potential of the drain voltage Vs in the periods “T3” and “T4”. However, in the period “T3”, the source voltage Vs is in a higher potential state than the counter electrode voltage Vcom2 in the liquid crystal panel 206. In the 'T4' period, the source voltage Vs is in a lower potential state than the counter electrode voltage Vcom2 inside the liquid crystal panel 206. In this operation, since the source voltage potential is located at a considerably high potential with respect to the counter electrode voltage potential, the voltage distortion of the counter electrode voltage becomes large, and the convergence rate is slowed down. Therefore, the potential difference between the source voltage Vs and the counter electrode voltage Vcom2 becomes the effective voltage value VrmsWL1 applied to the liquid crystal 217 at the timing when the 'T4' period ends, that is, the timing when the non-selection voltage Vgoff is applied to the scanning line. In this conventional example, since the counter electrode voltage Vcom2 inside the liquid crystal panel 206 does not reach the desired counter electrode voltage Vcom1, a potential difference of ΔVcomH occurs, which becomes an insufficient effective voltage value. Further, when the TFT 216 transitions to the “off” state, the phenomenon of voltage jumping to the parasitic capacitance 220 described above occurs. This jump voltage level is ΔVgsWL. Therefore, as a result, the effective voltage value applied to the liquid crystal 217 is −VrmsWL2 (= −VrmsWL1−ΔVgsWH). As described above, since the counter voltage Vcom2 in the liquid crystal panel 206 is deficient in ΔVcomH relative to the desired counter electrode voltage Vcom1 as described above, the effective voltage value corresponding to ΔVcomH is insufficient. It has occurred.
[0023]
  Similarly, when the positive white display voltage VdWH shown in FIG. 4B is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the drain voltage Vd of the previous line during the period 'T1'. Transition to the voltage level (shifted to a higher potential). Thereafter, the counter electrode voltage is changed to an alternating current in the period “T2”, and transits to a low potential voltage. Since the change in the counter electrode voltage is steeper than the writing speed of the TFT 216, the potential of the source voltage Vs shifts to a low potential in accordance with the AC conversion of the counter electrode voltage as shown in FIG. 4B. . Thereafter, the source voltage Vs transitions to the potential of the drain voltage Vs in the periods “T3” and “T4”. However, in the period “T3”, the source voltage Vs is in a lower potential state than the counter electrode voltage Vcom2 in the liquid crystal panel 206. In the 'T4' period, the source voltage Vs is in a higher potential state than the counter electrode voltage Vcom2 inside the liquid crystal panel 206. In this operation, the potential difference between the counter electrode voltage and the drain voltage is larger than when the negative gradation voltage described in FIG. 4A described above is applied. Accordingly, since the amount of write voltage in the “T4” period increases, the counter electrode voltage Vcom2 does not reach the desired counter electrode voltage Vcom1, and a potential difference of ΔVcomL is generated. Therefore, the effective voltage value applied to the liquid crystal 217 is VrmsWH1, and an insufficient effective voltage value of ΔVcomL has occurred. Further, when the TFT 216 transitions to the “off” state, a voltage jump occurs due to the influence of the parasitic capacitance 220 described above. This jump voltage level is ΔVgsWH. Therefore, as a result, the effective voltage value applied to the liquid crystal 217 is VrmsWH2 (= VrmsWH1-ΔVgsWL), and an effective voltage value shortage corresponding to ΔVcomL due to insufficient convergence of the counter electrode voltage Vcom2 occurs. .
[0024]
  Next, the manner in which the black display voltage is applied will be described with reference to FIG. When the negative black display voltage VdBL shown in FIG. 5A is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the voltage level of the drain voltage Vd of the previous line in the 'T1' period. (Shifts to high potential). Thereafter, the counter electrode voltage is converted into an alternating current during the period “T2”, and is shifted to a high potential in accordance with the AC conversion of the counter electrode voltage as shown in FIG. Thereafter, in the “T3” period, the source voltage Vs transitions to the potential of the drain voltage Vs, and in the “T4” period, the source voltage Vs is stabilized. The effective voltage value applied to the liquid crystal 217 at that time is VrmsBL1. Here, in consideration of the jump voltage ΔVgsBL, the effective voltage value applied to the liquid crystal 217 in the holding state is −VrmsBL2 (= VrmsBL1−ΔVgsBL). That is, since the counter electrode voltage Vcom1 is shifted to the low potential side, when the TFT 216 is in the “on” state, the source voltage Vs is located on the positive side of the counter electrode voltages Vcom1 and Vcom2, but the TFT 216 is “ The transition to the OFF state and the occurrence of a jump voltage causes a change to a negative gradation voltage. Further, since the potential change of the source voltage Vs in the period “T2” is small compared to the application of the white display voltage shown in FIG. 4A, the counter electrode voltage Vcom2 is changed to the desired counter electrode voltage Vcom1. The convergence rate is improved, and the effective value fluctuation due to the insufficient convergence rate of the counter electrode voltage Vcom2 does not occur.
[0025]
  When VdBH is applied as the positive black display voltage shown in FIG. 5B, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the voltage of the drain voltage Vd of the previous line in the 'T1' period. Transition to level (shift to high potential). Thereafter, the counter electrode voltage is converted into an alternating current during the period “T2”, and is shifted to a low potential in accordance with the AC conversion of the counter electrode voltage as shown in FIG. Thereafter, in the period “T3” and “T4”, the source voltage Vs transitions to the potential of the drain voltage Vs, and the source voltage Vs becomes stable. Since the potential change between the source voltage Vs and the counter electrode voltage Vcom2 is smaller than when the white display voltage shown in FIG. 4B is applied, the amount of the write voltage is small and the counter electrode voltage Vcom2 is the desired counter electrode voltage. The convergence rate to Vcom1 is improved. Considering the jump voltage, if the effective voltage value applied to the liquid crystal 216 in the period “T4” is VrmsBH1, the effective voltage value in the holding state is VrmsBH2 (= VrmsBH1−ΔVgsBH), but FIG. As with the description of), the effective value fluctuation due to the lack of convergence of the counter electrode voltage Vcom2 does not occur.
[0026]
  As described above, in a state where the potential difference between the counter electrode voltage Vcom and the drain voltage Vd is large, the voltage distortion of the counter electrode voltage Vcom increases, and the effective voltage value to the liquid crystal 217 is insufficient. In addition, in a state where the potential difference between the counter electrode voltage Vcom and the drain voltage Vd is small, the voltage distortion of the counter electrode voltage Vcom is small, and an insufficient effective voltage value to the liquid crystal 217 does not occur.
[0027]
  Next, considering the voltage application state in the white display and the voltage application state in the black display, the image quality deterioration factor shown in FIG. 6 will be described with reference to FIG.
[0028]
  In the line of the area (A) shown in FIG. 6, the white display data is included in the display data in the horizontal direction.electrodeThe voltage waveform Vcom2 is a voltage waveform as shown in FIG. That is, voltage variation of the counter electrode voltage Vcom2 due to white display occurs, and a voltage shortage of ΔVcomGH occurs with respect to the desired counter electrode voltage Vcom1.
[0029]
  Similarly, in the line of the area (B) shown in FIG. 6, since all horizontal display data is halftone display data,electrodeThe voltage waveform Vcom2 is a voltage waveform as shown in FIG. That is, the counter electrode voltage Vcom2 reaches the desired counter electrode voltage Vcom1. Therefore, even in the same intermediate luminance display, the effective voltage value applied to the liquid crystal 217 in the hold state differs by ΔVcomGH, and the effective voltage value is insufficient. Therefore, the horizontal display data includes white display data. The intermediate brightness of the line is dark. Therefore, the effective voltage difference corresponding to the insufficient convergence of the counter electrode voltage can be identified to the human eye as a luminance change, and appears as a lateral smear.
[0030]
[Means for Solving the Problems]
  An object of the present invention is to provide a liquid crystal display device that realizes high quality display using a low voltage signal driving circuit.
[0031]
  The present invention has been made to achieve the above object, and as its first form,Composed of thin film transistorsA liquid crystal panel having M pixel units each including a switching element and a liquid crystal in the horizontal direction and N pixels in the vertical direction and display data are input, and a gradation voltage corresponding to the input display data is generated. Select one of the signal driving circuit to be applied to the corresponding pixel portion in the horizontal direction of display data and the pixel portion arranged in the vertical direction, and the pixel portion arranged in the vertical direction selected at that time The pixel portions arranged in the vertical direction, to which the selection voltage is applied, are arranged at the same time, and are provided with a scanning drive circuit for applying the non-selection voltage, and the liquid crystal is commonly opposed to each of the pixel portions. When a selection voltage output to the scanning drive circuit is applied to the switching element of the pixel portion, the gradation voltage generated by the signal drive circuit is applied to the liquid crystal and The floor In a liquid crystal display that controls display brightness with an effective voltage value of voltage, a circuit that detects a data amount of the input display data and a counter electrode voltage value that is applied to the counter electrode according to the detected display data amount It has a power supply circuit for adding / subtracting the correction voltage value.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
  An embodiment of the liquid crystal display of the present invention will be described with reference to FIGS. 1 and 8 to 13.
  FIG. 1 is a block diagram of a liquid crystal display of the present invention. FIG. 8 shows an AC signal generation circuit and a correction period signal generation circuit in the interface circuit of the present invention. FIG. 9 is a timing chart illustrating the operation of the AC signal generation circuit and the correction period signal generation circuit shown in FIG. Figure 10 shows the oppositeelectrodeIt is a voltage Vcom generation circuit. Figure 11 shows the oppositeelectrodeOpposite generated by the voltage Vcom generation circuitelectrodeIt is a timing chart figure explaining operation of voltage Vcom. 12 and 13 are drive waveform diagrams for explaining the operation of the present invention.
[0033]
  In FIG. 1, reference numeral 101 denotes an interface signal including display data and a synchronization signal transferred from a system (not shown). An interface circuit 102 generates display data and control signals for driving the liquid crystal display of the present invention. Reference numeral 103 denotes a signal driving circuit that generates a gradation voltage corresponding to display data. Reference numeral 104 denotes a scan drive circuit, which sequentially selects scan lines. Reference numeral 105 denotes a power supply circuit. Reference numeral 106 denotes a liquid crystal panel on which display corresponding to display data is made.
[0034]
  Of the control signals generated by the interface circuit 102, 107 is a control signal for the signal driving circuit 103, and includes display data and control signals. Reference numeral 108 denotes a control signal for the scan driving circuit 104, which transfers a timing signal for sequentially selecting scan lines. 109 is an AC signal M ′ to be transferred to the power supply circuit 106, and 110 and 111 are control signals to transfer a correction period signal indicating a period during which the correction voltage is applied.
[0035]
  Among the voltage signals generated by the power supply circuit 106, 112 is a gradation voltage signal to be transferred to the signal driving circuit 103, and transfers a voltage serving as a reference for the gradation voltage corresponding to the display data to be transferred to the liquid crystal panel 106. . A scanning voltage signal 113 is transferred to the scanning drive circuit 104, and a counter electrode 114 is connected to the liquid crystal 105. Reference numeral 115 denotes a signal line group for transferring a gradation voltage corresponding to display data. Reference numeral 116 denotes a scanning line group for transferring a scanning voltage for selecting and deselecting the scanning line. Reference numeral 117 denotes a pixel portion constituting the liquid crystal panel 105, which is formed at the intersection of the signal line group 115 and the scanning line group 116, so that the liquid crystal panel 105 has a matrix structure. In the pixel portion 115, 118 is a thin film transistor (hereinafter referred to as TFT) which is a switching element, 119 is a liquid crystal, 120 is a compensation capacitor, and 121 is a source electrode. And 122 is a gate formed between a scanning line (also referred to as a gate line) 116 and a source electrode.−This is the parasitic capacitance between sources. Reference numeral 123 denotes a setting circuit for setting a period during which the correction voltage is applied, and reference numeral 124 denotes a setting signal output from the setting circuit 123.
[0036]
  In FIG. 8, reference numeral 801 denotes a vertical synchronization signal VSYNC, which is a signal that becomes effective once per frame. Reference numeral 802 denotes a horizontal synchronization signal HSYNC, which is a signal that becomes effective once per horizontal period. Reference numeral 803 denotes a dot clock DotCLK, which has an operating frequency synchronized with display data. 804 is oppositeelectrodeThis is a signal PBST for setting a correction voltage period that is effective when the voltage Vcom is positive.electrodeThe signal NBST sets a correction voltage period that is effective when the voltage Vcom is negative.
[0037]
  811 is an AC signalM 'This is a signal for applying a positive gradation voltage and a negative gradation voltage to the liquid crystal panel 106, and is inverted every horizontal period. 828 is oppositeelectrodeThis is a signal PBSTSET that sets a correction voltage period that is effective when the voltage Vcom is positive.electrodeThe signal NBTSSET sets a correction voltage period that is effective when the voltage Vcom is negative.
[0038]
  Reference numerals 806 and 808 denote flip-flops, each of which has a function of dividing the vertical synchronizing signal 801 and the horizontal synchronizing signal 802, and generates divided signals 807 and 809, respectively. Reference numeral 810 denotes an exclusive logical OR circuit. A counter 812 is reset by a horizontal synchronization signal 802 and counts up in synchronization with the dot clock 803. 813 is an output signal of the counter 812, 814 and 815 are decode circuits for decoding the set values of the PBSTSET 804 and NBTSSET 805, respectively, and 815 and 816 are output signals of the respective decode circuits. Reference numerals 818 and 820 denote comparison circuits, which generate valid pulses when the count value output from the counter 812 matches the decode value output from the decode circuits 814 and 816. Reference numerals 819 and 821 denote output signals for transferring valid pulses generated by the comparison circuits 818 and 820, respectively. 822 and 824 are JK flip-flops, which are set when the horizontal synchronizing signal 802 becomes valid, and reset when a valid pulse is output to the output signals 819 and 821. Reference numerals 823 and 825 denote output signals from the JK flip-flops 822 and 824. 827 and 829 are AND circuits, which are gated with the AC signal 811 to generate control signals for the PBST 828 and the NBST 830.
[0039]
  FIG. 9 is a timing chart showing the operation of the circuit for generating each timing signal shown in FIG.
[0040]
  In FIG. 10, reference numeral 1001 denotes a capacitor for enabling only the AC component of the AC signal M ′ and cutting the DC component, 1002 is a resistor for receiving the output, and 1003 is an AC signal from which the DC component is cut. Reference numeral 1004 denotes a capacitor used for the feedback system of the buffer amplifier 1003, and reference numerals 1005 and 1006 denote diodes used for the feedback system of the buffer amplifier 1003, respectively. Reference numeral 1007 denotes a resistor that determines the output current value of the buffer amplifier. Reference numerals 1008 and 1009 denote dividing resistors for generating a reference voltage. Reference numeral 1010 denotes a buffer amplifier for counter electrode voltage AC conversion.electrodeA resistor and a volume resistor for setting a reference voltage of the voltage Vcom. A current value is determined by a resistor 1014 provided at the output of the volume resistor. Reference numerals 1015 and 1016 denote buffer transistors for amplifying the current of the buffer amplifier 1010. Reference numerals 1017 and 1018 denote resistors provided in the feedback system of the buffer amplifier 1010 and the buffer transistors 1015 and 1016, respectively. 1019 is oppositeelectrodeA capacitor for enabling only the AC component of the voltage Vcom correction voltage period signal 'PBST' and cutting the DC component, 1020 is a resistor for receiving the output, 1021 is a diode, and 1022 is a transistor that performs a switching operation. 1023 is a resistor. When PBST is at a “High” level, the transistor 1022 is in an “ON” state, and performs an operation of drawing a feedback system current of the buffer amplifier 1010 and the buffer transistors 1015 and 1016.
[0041]
  1024 is oppositeelectrodeA capacitor for enabling only the AC component of the voltage Vcom correction voltage period signal 'NBST' and cutting the DC component, 1025 is a resistor that receives the output, 1026 is a diode, and 1027 is a transistor that performs a switching operation. 1028 is a resistor. When NBST is at the “High” level, the transistor 1027 is in the “ON” state, and the operation of drawing in the feedback system current of the buffer amplifier 1010 and the buffer transistors 1015 and 1016 is performed.
[0042]
  In FIG. 11, Vcom is a counter applied to the counter electrode using the embodiment of the present invention.electrodeThis is a voltage, and shows how a correction voltage is applied when the correction period signals “PBST” and “NBST” are at a “High” level. When the counter electrode voltage Vcom transitions to a high potential voltage, it becomes a high potential level by ΔVcomH with respect to VcomH which is a predetermined counter electrode voltage level. In addition, when the counter electrode voltage Vcom transitions to the low potential voltage, the voltage level becomes a high potential level by ΔVcomL with respect to the predetermined counter electrode voltage level VcomL.
[0043]
  In FIG. 12, FIG. 12 describes the operation of applying the white display voltage according to this embodiment, (a) is an example in which a negative gradation voltage is applied, and (b) is a positive polarity. This is an example in which a gradation voltage is applied. Vg in FIG. 12A is a voltage waveform applied to the scanning line, Vgon is a selection voltage level, and Vgoff is a non-selection voltage level. Vd is a gradation voltage waveform applied to the signal line, VdWH is a positive white display voltage, and VdWL is a negative white display voltage. Vcom1 is a counter electrode voltage waveform input to the liquid crystal panel 206, and Vcom2 is a counter electrode voltage waveform inside the liquid crystal panel 206. VcomHB is obtained by adding a correction voltage ΔVcomH to a normal positive polarity counter electrode voltage VcomH, and VcomLB is obtained by adding a correction voltage ΔVcomL to a normal negative polarity counter electrode voltage VcomL. Vs is a source voltage waveform of the source electrode 121 of the pixel unit 118 inside the liquid crystal panel 206. The same applies to FIG.
[0044]
  In FIG. 13, FIG. 13 describes the operation of applying the black display voltage according to this embodiment, (a) is an example in which a negative gradation voltage is applied, and (b) is a positive polarity. This is an example in which a gradation voltage is applied. Vd is a gradation voltage waveform applied to the signal line, VdBH is a positive black display voltage, and VdBL is a negative black display voltage. Others are the same as described in FIG.
[0045]
  Again, the detailed operation of the liquid crystal display according to the embodiment of the present invention will be described with reference to FIG.
[0046]
  Display data and a synchronization signal transferred by the interface signal 101 are input by the interface circuit 102, and the interface circuit 102 controls the signal drive circuit 103, the control signal 108 for controlling the scan drive circuit 104, and the power supply circuit 105. The liquid crystal alternating current signal 109 and the control signals 110 and 111 are controlled.
[0047]
  In the signal driving circuit 103, the display data for one horizontal line is sequentially fetched, and when the display data for one horizontal line is fetched, the gradation voltage corresponding to the fetched display data for one horizontal line is obtained from the signal line group 114. Output one horizontal line at the same time. The signal driving circuit 103 continues to output the gradation voltage for one horizontal line during one horizontal period. At this time, the signal driving circuit 103 performs in parallel the operation of sequentially fetching the display data of the next horizontal line. Therefore, the display data output from the interface circuit 102 is output as a gradation voltage to the liquid crystal panel 106 during the next horizontal period. The signal driving circuit 103 repeats this operation, and outputs a gradation voltage corresponding to display data for one frame, that is, one screen, to the liquid crystal panel 105. The gradation voltage output from the signal driver circuit 103 is generated with reference to the gradation voltage transferred by the gradation voltage line 111. In general, the reference voltage of the gray scale voltage transferred by the gray scale voltage line 111 is a multi-level voltage from a black display voltage to a white display voltage, and this embodiment is also described in the same manner. To do. In the scanning drive circuit 104, a selection voltage is sequentially applied from the first line to the scanning line 116 in synchronization with the control signal 108. At this time, the TFT 118 of each pixel unit 117 is in a selected state when a selection voltage is applied, and applies the gradation voltage transferred from the signal line group 115 to the liquid crystal 119 and the compensation capacitor 120. When a non-selection voltage is applied to the scanning line 116, the scanning line 116 is held until the next selection state. As described above, in the liquid crystal display, the pixel portion 117 is controlled in a line-sequential manner to scan the pixel portion 117, and the gray level display is realized by controlling the amount of light transmitted at the voltage level applied to the liquid crystal 119. are doing. The basic operation so far is the same as that of the conventional liquid crystal display (FIGS. 2 and 3).
[0048]
  The present invention is characterized in that a circuit for correcting the counter electrode voltage is added to the interface circuit 102 and the power supply circuit 106. That is, as shown in FIG. 8, the flip-flop 806 divides the vertical synchronizing signal to generate a divided signal 807 shown in the timing chart of FIG. Similarly, the flip-flop 808 divides the horizontal synchronizing signal to generate a divided signal 809 shown in the timing chart of FIG. An alternating signal M ′ is generated by inputting these two types of frequency-divided signals to the exclusive logical OR circuit 810.
[0049]
  The counter 812 is reset by the horizontal synchronization signal 802 and performs a count-up operation according to the input dot clock 803. In synchronization with this, the JK flip-flops 822 and 824 are set. The count value output from the counter 812 is compared with the value decoded by the PBSTSET 804 by the decoder circuit 814 and the value decoded by the NBSTS 805 by the decode circuit 816 by the comparison circuits 822 and 824, and the valid pulse is transferred to the signal lines 823 and 825. . The JK flip-flops 822 and 824 are reset when a valid pulse is input from the signal lines 823 and 825. Therefore, the period from the timing when the horizontal synchronization signal 802 is input to the timing when the effective pulse is valid for the signal lines 823 and 825 is the period during which the correction voltage is applied. Then, the AND circuits 827 and 829 perform mask processing. When the alternating signal 811 is positive, it is reflected in the PBST 828, and when the alternating signal 811 is negative, it is reflected in the NBST 830. This is shown in FIG. The compensation signal period setting signals PBSTSET 804 and NBTSSET 805 are both included in the signal 124 shown in FIG. 1, and the pulse width of the setting circuit 123 can be easily changed according to the load condition of the liquid crystal panel 106. .
[0050]
  Next, generation of the counter electrode voltage Vcom to which the correction voltage shown in FIG. 11 is added will be described with reference to FIG.
  When a positive voltage ('High' level voltage) is input to the liquid crystal alternating signal M ′, the DC component is cut by the capacitor 1001. Then, current flows through the capacitor 1004 and the resistor 1002, and the output of the buffer amplifier 1003 gradually decreases. When the potential difference between both ends of the capacitor 1004 exceeds the forward voltage of the diode 1006, the diode 1006 becomes conductive. The output voltage is a constant voltage value on the low potential side. Further, when a negative voltage (“Low” level voltage) is input to the liquid crystal alternating current signal M ′, the DC component is cut by the capacitor 1001. Then, a current flows in the opposite direction to the positive voltage ('High' level voltage) via the capacitor 1004 and the resistor 1002, the output of the buffer amplifier 1003 gradually increases, and the potential difference between both ends of the capacitor 1004 becomes the diode 1005. When the forward voltage is exceeded, the diode 1005 becomes conductive and the output voltage becomes a constant voltage value on the high potential side. By repeating the above, an AC voltage waveform is obtained at the output of the buffer amplifier 1003 using the reference voltage generated by the resistors 1008 and 1009 as the AC center voltage level. Further, this voltage waveform changes as a current value through the resistor 1007. The changed current value is input to the negative input terminal of the buffer amplifier 1010, amplified and output. In the negative input terminal portion of the buffer amplifier 1010, the amount of current flowing through the resistor 1007, the current flowing through the resistor 1014, and the current flowing through the resistors 1017 and 1018 coincide with each other based on the principle of the immediate short. Therefore, by controlling the current flowing through the feedback system of the buffer amplifier 1010 and the buffer transistors 1015 and 1016, the voltage value of the common electrode voltage Vcom can be controlled. That is, when the counter electrode voltage Vcom is positioned at the positive polarity (high potential) voltage level, the transistor 1022 is selected and the current flows through the resistor 1023 by setting the correction signal PBST to the “High” level voltage. become. At this time, since the current flowing through the resistor 1017 is separated into the current flowing through the resistor 1018 and the resistor 1023, the amount of current flowing through the resistor 1018 decreases. Therefore, the counter electrode voltage Vcom shifts the counter electrode voltage level to a high potential so as to allow more current to flow, whereby a correction voltage can be applied to the counter electrode voltage Vcom. Further, by setting the correction signal PBST1019 to the “Low” level voltage, the transistor 1022 is in a non-selected state, and no current flows through the resistor 1023. At this time, an operation for reducing the current flowing through the resistor 1018 occurs, and the counter electrode voltage Vcom shifts to a normal voltage level. The operation is also the same depending on the polarity of the correction signal NBST.
[0051]
  Next, the detailed operation inside the liquid crystal panel 106 of this embodiment will be described with reference to the drive waveform diagrams of FIGS.
[0052]
  The operation of each voltage waveform will be described over time. When the negative white display voltage VdWL shown in FIG. 12A is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the voltage level of the drain voltage Vd of the previous line in the 'T1' period. (Shifts to high potential). After that, when the counter electrode voltage is changed to AC in the period “T2”, the change of the counter electrode voltage is steeper than the writing speed of the TFT 118. Therefore, the potential of the source voltage Vs is as shown in FIG. As shown, it shifts to a high potential according to the counter electrode voltage being changed to AC. At this time, the voltage level of the counter electrode voltage Vcom is corrected to a high potential voltage level (VcomHB) in advance in order to correct distortion. After that, the source voltage Vs transitions to the potential of the drain voltage Vs in the periods “T3” and “T4”, but the source voltage Vs is in a higher potential state than the counter electrode voltage Vcom2 in the liquid crystal panel 106 in the “T3” period. In the 'T4' period, the source voltage Vs is in a lower potential state than the counter electrode voltage Vcom2 inside the liquid crystal panel 106. In this operation, the source voltage potential is located at a considerably higher potential than the counter electrode voltage potential. However, by adding a correction voltage to the counter electrode voltages Vcom1 and Vcom2, the amount of voltage distortion is reduced and the convergence rate is increased. Aim to improve the effect. Next, since the counter electrode voltages Vcom1 and Vcom2 transition to the normal counter electrode voltage level (shift to the low voltage level side) in the period “T5”, the source electrode voltage Vs temporarily transitions to the low potential side. . Thereafter, when the counter electrode voltages Vcom1 and Vcom2 are stabilized, the source voltage Vs transitions again to the inputted drain voltage VdWL. In the 'T7' period, the counter electrode voltage Vcom2 and the source voltage Vs are transitioned to desired voltage levels. The effective voltage value applied to the liquid crystal 119 at this time is −VrmsWL3. In addition, when a non-selection voltage is applied to the scanning line and the TFT 118 transitions to the “off” state, the phenomenon of the voltage jumping into the parasitic capacitance 122 described above occurs. This jump voltage level is ΔVgsWL. Therefore, as a result, the effective voltage value applied to the liquid crystal 119 is −VrmsWL4 (= −VrmsWL3−ΔVgsWL). As described above, the effective voltage value is a desired effective voltage value because the counter electrode voltage Vcom2 in the liquid crystal panel 206 matches the desired counter electrode voltage Vcom1.
[0053]
  Accordingly, applying a convex correction voltage to the positive (high potential) counter electrode voltage Vcom described in this embodiment has an effect of improving the convergence rate of the counter electrode voltage Vcom2 inside the liquid crystal panel 106. .
[0054]
  Next, when the positive white display voltage VdWH shown in FIG. 12B is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is equal to the drain voltage Vd of the previous line in the 'T1' period. Transition to the voltage level (shifted to a higher potential). After that, when the counter electrode voltage is changed to AC in the “T2” period, the change of the counter electrode voltage is steeper than the writing speed of the TFT 118. Therefore, the potential of the source voltage Vs is as shown in FIG. As shown, the potential shifts to a low potential in accordance with the alternating voltage of the counter electrode voltage. At this time, the voltage level of the counter electrode voltage Vcom is corrected in advance to a high potential voltage level (VcomB) in order to correct distortion. After that, the source voltage Vs transitions to the potential of the drain voltage Vs in the period “T3” and “T4”, but the source voltage Vs is in a lower potential state than the counter electrode voltage Vcom2 in the liquid crystal panel 106 in the period “T3”. In the 'T4' period, the source voltage Vs is in a lower potential state than the counter electrode voltage Vcom2 inside the liquid crystal panel 106. In this operation, by adding a correction voltage to the counter electrode voltages Vcom1 and Vcom2 so that the counter electrode voltage potential is positioned higher than the normal counter electrode voltage level, the convergence rate of the source voltage Vs is shortened. are doing. As a result, the effect of improving the convergence rate of the counter electrode voltage is aimed. Next, since the counter electrode voltages Vcom1 and Vcom2 transition to the normal counter electrode voltage level (shift to the low voltage level side) in the period “T5”, the source electrode voltage Vs temporarily transitions to the low potential side. . Thereafter, when the counter electrode voltages Vcom1 and Vcom2 are stabilized, the source voltage Vs transitions again to the inputted drain voltage VdWH. In the 'T7' period, the counter electrode voltage Vcom2 and the source voltage Vs are transitioned to desired voltage levels. The effective voltage value applied to the liquid crystal 119 at this time is VrmsWH3. In addition, when a non-selection voltage is applied to the scanning line and the TFT 118 transitions to the “off” state, the phenomenon of the voltage jumping into the parasitic capacitance 122 described above occurs. This jump voltage level is ΔVgsWH. Therefore, as a result, the effective voltage value applied to the liquid crystal 119 is VrmsWL4 (= VrmsWL3−ΔVgsWL). As described above, the effective voltage value is a desired effective voltage value because the counter electrode voltage Vcom2 in the liquid crystal panel 206 matches the desired counter electrode voltage Vcom1.
[0055]
  Therefore, applying a convex correction voltage to the negative polarity (low potential) counter electrode voltage Vcom described in this embodiment improves the writing speed, thereby reducing the counter electrode voltage Vcom2 inside the liquid crystal panel 106. There is an effect of improving the convergence rate.
[0056]
  When the negative black display voltage VdBL shown in FIG. 13A is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the voltage level of the drain voltage Vd of the previous line in the 'T1' period. (Shifts to high potential). After that, when the counter electrode voltage is changed to AC in the period “T2”, the change of the counter electrode voltage is steeper than the writing speed of the TFT 118. Therefore, the potential of the source voltage Vs is as shown in FIG. As shown in the figure, the counter electrode voltage shifts to a high potential according to the alternating current, and also transitions to the potential of the drain voltage Vd and stabilizes. At this time, the voltage level of the counter electrode voltage Vcom is corrected in advance to a high potential voltage level (VcomHB) in order to perform voltage correction when the white display voltage is applied. After that, the counter electrode voltages Vcom1 and Vcom2 transition to the normal counter electrode voltage level (shift to the low voltage level side) in the period “T3”, so that the source electrode voltage Vs temporarily transitions to the low potential side. Thereafter, when the counter electrode voltages Vcom1 and Vcom2 are stabilized, the source voltage Vs transitions again to the inputted drain voltage VdBL. In the 'T4' period, the counter electrode voltage Vcom2 and the source voltage Vs transition to the desired voltage level. The effective voltage value applied to the liquid crystal 119 at this time is VrmsBL3. In addition, when a non-selection voltage is applied to the scanning line and the TFT 118 transitions to the “off” state, the phenomenon of the voltage jumping into the parasitic capacitance 122 described above occurs. This jump voltage level is ΔVgsBL. Therefore, as a result, the effective voltage value applied to the liquid crystal 119 is −VrmsBL4 (= VrmsBL3−ΔVgsBL). As described above, the effective voltage value is a desired effective voltage value because the counter electrode voltage Vcom2 in the liquid crystal panel 106 matches the desired counter electrode voltage Vcom1.
[0057]
  Therefore, even if an upward convex correction voltage is applied to the positive (high potential) counter electrode voltage Vcom described in the present embodiment, the write voltage amount is small, so that there is no effect on the effective voltage value.
[0058]
  Next, in the case where the positive black display voltage VdBH shown in FIG. 13B is applied, when the selection voltage Vgon is applied to the scanning line, the source voltage Vs is the drain voltage Vd of the previous line in the 'T1' period. Transition to the voltage level (shifted to a higher potential). Thereafter, when the counter electrode voltage is changed to AC in the period “T2”, the change of the counter electrode voltage is steeper than the writing speed of the TFT 118, and therefore the potential of the source voltage Vs is as shown in FIG. As shown in the figure, the potential shifts to a low potential in accordance with the alternating voltage of the counter electrode voltage and transitions to the drain voltage Vd level. At this time, the voltage level of the counter electrode voltage Vcom is corrected in advance to the high potential voltage level (VcomLB) in order to apply the white display voltage. Thereafter, the source voltage Vs transits to the potential of the drain voltage Vd. After that, the counter electrode voltages Vcom1 and Vcom2 transition to the normal counter electrode voltage level (shift to the low voltage level side) in the period “T3”, so that the source electrode voltage Vs temporarily transitions to the low potential side. Thereafter, when the counter electrode voltages Vcom1 and Vcom2 are stabilized, the source voltage Vs transitions again to the inputted drain voltage VdBL. In the 'T4' period, the counter electrode voltage Vcom2 and the source voltage Vs transition to the desired voltage level. The effective voltage value applied to the liquid crystal 119 at this time is VrmsBH3. In addition, when a non-selection voltage is applied to the scanning line and the TFT 118 transitions to the “off” state, the phenomenon of the voltage jumping into the parasitic capacitance 122 described above occurs. This jump voltage level is ΔVgsBL. Therefore, as a result, the effective voltage value applied to the liquid crystal 119 is VrmsBH4 (= VrmsBH3−ΔVgsBH). As described above, the effective voltage value is a desired effective voltage value because the counter electrode voltage Vcom2 in the liquid crystal panel 106 matches the desired counter electrode voltage Vcom1.
[0059]
  Therefore, it is described in this example.negativepolarity(LowEven if an upward convex correction voltage is applied to the counter electrode voltage Vcom of (potential), since the write voltage amount is small, there is no influence on the effective voltage value.
[0060]
  As described above, by applying a correction voltage to the counter electrode voltage described in the present embodiment, the waveform distortion of the counter electrode voltage can be corrected, and a good display screen can be obtained without depending on display data. Become.
[0061]
  Next, FIG. 14 shows the relationship between the application time of the high potential counter electrode voltage and the amount of change in luminance when a counter electrode voltage having a potential higher than the final target counter electrode voltage level is once applied to the counter electrode voltage Vcom. The relationship between the potential difference between the counter electrode voltage level of the final target and the counter electrode voltage level once set to a high potential voltage, and the amount of change in luminance is shown in FIG.
[0062]
  In FIG. 14, the vertical axis represents the smear level, and the left and right background display luminances “BA” of the white display rectangle of the “A” region and the background display luminance “BB” of the “B” region described in FIG. The following is obtained from the difference in luminance.
[0063]
[Expression 2]
  ΔB = | (BB−BA) / BB | (Expression 2)
  Accordingly, when the left and right background display luminances “BA” of the white display rectangle in the “A” area are darker than the background display luminances “BB” in the “B” area as in the conventional example, the positive value is an absolute value. Converted. In addition, the smear level is a level in which 3% or less cannot be seen as a luminance difference by human eyes. Further, the horizontal axis represents the ratio of the time during which a counter electrode voltage having a higher potential voltage than the final target counter electrode voltage level is applied within one horizontal period. For example, the horizontal resolution is 1024 dots, the number of vertical lines In a 768-line liquid crystal panel, one horizontal time is about 16 μs, so 50% is about 8 μs. In addition, the potential difference between the final counter electrode voltage level at this time and the counter electrode voltage level once set to a high potential voltage is described as 1.5V. Speaking from FIG. 14, the smear level can be suppressed to within 3% by applying the correction voltage for a period of about 50% (8 μs) to 75% (12 μs). Therefore, if the correction voltage application period is short, there is no effect of applying the correction voltage, and if the correction voltage application period is long, the counter electrode voltage does not reach the final counter electrode voltage level.
[0064]
  In FIG. 15, the vertical axis represents the smear level, the horizontal axis represents the potential difference between the final counter electrode voltage level and the counter electrode voltage level once set to a high potential voltage, and the correction voltage application period is 10 μs. is there. Speaking from FIG. 15, the smear level can be suppressed to within 3% by applying the correction voltage from 1V to 2V. Therefore, if the voltage level of the correction voltage is low, there is no effect of applying the correction voltage, and if the voltage level of the correction voltage is high, the counter electrode voltage does not reach the final target counter electrode voltage level.
[0065]
  As described above, in the description of the embodiment of the present invention, a counter electrode voltage having a potential higher than the final target counter electrode voltage level is once applied to the positive (high potential) counter electrode voltage Vcom; By applying a counter electrode voltage having a higher potential than the final target counter electrode voltage level to the negative electrode (negative potential) counter electrode voltage Vcom, it is possible to solve the conventional lateral smear. However, as an example in which the present invention is most effective, it is a TFT liquid crystal panel having a small liquid crystal capacity. That is, when the liquid crystal capacitance is small, the amount of jumping voltage ΔVgs jumping into the parasitic capacitance between the source and gate increases, and the source electrode voltage level is reduced when the negative electrode (low potential) counter electrode voltage described in FIG. This is because the write margin is insufficient.
[0066]
  Therefore, as a method with a small liquid crystal capacity, the liquid crystal is operated by an electric field substantially parallel to the substrate surface between two electrodes formed on the same substrate, and light incident on the liquid crystal from the gap between the two electrodes is modulated and displayed. This is considered to be effective for a TFT liquid crystal display employing a horizontal electric field type liquid crystal.
[0067]
  Next, a TFT liquid crystal display employing a horizontal electric field type liquid crystal will be described.
[0068]
  FIG. 16 shows the active of the present invention.MaIt is a top view which shows one pixel and its periphery of a trix system color liquid crystal display device. As shown in FIG. 16, each pixel includes a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode line) CL, and two adjacent video signal lines (drain signal line or line). The vertical signal line (DL) is arranged in a region intersecting with DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL and counter-voltage signal lines CL are arranged in the up-down direction. The video signal lines DL extend in the vertical direction, and a plurality of video signal lines DL are arranged in the horizontal direction. The pixel electrode PX is connected to the thin film transistor TFT, and the counter electrode CT is integrated with the counter voltage signal line CL.
[0069]
  The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode CT, thereby controlling display. The pixel electrode PX and the counter electrode CT are formed in a comb-teeth shape, and are each an elongated electrode in the vertical direction of the figure.
[0070]
  17 is a cross-sectional view taken along the line 3-3 in FIG. 16, FIG. 18 is a cross-sectional view of the thin film transistor TFT along the line 4-4 in FIG. 16, and FIG. 19 is a storage capacitor Cstg along the line 5-5 in FIG. FIG. As shown in FIGS. 17 to 19, a thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and a color filter FIL, on the upper transparent glass substrate SUB2 side. A light blocking black matrix pattern BM is formed.
[0071]
  In addition, alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal are provided on the inner surfaces (liquid crystal LC side) of the transparent glass substrates SUB1 and SUB2, and the outer sides of the transparent glass substrates SUB1 and SUB2. Is provided with a polarizing plate in which the polarization axes are arranged orthogonally (crossed Nicols arrangement).
[0072]
  16 to 19, the liquid crystal is operated by an electric field substantially parallel to the substrate surface between two electrodes formed on the same substrate, and light incident on the liquid crystal from the gap between the two electrodes is modulated. It becomes possible to display.
[0073]
  Next, a module structure diagram of the TFT liquid crystal panel to which the present invention is applied will be described.
[0074]
  FIG. 20 is an exploded perspective view showing each component of the liquid crystal display module MDL. SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, PCB1 is a signal drive circuit, PCB2 is a scan drive circuit, MCA is an intermediate case, and SPB is light diffusion The plate, LCB is a light guide, BL1 and BL2 are backlight fluorescent tubes, LCA is a backlight case, and IFPCB is an interface circuit board. Each member is stacked in a vertical arrangement relationship as shown in FIG. Assembled.
[0075]
  The module MDL is fixed in its entirety by claws and hooks provided in the shield case SHD. The backlight case LCA is configured to accommodate the backlight fluorescent tube BL, the light diffusion plate SPB, and the light guide LCB, and guides the light of the backlight fluorescent tube BL disposed on the side surface of the light guide LCB. The body LCB, the reflecting plate RM, and the light diffusing plate SPB make a uniform backlight on the display surface and emit it toward the liquid crystal display panel PNL side. The interface circuit 102 and the power supply circuit 105 shown in FIG. 1 of the present invention are mounted on the IFPCB.
[0076]
  An example in which the state is viewed from the rear side of the liquid crystal module MDL in FIG. 21 will be described.
[0077]
  Thus, the interface circuit 102 and the power supply circuit 105 shown in FIG. 1 of the present invention are mounted on the IFPCB.
[0078]
  According to the above embodiment, the following effects can be obtained. According to the embodiment of the present invention, when the counter electrode voltage transitions to a positive (high potential) counter electrode voltage, an upward convex correction voltage is applied so that the counter electrode voltage inside the liquid crystal panel is reduced. It is possible to make the voltage level transition to the normal voltage level within the specified time, and when making a transition to the negative electrode (low potential) counter electrode voltage, the source voltage is applied by applying an upward convex correction voltage. Makes it possible to transition the voltage level of the counter electrode voltage inside the liquid crystal panel to the normal voltage level within a specified time by making the transition to the drain voltage level at high speed. It is possible to stabilize the effective voltage value to be applied, and there is an effect that high-quality display can be realized even if a signal driving circuit compatible with low voltage driving is used.
[0079]
  In addition, the period during which the correction voltage is applied can be easily set and made variable, so that it is possible to easily handle liquid crystal panels with different loads. There is.
[0080]
  Further, according to the embodiment of the present invention, it is possible to easily change the correction voltage level of the counter electrode voltage by changing the resistance value for current drawing constituting the feedback system of the buffer amplifier. It is possible to easily cope with liquid crystal panels with different loads, and there is an effect that liquid crystal panels of various specifications can be displayed with high image quality.
[0081]
  Further, according to the embodiment of the present invention, it becomes possible to use a signal driving circuit compatible with low voltage driving, and the signal driving circuit can be configured by a low-cost general-purpose LSI process. There is an effect that can be configured.
[0082]
  Further, according to the embodiment of the present invention, a signal driving circuit can be configured by a low-cost general-purpose LSI process, and the signal driving circuit can be reduced in size, so that the frame of the liquid crystal display can be narrowed. effective.
[0083]
【The invention's effect】
  According to the present invention, there is an effect that high-quality display can be realized even if a signal driving circuit compatible with low voltage driving is used.
[Brief description of the drawings]
FIG. 1 is a block diagram of a liquid crystal display according to the present invention.
FIG. 2 is a block diagram of a conventional liquid crystal display.
FIG. 3 is a driving waveform diagram of a conventional liquid crystal display.
FIG. 4 is a driving waveform diagram of a conventional liquid crystal display.
FIG. 5 is a driving waveform diagram of a conventional liquid crystal display.
FIG. 6 is a display example of a conventional liquid crystal display.
FIG. 7 is a driving waveform diagram of a conventional liquid crystal display.
FIG. 8 is a block diagram of an AC circuit and a correction circuit according to the present invention.
FIG. 9 is a timing chart showing the operation of the AC circuit and the correction circuit of the present invention.
FIG. 10 is a circuit diagram of a common electrode voltage generation circuit according to the present invention.
FIG. 11 is a drive waveform diagram showing the operation of the common electrode voltage generation circuit of the present invention.
FIG. 12 is a drive waveform diagram of the liquid crystal display of the present invention.
FIG. 13 is a drive waveform diagram of the liquid crystal display of the present invention.
FIG. 14 is a graph showing the relationship between the smear level and the correction power application time according to the present invention.
FIG. 15 is a graph showing the relationship between the smear level and the correction voltage amount according to the present invention.
FIG. 16 is a plan view showing one pixel of the liquid crystal display device of the present invention and its periphery.
17 is a view showing a cross section taken along the line 3-3 in FIG. 16;
18 is a cross-sectional view of the thin film transistor TFT taken along the line 4-4 in FIG.
FIG. 19 is a diagram showing a cross section of the storage capacitor Cstg at the section line 5-5 in FIG.
FIG. 20 is an exploded perspective view showing components of the liquid crystal display module MDL of the present invention.
FIG. 21 is a view of the liquid crystal module MDL of the present invention as viewed from the rear side.
[Explanation of symbols]
101: interface signal, 102: interface circuit, 103: signal drive circuit, 104: scan drive circuit, 105: power supply circuit, 106: liquid crystal panel, 107: control signal, 108: control signal, 109: alternating signal M ′ 110: correction period signal, 111: correction period signal, 112: gradation voltage signal, 113: scanning voltage signal, 114: counter electrode, 115: signal line group, 116: scanning line group, 117: pixel portion, 118: thin film transistor (Thin Film Transistor, TFT), 119: liquid crystal, 120: compensation capacitor, 121: source electrode, 122: gate−Parasitic capacitance between sources, 123: setting circuit, 124: setting signal, 201: interface signal, 202: interface circuit, 203: signal driving circuit, 204: scan driving circuit, 205: power supply circuit, 206: liquid crystal panel, 207: control Signal, 208: control signal, 209: alternating signalM '210: gradation voltage signal, 211: scanning voltage signal, 212: counter electrode, 213: signal line group, 214: scanning line group, 215: pixel portion, 216: thin film transistor (Thin Film Transistor, TFT), 217: liquid crystal 218: compensation capacitor, 219: source electrode, 220: gate−Parasitic capacitance between sources, 801: vertical synchronization signal VSYNC, 802: horizontal synchronization signal HSYNC, 803: dot clock DotCLK, 804: counter electrode voltage positive polarity correction signal PBST, 805: counter electrode voltage negative polarity correction signal NBST, 811 : AC signalM '828: Counter electrode voltage positive polarity correction period setting signal PBSTSET, 830: Counter electrode voltage negative polarity correction period setting signal NBTSSET, 806: Flip flop, 808: Flip flop, 807: Frequency division signal, 809: Frequency division signal 810: exclusive logical OR circuit, 812: counter, 813: output signal, 814: decode circuit, 815: decode circuit, 815: output signal, 816: output signal, 818: comparison circuit, 820: comparison circuit, 819: Output signal, 821: Output signal, 822: JK flip-flop, 824: JK flip-flop, 823: Output signal, 825: Output signal, 827: AND circuit, 829: AND circuit, 1001: Capacitor, 1002: Resistor, 1003: Buffer amplifier, 1004: capacitor, 1005: diode 1006: diode, 1007: resistor, 1008: resistor, 1009: resistor, 1010: buffer amplifier, 1011: resistor, 1012: volume resistor, 1013: resistor, 1014: resistor, 1015: buffer transistor, 1016: buffer transistor, 1017 : Resistor, 1018: resistor, 1019: capacitor, 1020: resistor, 1021: diode, 1022: transistor, 1023: resistor, 1024: capacitor, 1025: resistor, 1026: diode, 1027: transistor, 1028: resistor.

Claims (10)

A liquid crystal panel having M pixels in the horizontal direction and N pixels in the vertical direction, each of which includes a switching element composed of a thin film transistor and a liquid crystal, and display data are input, and a gradation voltage is generated according to the input display data. Then, one of the signal driving circuit for applying this to the corresponding pixel unit in the horizontal direction of the display data and the pixel unit arranged in the vertical direction are sequentially selected and arranged in the vertical direction selected at that time. The pixel portion to be applied is provided with a scanning drive circuit for applying a selection voltage to the pixel portion arranged in the vertical direction that is not selected at that time, and a non-selection voltage.
The liquid crystal has one common counter electrode in each pixel unit, and when the selection voltage output from the scan driving circuit is applied to the switching element of the pixel unit, the signal driving circuit generates In a liquid crystal display device that applies a gradation voltage to the liquid crystal and controls display luminance by an effective voltage value of the gradation voltage with respect to the counter electrode.
A circuit for generating an AC signal indicating AC conversion of the counter electrode voltage applied to the counter electrode, and a correction period signal indicating a period of applying a correction voltage to the counter electrode voltage applied to the counter electrode;
The AC signal and the correction period signal generate the AC counter voltage applied to the counter electrode, and when the counter electrode voltage is a positive voltage, the counter electrode voltage in the first half of one horizontal period. And a counter electrode voltage generating circuit that applies a convex correction voltage to the counter electrode voltage in the first half of one horizontal period when the counter electrode voltage is a negative voltage. A liquid crystal display device.   A circuit that generates a correction period signal indicating a period in which a correction voltage is applied to the counter electrode voltage applied to the counter electrode is compared with a counter that counts one horizontal period and a setting value that indicates the correction period, and the correction The liquid crystal display device according to claim 1, wherein a period signal is generated. The AC signal and the correction period signal generate the AC counter voltage applied to the counter electrode, and when the counter electrode voltage is a positive voltage, the counter electrode voltage in the first half of one horizontal period. When the counter electrode voltage is a negative voltage, the counter electrode voltage generation circuit for applying the convex correction voltage to the counter electrode voltage in the first half of one horizontal period is applied to the counter electrode. 3. The liquid crystal display device according to claim 1, wherein the voltage is shifted to a higher potential voltage level than a normal counter electrode voltage when the correction period signal is valid. The correction period signal is valid in the first half of one horizontal period,
The liquid crystal display device according to claim 1, wherein the counter electrode voltage generation circuit adds the correction voltage when the correction period signal is valid.   The liquid crystal display device according to claim 2, wherein the set value indicating the correction period is variable according to characteristics of the liquid crystal panel.   The counter electrode voltage generation circuit includes a buffer circuit for amplifying the alternating signal, a feedback circuit using a resistor, and a switch circuit added to the feedback circuit, and the switch circuit is in a state where the correction period signal is valid. 4. The liquid crystal display device according to claim 3, wherein the correction voltage is added by controlling the current amount of the feedback circuit.   3. The liquid crystal display device according to claim 2, wherein the correction period signal has a different correction period between the positive-polarity counter electrode voltage and the negative-polarity counter electrode voltage.   4. The liquid crystal display device according to claim 3, wherein the correction voltage is different in a correction voltage level at the time of the positive counter electrode voltage and a correction voltage level at the time of the negative counter electrode voltage. A liquid crystal panel having a plurality of pixel portions each provided with a switching element and a liquid crystal composed of a thin film transistor, and a common counter electrode in each pixel portion of the liquid crystal panel, and a selection output from the scan drive circuit to the pixel portion When a voltage is applied, a gradation voltage generated by a signal driving circuit is applied to the liquid crystal, and a display luminance is controlled by an effective voltage value of the gradation voltage with respect to the counter electrode.
A circuit that generates a correction period signal indicating a period during which a correction voltage is applied to the counter electrode voltage applied to the counter electrode;
In the period when the AC signal is applied, when the counter electrode voltage is a positive voltage, a correction voltage is applied to the counter electrode voltage in the first half of one horizontal period so that the value becomes larger on the positive electrode side. A liquid crystal display device comprising: a counter electrode voltage generation circuit that applies a correction voltage to the counter electrode voltage in the first half of one horizontal period so that the value on the negative electrode side becomes small when the voltage is a negative voltage. When the selection voltage output from the scan driving circuit is applied to the pixel portion of the liquid crystal panel having a plurality of pixel portions each including a switching element formed of a thin film transistor and a liquid crystal, the gradation voltage generated by the signal driving circuit is In a voltage correction circuit of a liquid crystal display device, which is applied to a liquid crystal and controls display luminance by an effective voltage value of the gradation voltage with respect to a common counter electrode in each pixel unit,
A circuit that generates a correction period signal indicating a period during which a correction voltage is applied to the counter electrode voltage applied to the counter electrode;
In the period when the AC signal is applied, when the counter electrode voltage is a positive voltage, a correction voltage is applied to the counter electrode voltage in the first half of one horizontal period so that the value becomes larger on the positive electrode side. A voltage correction circuit , comprising: a counter electrode voltage generation circuit that applies a correction voltage to the counter electrode voltage in the first half of one horizontal period so that the value on the negative electrode side becomes small when the voltage is a negative voltage.

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