JP3706705B2 - Dependent device used in PDS transmission system and clock synchronization method in dependent device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a slave device used in a PDS transmission system and a clock synchronization method in the slave device, and more particularly to a slave device used in a PDS transmission system suitable for improving the accuracy of a phase for transmitting a burst signal. And a clock synchronization method in a subordinate apparatus.
[0002]
[Prior art]
A PDS (Passive Double Star) transmission for transmitting data by connecting a plurality of subscriber line termination devices (hereinafter referred to as home devices) to one subscriber line termination station device (hereinafter referred to as a station device). The system is used. Each in-home device operates an internal circuit in accordance with the extracted clock extracted from the downlink data signal transmitted from the station device. The burst signal to be transmitted to the station apparatus is transmitted according to the extracted clock.
[0003]
However, since the downlink data signal received by each in-home device often includes jitter, the jitter is superimposed on the extracted clock on which the internal circuit operates. The in-home device transmits a burst signal to the station device in accordance with the extracted clock on which the jitter is superimposed, so that the jitter included in the downlink signal is propagated to the burst signal.
[0004]
If jitter is included in the burst signal, an error occurs when the station apparatus reads the burst signal. In order to prevent this error, a clock synchronization method for reducing jitter included in a burst signal has been developed. For example, there is a home device that generates a device clock stabilized in the device and transmits a burst signal in accordance with the device clock. By transmitting the burst signal according to the stabilized in-device clock, it is possible to reduce jitter included in the transmitted burst signal. An elastic store memory is used to transfer a data signal between a circuit that operates with an extraction clock for receiving a downlink data signal and a circuit that operates with an in-device clock for transmitting a burst signal. This is to avoid the difficulty in passing data signals due to the phase difference between the extracted clock and the in-device clock. As a specific circuit example using an elastic store memory, there is a frame aligner described in Japanese Patent Application Laid-Open No. 61-90542.
[0005]
[Problems to be solved by the invention]
However, in the conventional home device, the signal transmission phase for transmitting the burst signal is controlled with reference to the frame synchronization signal included in the received downlink data signal. For this reason, if the downlink data signal includes jitter, an error corresponding to the jitter occurs in the signal transmission phase.
[0006]
The circuit for controlling the signal transmission phase operates according to a clock that is reduced to a signal speed at which the phase difference between the extracted clock and the in-device clock can be ignored. This is to process both the frame reference signal in the downlink data signal and the burst signal according to the in-device clock. However, if the clock speed is reduced, the clock cycle becomes longer and the phase control step becomes rougher. This causes the accuracy of controlling the phase to deteriorate.
[0007]
In the PDS transmission system, each in-home device controls the signal transmission phase so that the burst signal arrives at the station device in the assigned time slot. However, if the accuracy of the signal transmission phase is insufficient, burst signals transmitted from a plurality of in-home devices may collide with each other. In order to avoid this collision, a guard time is provided between adjacent time slots.
[0008]
However, providing a guard time, on the other hand, reduces the time slot resources that can be allocated. This leads to a decrease in data transmission efficiency in the transmission system. The inventors focused on reducing the guard time by improving the accuracy of the signal transmission phase for transmitting the burst signal.
[0009]
Effective use of time slot resources is common to subordinate apparatuses that perform transmission of data signals to the main apparatus in the TDMA system, such as the remote concentrator for connecting the in-home apparatus to the station apparatus in addition to the in-home apparatus described above. It is a problem.
[0010]
Therefore, an object of the present invention is to provide a slave device that can improve the accuracy of the burst signal transmission phase, and a clock synchronization method in the slave device.
[0011]
[Means for Solving the Problems]
According to the present invention, in order to achieve the above object,
One main device is used in a PDS (Passive Double Star) transmission system for transmitting data between the main device and a plurality of subordinate devices, receives a downlink data signal including a synchronization signal from the main device, and In the subordinate apparatus for transmitting the burst signal constituting the upstream data signal to the main apparatus,
With reference to the downlink data signal received from the main device, a stabilized clock generator for generating a stabilized in-device clock,
A clock re-sending unit for replacing the received downlink data signal with the in-device clock;
A delay time setting unit for setting a delay time from receiving a downlink data signal to transmitting a burst signal;
A synchronization signal detection unit for detecting a synchronization signal from a downlink data signal transferred to the in-device clock;
A delay amount adjusting unit for adjusting a phase for transmitting the burst signal to the main device to a phase that has passed the delay time after the synchronization signal is detected;
A slave device is provided that features:
[0012]
According to the second aspect of the present invention,
One main device is used in a PDS (Passive Double Star) transmission system for transmitting data between the main device and a plurality of subordinate devices, receives a downlink data signal including a synchronization signal from the main device, and In the clock synchronization method in the subordinate apparatus for transmitting the burst signal constituting the upstream data signal to the main apparatus,
Referring to the downlink data signal received from the main device, generate a stabilized in-device clock,
Replace the received downlink data signal with the in-device clock,
Detecting a frame synchronization signal included in the downlink data signal transferred to the in-device clock;
A burst signal is transmitted to the main device at a timing when a predetermined delay time has elapsed since the synchronization signal was detected.
A clock synchronization method is provided.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described with reference to FIGS. The present embodiment is an example of a home device used in a PDS transmission system having a station device as a main device and a home device as a subordinate device subordinate thereto.
[0014]
First, a configuration example of a PDS transmission system will be described with reference to FIG. In FIG. 1, the PDS transmission system includes a station device 18, N (N is a positive integer) indoor devices 1000 (1) to (N), and an optical star coupler 20. Composed.
[0015]
The station apparatus 18 and the optical star coupler 20 are connected by the optical fiber transmission line 16, and the N indoor devices 1000 (1) to (N) and the optical star coupler 20 are connected to the N optical fiber transmission lines 17 (1 ) To (N).
[0016]
Next, a data transmission method in the PDS transmission system will be described with reference to FIG. 2 and FIG. As shown in FIG. 2, the downlink data signal transmitted from the station apparatus 18 to each of the in-home apparatuses 1000 (1) to 1000 (N) is transmitted by a TDM (Time-Division Maltiplexing) system. As shown in FIG. 3, uplink data signals sent from the in-home devices 1000 (1) to (N) to the station device are transmitted by a TDMA (Time-Division Multiple Access) system.
[0017]
As shown in FIG. 2, the downlink data signal 1 transmitted from the station apparatus 18 to each of the in-home apparatuses 1000 (1) to (N) has N bursts for the N in-home apparatuses 1000 (1) to (N). The signal is sent to the optical fiber transmission line 16 as a series of signals including signals (hereinafter referred to as a series of signals). The continuous signal sent to the optical fiber transmission line 16 is branched by the optical star coupler 20 into N optical fiber transmission lines 17 (1) to (N). The branched signals 2 (1) to (N) are sent as serial signals to the in-home devices 1000 (1) to (N), respectively.
[0018]
On the other hand, as shown in FIG. 3, the uplink data signals transmitted from the in-home devices 1000 (1) to (N) to the station device 18 are transmitted from the in-home devices 1000 (1) to (N), respectively. 1) to (N). The transmitted burst signals 3 (1) to (N) are respectively sent to the transmission lines 17 (1) to (N) and multiplexed by the optical star coupler 20. The uplink data signal 4 multiplexed including the N burst signals 3 (1) to (N) is transmitted through the transmission path 16 and sent to the station apparatus 18.
[0019]
The burst signals 3 (1) to (N) are transmitted by controlling the transmission phase so that the burst signals do not collide when they arrive at the station device 18.
[0020]
That is, the time during which the transmitted burst signal is allowed to arrive at the station device 18 (hereinafter referred to as a time slot) is exclusively assigned to each of the in-home devices 1000 (1) to (N). Between each time slot, a time during which no burst signal is allowed to arrive (hereinafter referred to as a guard time) is provided. The magnitude of the guard time is determined in advance so that the burst signals do not collide with each other in consideration of the phase error at which the burst signals arrive at the station device 18. Each of the in-home devices 1000 (1) to (N) is assigned with each of the transmission delays corrected by the optical fiber transmission line 16 and the optical fiber transmission lines 17 (1) to (N) to which the in-home devices 1000 (1) to (N) are connected. The signal transmission phase for transmitting the burst signal is controlled so that the burst signal arrives at the station apparatus 18 in the determined time slot.
[0021]
Next, the home device will be described in detail with reference to FIG. In FIG. 4, an in-home device 1000 includes an interface unit 1100 for transmitting / receiving data signals to / from the outside, a clock stabilizing unit 1200 for stabilizing the clock of the data signal, and a data processing unit for executing data processing. 1400 and a termination circuit unit 1300 for transmitting / receiving a data signal to / from the data processing unit 1400.
[0022]
The downlink data signal OD given through the optical fiber transmission line 17 is received by the interface unit 1100, and the clock RC is extracted. The clock RC and the interfaced data signal RD are sent to the clock stabilization unit 1200 to stabilize the clock fluctuation. The stabilized data signal TD is sent to the termination circuit unit 1300 and terminated. The terminal-processed data signal PD is given to the data processing unit 1400, and processing is executed.
[0023]
On the other hand, the data signal PD generated by the data processing unit 1400 is terminated by the termination circuit unit 1300 and delayed by the clock stabilization unit 1200 so as to be transmitted at a predetermined timing. The delayed data DD is sent to the optical fiber transmission line 17 via the interface unit 1100.
[0024]
The clock stabilization unit 1200 includes a stabilization clock generation unit 1210 for generating a stabilized in-device clock, a clock reordering unit 1220 for replacing the clock of the downlink data signal with the in-device clock, A synchronization signal detection unit 1230 for detecting a frame synchronization signal from a downlink data signal transferred to the in-device clock, a delay time setting unit 1240 for setting a phase for transmitting a burst signal, and the delay time setting unit And a delay amount adjusting unit 1250 for adjusting the phase for transmitting the burst signal according to the delay time set to 1240.
[0025]
The stabilized clock generation unit 1210 refers to the clock RC extracted by the interface unit 1100, generates a stabilized clock SC with suppressed jitter, and outputs the generated stabilized clock SC to each block (clock mounted) of the clock stabilization unit 1200. To the replacement unit 1220, the synchronization signal detection unit 1230, the delay time setting unit 1240, and the delay amount adjustment unit 1250).
[0026]
The clock replacing unit 1220 replaces the clock of the data signal RD supplied from the interface unit 1100 with the stabilized clock SC and sends the clock to the synchronization signal detecting unit 1230 and the termination circuit unit 1300.
[0027]
When the synchronization signal detection unit 1230 detects a frame synchronization signal included in the data signal TD replaced with the stabilization clock, the synchronization signal detection unit 1230 sends the detection signal DS to the delay time setting unit 1240.
[0028]
The delay time setting unit 1240 is based on the data signal TD whose clock has been replaced, the data signal D sent from the termination circuit unit 1300, and the delay time that it has instructed immediately before. A delay time to be delayed is set, and this delay time is instructed to the delay amount adjustment unit 1250.
[0029]
The delay amount adjustment unit 1250 delays the data signal D supplied from the termination circuit unit 1300 by the delay time instructed by the delay time setting unit 1240 and sends it to the interface unit 1100.
[0030]
Next, details of each unit will be described with reference to FIGS.
[0031]
First, the interface unit 1100 will be described with reference to FIG.
[0032]
The interface unit 1100 has an optical / electrical conversion unit 1110 for converting the downlink data signal OD input as an optical signal into a data signal RD of an electrical signal, and a clock RC from the downlink data signal converted into the electrical signal. A clock extracting unit 1120 for extracting and an electric / optical converting unit 1130 for converting the data signal DD given as an electric signal from the data processing unit 1300 into a data signal OD of an optical signal are configured. The Here, the data signal and clock handled by the optical / electrical conversion unit 1110 and the clock extraction unit 1120 correspond to the clock (extraction clock RC) of the applied downlink data signal, and the data handled by the electrical / optical conversion unit 1130. The clock of the signal corresponds to the stabilized clock SC generated by the stabilized clock generator 1210 (see FIG. 4).
[0033]
Next, the stabilized clock generator 1210 will be described with reference to FIG.
[0034]
The stabilized clock generator 1210 is for referring to the clock RC extracted by the clock extractor 1120 and generating a stabilized clock SC with reduced jitter. For example, for a given clock, a stabilized clock can be generated by averaging clock pulse intervals in accordance with a predetermined rule. More specifically, for example, averaging the intervals between adjacent clock pulses, averaging the period of a predetermined pulse (for example, a pulse of a frame synchronization signal), and the time variation component of the phase It is possible to suppress high-frequency components for Fourier transform. Specifically, for example, the stabilized clock generation unit 1210 can be configured using a phase-locked oscillator that oscillates with reference to the extracted clock.
[0035]
FIG. 10 shows a configuration example of a stabilization clock generation unit 1210 using a phase locked oscillator.
[0036]
In FIG. 10, a stabilization clock generator 1210 compares the phase of a voltage control oscillator 1212 that oscillates at a frequency corresponding to a control voltage with a given reference signal and a signal that the voltage control oscillator 1212 oscillates. The phase comparator 1214 includes a low-pass filter 1216 for suppressing the high-frequency component of the time change of the voltage output of the phase comparator 1214.
[0037]
The voltage controlled oscillator 1212 oscillates with the output voltage of the phase comparator 1214 given through the low-pass filter 1216 as a control voltage, and is controlled so that the oscillation frequency becomes the frequency of the reference signal. Here, the control voltage is suppressed by the low-pass filter 1216 for the high-frequency component of the time change. For this reason, the high frequency component of the time change of the oscillation frequency of the voltage controlled oscillator 1212 is suppressed. Therefore, the voltage controlled oscillator 1212 can oscillate a signal with a frequency that follows the reference signal and with reduced jitter.
[0038]
Next, the clock replacement unit 1220 will be described with reference to FIGS. The clock replacement unit 1220 transmits the data signal RD received by the interface unit 1100 (see FIG. 4) by replacing the clock with the clock SC generated by the stabilization clock generation unit 1210 (see FIG. 4). Is for. The clock replacement unit 1220 can be configured as shown in FIG. 11, for example.
[0039]
In FIG. 11, the clock rearrangement unit 1220 includes a bit buffer unit 1222 for temporarily storing a data signal, a write control unit 1224 for controlling an address at which the data signal is written to the bit buffer unit 1222, and a data signal. Read control unit 1226 for controlling the address from which the bit buffer unit 1222 is read, and a phase monitoring unit 1228 for monitoring the phase difference between the write control unit 1224 and the read control unit 1226 so that no slip occurs. Configured.
[0040]
The bit buffer unit 1222 has a store memory function and can access data for each address. That is, given data can be stored at a designated address, and data stored at a designated address can be read.
[0041]
The write control unit 1224 includes a write address counter 1225 (Write-in Address Counter, hereinafter referred to as WAC) that operates according to the clock signal RC extracted by the clock extraction unit 1120. Then, the extracted clocks are counted, and an address corresponding to the counted value is designated in the bit buffer unit 1222.
[0042]
The read control unit 1226 includes a read address counter 1227 (Read-out Address Counter, hereinafter referred to as RAC) that operates according to the in-device clock generated by the stabilization clock generation unit 1210. Then, the internal clock is counted, and an address corresponding to the counted value is designated in the bit buffer unit 1222.
[0043]
The phase monitoring unit 1228 is for performing control for preventing a slip phenomenon. That is, the phase difference between the write control unit 1224 and the read control unit 1226 is monitored, and when this phase difference becomes larger than a predetermined value, the read control unit 1226 and the synchronization signal detection unit 1230 Then, a predetermined control for returning the clock synchronization is performed.
[0044]
With reference to FIG. 5 and FIG. 11, an operation of changing the clock of the data signal in the clock changing unit 1220 will be described. In the clock rearrangement unit 1220, the address is specified by the WAC 1225 according to the extracted clock RC and is written into the bit buffer unit 1222, and this is read from the bit buffer unit 1222 at the address specified by the RAC 1227 according to the stabilization clock SC. The clock of the data signal is transferred from the extracted clock RC to the stabilized clock SC.
[0045]
First, a data signal is given as shown in FIG. 5A, and an extraction clock RC used as a write clock is given as shown in FIG. 5B.
[0046]
The WAC 1225 operates in accordance with the clock extracted from the clock extraction unit 1120 and designates the write address as shown in FIG. Data is latched and written at the rising edge of the extracted clock RC. For example, as shown in FIG. 5D, when the WAC 1225 designates the first address, the data is written in the storage area where the first address of the buffer memory unit 1220 is defined. Hereinafter, data is written in a storage area in which addresses designated in order of No. 2, No. 3, No. 4,... Are defined.
[0047]
On the other hand, the stabilized clock SC generated by the stabilized clock generator 1210 is given to the RAC 1227 as a read clock shown in FIG. The RAC 1227 operates in accordance with the stabilization clock and designates the read address as shown in FIG. Data is latched and read at the rising edge of the read clock (stabilized clock SC). For example, when the RAC 1227 designates the first address, the data stored in the storage area where the first address of the buffer memory unit 1220 is defined is read. Hereinafter, data stored in a storage area in which addresses designated in order of No. 2, No. 3, No. 4,... Are defined is read as shown in FIG.
[0048]
As for the phase where the read address No. 1 (No. 2, No. 3, No. 4, etc.) is specified, the No. 1 of the write clock (No. 2, No. 3, No. 4, etc.) must be sufficiently specified Is set to the assumed phase. That is, it is set in advance in consideration of jitter that is assumed to be included in the extracted clock used as the write clock. Thereby, the written data can be reliably read out. For example, as shown in FIGS. 5C and 5F, the designation of the read address can be set delayed by one clock from the designation of the write address. More specifically, for example, a description of the phase delayed corresponding to the expected jitter with respect to the phase at which the downlink data signal shown in FIG. 5A arrives (that is, the phase of the extracted clock). An embedded clock can be generated as shown in FIG. 5B, and a read clock whose phase is delayed by one clock relative to the write clock can be generated as shown in FIG.
[0049]
Next, the synchronization signal detection unit 1230 will be described. The synchronization signal detection unit 1230 is for detecting a frame synchronization signal indicating the frame reference position from the downlink data signal. As shown in FIG. 4, the synchronization signal detection unit 1230 is arranged in the subsequent stage by the clock replacement unit 1220. Then, the frame synchronization signal is detected from the data signal TD on which the clock is replaced, and the detection signal DS is transmitted when it is detected.
[0050]
The synchronization signal detector 1230 having the above function can be configured as shown in FIG. 12, for example. In FIG. 12, a synchronization signal detector 1230 compares a bit pattern with each other, a data reader 1232 for reading a bit pattern from a given data signal TD, a memory 1235 for storing a bit pattern in advance, and the like. And a comparator 1234 for sending a detection signal DS when the two coincide with each other.
[0051]
Next, the delay time setting unit 1240 will be described. The delay time setting unit 1240 sets a delay time DT of a data signal transmission timing (signal transmission phase) with respect to the timing at which the synchronization signal detection unit 1230 detects the frame synchronization signal, and delays the set delay time DT. This is for instructing the amount adjusting unit 1250.
[0052]
The delay time setting unit 1240 having a function of dynamically obtaining second time information indicating a propagation time during which an optical signal propagates between a station device and a home device can be configured as shown in FIG. 13, for example. .
[0053]
The delay time setting unit 1240 in this configuration example includes, for example, a reception side frame counter 1242 for counting the number of clocks from the arrival of the frame synchronization signal to the transmission of the burst signal, and the transmission of the burst signal and the next Frame counter 1244 for counting the number of clocks until the frame synchronization signal arrives, an arithmetic circuit 1248 for determining the number of clocks of the delay time to be delayed, and an offset holding register for holding the delay time 1246 can be configured.
[0054]
The arithmetic circuit 1248 stores the response delay time in the station apparatus 18 (see FIG. 1) in advance. Then, the station apparatus 18 (see FIG. 1) is transmitted after the burst signal is transmitted by subtracting the previously stored response delay time from the number of clocks counted by the transmission side frame counter 1244 and dividing the remainder by 2. It is possible to obtain a delay time until arrival at the time, that is, second time information. The reason for dividing by 2 is that the number of clocks counted corresponds to the time required for the data signal to reciprocate through the optical fiber transmission line. Then, the time obtained by subtracting the second time information from the first time information is obtained as the number of clocks to be delayed. The obtained clock number is held in the offset holding register 1246. The reception side frame counter 1242 obtains the number of clocks held in the offset holding register 1246 after the frame synchronization signal is detected by the synchronization signal detection unit 1230, and obtains the phase at which the burst signal should be transmitted.
[0055]
Next, the delay amount adjustment unit 1250 will be described with reference to FIG.
[0056]
The timing (signal transmission phase) at which the data signal D supplied from the data processing unit 1400 (see FIG. 4) is transmitted is delayed by the delay time DT instructed from the delay time setting unit 1240 to obtain a delayed data signal DD. It is for sending out.
[0057]
The delay amount adjustment unit 1250 can be configured as shown in FIG. 14, for example. In FIG. 14, a delay amount adjustment unit 1250 includes a bit buffer unit 1252 for temporarily storing a data signal, a write control unit 1254 for sequentially writing the applied data signal to the bit buffer unit 1254 bit by bit, The read control unit 1256 for sequentially reading the data signal stored in the bit buffer unit 1252 bit by bit, the timing at which the read control unit 1256 reads the data signal, and the write control unit 1254 writes the data signal A clock shifter 1258 for delaying the timing by a clock corresponding to the given delay time is configured. The writing of the data signal and the reading of the data signal in the bit buffer unit 1252 can be performed in the same procedure as the clock switching unit 1220. However, the delay amount adjustment unit 1250 is different in that the data signal is read at a timing delayed by the clock instructed by the clock shifter.
[0058]
Next, the termination circuit unit 1300 will be described with reference to FIG.
[0059]
The termination circuit unit 1300 includes a serial / parallel conversion unit 1320 for converting the data signal TD supplied from the clock stabilization unit 1200 (see FIG. 4) into a parallel signal PD, and a data processing unit 1400 (see FIG. 4). A parallel / serial conversion unit 1340 for converting a given data signal PD into a serial signal D and termination circuits 1325 and 1345 connected to the respective conversion units are configured. Thus, a serial signal can be used for data transmission with the station device 18 and a parallel signal can be used for data transmission with the data processing unit 1400.
[0060]
Next, with reference to FIG. 4 and FIGS. 9-15, operation | movement of the household device 1000 comprised as mentioned above is demonstrated.
[0061]
First, an operation for receiving a downlink data signal transmitted from the station apparatus 18 (see FIG. 1) will be described. The home device 1000 operates using the stabilized clock SC generated by the stabilized clock generator 1210 as the in-device clock. For this reason, the clock of the transmitted downstream data signal OD is transferred to the stabilized clock SC by the clock changing unit 1220 and used by the processing device 1400.
[0062]
The in-home device 1000 receives a downlink data signal from the station device 18 (see FIG. 1) as an optical signal via the optical fiber transmission line 17. In the interface unit 1100, the downlink data signal is sent as an optical signal OD and converted into an electric signal RD by the optical / electrical converter 1110. Also, the clock signal RC is extracted by the clock extraction unit 1120 from the downlink data signal RD converted into the electrical signal. The downlink data signal RD converted to the electrical signal and the extracted clock signal RC are sent to the clock stabilization unit 1200, respectively.
[0063]
The extracted clock signal RC is input to the stabilization clock generation unit 1210 as a reference signal in the clock stabilization unit 1200. The stabilized clock generator 1210 generates a stabilized clock signal SC that is synchronized with the extracted clock signal RC and has reduced jitter. The generated stabilized clock signal SC is used as an in-device clock.
[0064]
On the other hand, the data signal RD is transferred to the stabilized clock SC by the clock changing unit 1220. The data signal TD transferred to the stabilization clock SC is sent to the synchronization signal detection unit 1230 and the termination circuit unit 1300, respectively.
[0065]
The data signal TD sent to the termination circuit unit 1300 is converted from a serial signal to a parallel signal in the serial / parallel conversion unit 1320. The data signal PD converted into the parallel signal is sent to the data processing unit 1400 and used.
[0066]
Next, an operation for sending a burst signal to the station apparatus 18 (see FIG. 1) will be described. The home device 1000 transmits the data signal PD from the processing device unit 1400 to the station device 18 as a burst signal. At this time, the phase at which the data signal is transmitted is controlled so that the timing at which the burst signal arrives at the station device 18 (see FIG. 1) enters the time slot assigned to the in-home device. The phase control is performed with reference to the frame synchronization signal included in the downlink data signal TD replaced with the stabilization clock.
[0067]
The delay time setting unit 1240 propagates the first time information indicating the phase difference between the frame synchronization signal and the start point of the time slot assigned to the in-home device 1000, and the optical signal between the station device and the in-home device. Second time information indicating the propagation time is given. The delay time setting unit 1240 sets a delay time from the reception of the frame synchronization signal to the transmission of the burst signal based on the assigned time slot and the given propagation time.
[0068]
The first time information has a predetermined value based on the path length of the optical fiber transmission path 17. This may be stored in advance in the delay time setting unit 1240, or the value assigned by the station device 18 (see FIG. 1) may be dynamically acquired.
[0069]
The second time information may be a value obtained by the station device from the station device 18 (see FIG. 1), or may be obtained dynamically by the delay time setting unit 1240. In order to obtain the second time information, for example, the time from when the burst signal is transmitted until the frame synchronization signal arrives is measured, and can be obtained based on this. At this time, the phase (timing) of the detection signal DS indicating that the synchronization signal detection unit 1230 has detected the frame synchronization signal can be used. As a result, the phase of the frame synchronization signal included in the data signal TD replaced with the stabilization clock SC used as the in-device clock can be used as a reference. In other words, fluctuations in the arrival phase of the frame synchronization signal can be avoided and used as a reference for the signal transmission phase. Therefore, the accuracy for obtaining the second time information can be improved.
[0070]
The delay amount adjusting unit 1250 receives the delay time set by the delay time setting unit 1240 and delays the phase at which the burst signal is transmitted by the delay time. The phase delay can be performed in steps of this clock according to the stabilization clock SC used as the in-device clock. By using the stabilization clock SC, it is possible to reduce the variation in the step of the phase delay and to set the step size to the same clock cycle as that of the received downlink data signal.
[0071]
The burst signal DD whose transmission phase has been adjusted by the delay amount adjustment unit 1250 is sent to the interface unit 1100. The burst signal converted into the optical signal OD in the interface unit 1100 is sent to the optical fiber transmission line 17.
[0072]
As described above, the delay time setting unit 1240 and the delay amount adjustment unit 1250 perform processing on the data signal TD that has been replaced with the in-device clock by the clock replacement unit 1220. Both can be clocks stabilized. That is, it is possible to realize both the clocks in common and to stabilize the clocks on which they operate.
[0073]
By sharing the clock, it is possible to avoid the difficulty of clock transfer without reducing the clock speed of the clock for controlling the signal transmission phase. Therefore, the signal transmission phase can be controlled in fine steps, and the control accuracy can be improved.
[0074]
In addition, by using a stabilized clock as the clock for operating the circuit, it is possible to reduce jitter contained in the burst signal to be transmitted and to reduce fluctuations in the signal transmission phase, thereby improving control accuracy. Can be improved.
[0075]
Since the two effects of finely controlling the steps and reducing the fluctuation of the phase to be controlled are synergistic, the operation of improving the accuracy of the signal transmission phase in the in-home device 1000 to which the present invention is applied. Is remarkable.
[0076]
It should be noted that the propagation time for the data signal to propagate through the optical fiber transmission line, the propagation time when the PDS transmission system is not operated, and the response immediately before the transmission each time a burst signal is transmitted when the PDS transmission system is operated. The propagation time can be obtained for the received signal.
[0077]
Then, the temporal variation of the propagation time may be obtained based on the propagation time obtained during the non-operation. Then, in response to the first propagation time, an instruction to delay the signal transmission timing is given to the data processing unit 1400, and the delay variation corresponding to the propagation time variation is given by the delay amount adjusting unit 1250. Also good. Thereby, the delay amount to be delayed by the delay amount adjustment unit 1250 can be limited to the variation over time, and can be reduced as compared with the case where the entire delay is performed. That is, the memory capacity (capacity of the bit buffer unit 1252) that the delay amount adjustment unit 1250 should have can be reduced. Therefore, the delay amount adjusting unit 1250 can be configured in a small and economical manner. However, the delay amount adjusting unit 1250 can only adjust the timing of sending the data signal in the direction of delaying. However, when the delay amount is set in this way, the delay amount to be delayed by the delay amount adjustment unit 1250 can be either positive or negative. Accordingly, by reducing the delay amount corresponding to about half the maximum delay amount that can be delayed by the delay amount adjustment unit 1250 from the value instructed to the data processing 1400, not only the timing but also the timing is advanced. Therefore, it is possible to cope with the fact that the delay amount is in both positive and negative directions.
[0078]
In this way, by dynamically acquiring the second time information, it is possible to cope with a change in the propagation time due to a change in the transmission line length and a change in the transmission speed in the optical fiber transmission line. Can do. For this reason, it becomes possible to cope with the long-term operation of the PDS transmission system, the operation in an environment with a large change, and the transmission path being stretched with a large tension.
[0079]
Here, the relationship between the clock speed of the in-device clock and the accuracy with which the signal transmission phase is controlled will be described with reference to FIGS.
[0080]
First, a case where the delay time setting unit 1240 operates at a clock speed corresponding to the clock speed (line clock speed) of the downlink data signal received will be described.
[0081]
As shown in the signal waveform of FIG. 6A, a pulse signal indicating that the frame synchronization signal has been detected is sent from the synchronization signal detection unit 1230 to the reception-side frame counter 1230.
[0082]
The reception-side frame counter 1242 starts counting the clocks starting from the rising edge of the pulse sent from the synchronization signal detection unit 1230, and sequentially sends the counted value to the arithmetic circuit 1248 as shown in FIG. 6B. Output.
[0083]
The arithmetic circuit 1248 obtains the clock number of the delay amount d1 corresponding to the delay time to be delayed, and sequentially compares the obtained clock number of the delay amount d1 with the numerical value sent from the reception side frame counter 1242. When these values match, a trigger signal is sent to the transmission side frame counter 1244 and the delay amount adjustment unit 1250 as shown in FIG.
[0084]
The transmission-side frame counter 1244 starts counting the clock with the trigger signal as a start, and continues counting sequentially as shown in FIG.
[0085]
When the trigger signal is sent from the arithmetic circuit 1248, the delay amount adjustment unit 1250 starts sending burst signals, and the data is sent to the electrical / optical conversion unit as shown in FIG. 6 (h). 1130.
[0086]
On the other hand, in the case where the delay time setting unit 1240 operates at a clock speed corresponding to half of the clock speed of the received downlink data signal, the delay time setting unit 1240 similarly applies to (e) to (g) of FIG. Signals are sent and received as shown. However, the clock speed of the clocks counted by the reception side frame counter 1242 and the transmission side frame counter 1244 is halved, the phase interval at which the counted values are transmitted is doubled, and the arithmetic circuit The difference is that the number of clocks of the delay amount d2 obtained by 1248 is half the number of clocks of the delay amount d1 described above.
[0087]
Therefore, in the latter case, the phase at which the arithmetic circuit 1248 can send the trigger signal is limited to the phase at which the reception side frame counter 1242 sent at a phase interval twice that of the former sends the numerical value. That is, the smallest phase step that can be controlled is twice as large.
[0088]
In terms of a specific signal speed, assuming that the clock speed (line clock speed) of the received downlink data signal is 150 Mb / sec, one period is 6.4 nsec. By setting the internal clock at the clock speed corresponding to the line clock speed, the delay amount adjusting unit 1250 can transmit the burst signal with the phase a shown in FIG.
[0089]
However, when the divided clock is used as the in-device clock, the clock speed is reduced to ½. In this numerical example, the clock speed is 75 Mb / sec. That is, one cycle is 12.8 nsec. From this, the controllable phase interval is 12.8 nsec, which is larger than the former case. Therefore, the delay amount adjustment unit 1250 transmits a burst signal with the phase A shown in (i) of FIG. Therefore, in the latter case, a phase error of δ shown in (i) of FIG. 6 occurs with respect to the phase a in the former case.
[0090]
As described above, the in-home device 1000 to which the present invention is applied includes the clock replacement unit 1200 before the frame synchronization unit 1230, the delay time setting unit 1240, and the delay amount adjustment unit 1250. As a result, the clock speed of the in-device clock can be matched with the line clock speed. Therefore, it is possible to avoid the occurrence of a phase error in the signal transmission phase due to the slow clock speed of the in-device clock described above.
[0091]
Next, a second embodiment of the present invention will be described with reference to FIGS. The present embodiment is an example of a remote concentrator in a data transmission system configured with a PDS transmission system.
[0092]
In the description of the first embodiment, the case has been described in which the slave device connected to the main device is deployed in a place where the transmitted data is used. As a usage form of such a subordinate device, for example, a home device deployed in a home or each department in a company can be cited. However, the aspect of the subordinate apparatus to which the present invention is applied is not limited to this. For example, it may be provided between the station device and the home device. More specifically, it can be used as a relay device for connecting a home device to each transmission path connected to the station device, a remote concentrator for connecting a plurality of home devices for each transmission path, etc. .
[0093]
Below, the form utilized as a remote concentrator is demonstrated.
First, a configuration example of a transmission system to which the remote concentrator of this embodiment is applied will be described with reference to FIG. In FIG. 7, the transmission system includes a station device 18 and N remote concentrators 2000 (1) to (N) connected by the optical star coupler 20, and respective remote concentrators 2000 (n) (where n is , N integers 1, 2, 3,..., N, respectively). _n Premises equipment 3000 (n, 1) to (n, L _n ).
[0094]
The station apparatus 18 and the optical star coupler 20 are connected by the optical fiber transmission line 16, and the N indoor devices 1000 (1) to (N) and the optical star coupler 20 are connected to the N optical fiber transmission lines 17 (1 ) To (N). Each remote concentrator 2000 (n) includes L _n Premises equipment 3000 (n, 1) to (n, L _n ) But L _n Transmission lines 15 (n, 1) to (n, L _n ), Respectively.
[0095]
Number L of in-home devices 3000 connected to each remote concentrator 2000 (n) _n Can be selected independently for each remote concentrator. In particular, L _n 1 is equivalent to using the remote concentrator as a relay device.
[0096]
Each remote concentrator 2000 (n) and in-home devices 3000 (n, 1) to (n, L) connected thereto _n ) Are respectively connected to the transmission lines 15 (n, 1) to (n, L _n For example, an optical fiber transmission line or an electric conductor transmission line can be used. By adopting a transmission line using an electric conductor, connection, removal, and reconnection of the transmission line can be easily performed as compared with the optical fiber transmission line. Therefore, for example, an optical fiber can be used for a long-distance main line transmission line, and an electric conductor can be used for the transmission line branched to each in-home device. That is, an optical fiber excellent in noise resistance and data transmission density and an electric conductor that can be easily inspected and connected can be used depending on the use of the transmission line.
[0097]
The remote concentrator can be provided, for example, in a wiring groove or a wiring duct. When it is provided in the wiring groove, it is provided near the manhole so that access to the remote concentrator is facilitated during maintenance inspection. In addition, you may make a housing | casing into a structure which has weather resistance, and may provide in ground facilities, for example, a utility pole, an eaves tip, etc.
[0098]
Next, the configuration of the remote line concentrator 2000 (n) will be described with reference to FIG. In FIG. 8, a remote concentrator 2000 (n) includes an interface unit 1100 for transmitting / receiving data signals to / from the outside, a clock stabilizing unit 1200 for stabilizing the clock of the data signals, and the data signals to the in-home device 3000. A distributor unit 1500 for distributing the data signal to the distributor unit 1500 and a termination circuit unit 1300 for transmitting and receiving the data signal to the distributor unit 1500. The remote line concentrator 2000 in the present embodiment is different from the in-home apparatus in the first embodiment described above in that it does not have the data processing unit 1400 and has the distributor unit 1500. Other blocks, that is, the interface unit 1100, the clock stabilization unit 1200, and the termination circuit unit 1300 can be configured in the same manner as the corresponding blocks of the in-home device in the first embodiment. Therefore, repeated description of these blocks is omitted.
[0099]
Remote concentrator 2000 (n) and in-home devices 3000 (n, 1) to 3000 (n, L _n ), The termination circuit unit 1300 can be omitted.
[0100]
The distributor unit 1500 converts the data received from the station device 18 (see FIG. 7) into the connected home devices 3000 (n, 1) to 3000 (n, L). _n ) And in-home devices 3000 (n, 1) to 3000 (n, L _n ) Are multiplexed for transmission to the station device 18 (see FIG. 7). For example, it can be configured using a repeater hub that transmits data received at a certain port to another port. Moreover, you may comprise using the switch hub provided with the exchange function.
[0101]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the precision with which the signal transmission phase from which the burst signal transmitted from a subordinate apparatus is transmitted to a main apparatus is controlled can be improved.
[0102]
As a result, the gate time can be set short while the collision between the burst signals is suppressed. Therefore, it is possible to effectively use time slot resources in the PDS transmission system and improve data transmission efficiency.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a configuration example of a PDS transmission system.
FIG. 2 is an explanatory diagram showing a transmission structure of a downlink data signal in a PDS transmission system.
FIG. 3 is an explanatory diagram showing a transmission structure of an uplink data signal in a PDS transmission system.
FIG. 4 is a block diagram showing an example of a home device to which the present invention is applied.
FIG. 5 is a timing chart showing an operation phase in which a clock of a data signal is replaced.
FIG. 6 is a timing chart showing an operation phase for controlling a signal transmission phase.
FIG. 7 is a configuration diagram illustrating a configuration example of a transmission system having a PDS transmission system.
FIG. 8 is a block diagram showing an example of a remote concentrator to which the present invention is applied.
FIG. 9 is a block diagram illustrating a configuration example of an interface unit.
FIG. 10 is a block diagram illustrating a configuration example of a stabilization clock generation unit.
FIG. 11 is a block diagram illustrating a configuration example of a clock replacement unit.
FIG. 12 is a block diagram illustrating a configuration example of a synchronization signal detection unit.
FIG. 13 is a block diagram illustrating a configuration example of a delay time setting unit.
FIG. 14 is a block diagram illustrating a configuration example of a delay amount adjustment unit.
FIG. 15 is a block diagram illustrating a configuration example of a termination circuit unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Downlink data signal, 2 (1)-(N) ... Branched downlink data signal, 3 (1)-(N) ... Burst signal, 4 ... Uplink data signal, 15 (n, 1)-(n, L _n ) ... transmission path, 16, 17 (1) to (N) ... optical fiber transmission path, 18 ... station apparatus, 20 ... optical star coupler, 1000 (1) to (N) ... in-home equipment, 1100 ... interface section, 1110 ... Optical / electrical conversion unit, 1120 ... Clock extraction unit, 1130 ... Electric / optical conversion unit, 1200 ... Clock stabilization unit, 1210 ... Stabilized clock generation unit, 1212 ... Voltage controlled oscillator, 1214 ... Phase comparator, 1216 ... Low-pass filter, 1220... Clock replacement unit, 1222... Bit buffer unit, 1224... Write control unit, 1225... Write address counter (WAC), 1226. 1228: Phase monitoring unit, 1230 ... Synchronization signal detecting unit, 1232 ... Data reader, 1234 ... Comparator, 1235 ... Memory, 1240 Delay time setting unit, 1242 ... reception side frame counter, 1244 ... transmission side frame counter, 1246 ... offset holding register, 1248 ... arithmetic circuit, 1250 ... delay amount adjustment unit, 1252 ... bit buffer unit, 1254 ... write control unit, 1246: Read control unit, 1258 ... Clock shifter, 1300 ... Termination circuit unit, 1320 ... Series / parallel conversion unit, 1325 ... Termination circuit, 1340 ... Parallel / serial conversion unit, 1345 ... Termination circuit, 1400 ... Data processing unit, 1500 ... distributor unit, 2000 (1) to (N) ... remote concentrator, 3000 (n, 1) to (n, L) _n ) {N | 1, 2, 3,..., N}.

Claims (5)

The main device is used in a PDS (Passive Double Star) transmission system for transmitting data between the main device and a plurality of subordinate devices connected to the main device via a transmission path. In the subordinate apparatus for receiving the downlink data signal including the synchronization signal from and transmitting the burst signal constituting the uplink data signal to the main apparatus,
A stabilized clock generator that references a downlink data signal received from the main device and generates a stabilized in-device clock from a clock signal included in the downlink data signal;
A clock re-sending unit that re-sends the received downlink data signal to the in-device clock;
A synchronization signal detection unit for detecting a synchronization signal from the downlink data signal transferred to the in-device clock;
By measuring the time interval from the transmission of the burst signal to the reception of the data signal using the internal clock, the propagation time required for the optical signal to propagate between the slave device and the main device is calculated, A delay time setting unit for setting a delay time from receiving a downlink data signal to transmitting a burst signal using the propagation time;
A delay amount adjusting unit that adjusts the phase for transmitting the burst signal to the main device to the phase that has passed the delay time since the synchronization signal was detected, using the internal clock
The subordinate apparatus, wherein the delay time setting unit calculates the propagation time using the number of clocks of the in-apparatus clocks counted from transmission of a burst signal to detection of the synchronization signal . In claim 1,
At least one in-home device that can use the transmitted data is connected, and a distributor is provided for distributing received data signals to the in-home devices and collecting data signals received from the in-home devices. A subordinate device characterized by that. In claim 1 or 2,
The subordinate apparatus, wherein the stabilization clock generation unit generates a clock signal in which intervals between clock pulses are averaged for a clock signal included in the downlink data signal. In claim 3,
The dependent device, wherein the stabilization clock generation unit is a phase-locked oscillator that oscillates with reference to a clock signal included in the downlink data signal. One main device is used in a PDS (Passive Double Star) transmission system for transmitting data between the main device and a plurality of subordinate devices, receives a downlink data signal including a synchronization signal from the main device, and In the clock synchronization method in the subordinate apparatus for transmitting the burst signal constituting the upstream data signal to the main apparatus,
The slave device is
A clock generation step of referring to a downlink data signal received from the main device and generating a stabilized in-device clock from a clock signal included in the downlink data signal;
The downlink data signal thus received and loaded replacement step Ru reloading the device clock generated above,
A detection step of detecting a frame synchronization signal included in the downlink data signal transferred to the in-device clock;
A calculation step of calculating a propagation time required for the optical signal to propagate between the slave device and the main device by measuring a time interval of transmission and reception of the data signal;
A setting step for setting a delay time from reception of a downlink data signal to transmission of a burst signal using the propagation time;
A transmission step of transmitting a burst signal to the main unit at a timing when the delay time has elapsed since the synchronization signal was detected ;
Run
The calculation step is
A clock synchronization method characterized in that the propagation time is calculated using the number of clocks of the in-device clock counted from transmission of a burst signal to detection of the synchronization signal .

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