JP3719902B2 - Memory circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory circuit, and particularly to a mask ROM (Read
(Only Memory) circuit.
[0002]
[Prior art]
Some conventional memory circuits write memory data to a memory cell by determining whether or not to connect the memory cell to a bit line using a mask pattern. Taking the conventional mask ROM shown in FIG. 2 as an example, the configuration of the memory circuit and the method for writing and reading stored data will be described.
[0003]
The memory circuit shown in FIG. 2 is called a NOR type mask ROM, and includes a data storage unit 1 composed of a memory cell array, a column selector 2, and a read circuit 3. The broken-line arrows written in the data storage unit 1 and the column selector 2 indicate a situation where the circuit is expanded as the scale of the memory circuit increases.
[0004]
The memory cell array of the data storage unit 1 is composed of cell transistors 5 arranged in a matrix in the row and column directions, and the gates of the cell transistors 5 are connected to each other in the row direction so that the word lines of the memory cell array 6 is formed. The drains of the cell transistors 5 arranged along the column direction are connected in parallel to the bit lines 9, respectively, and the sources are all grounded. In this way, a NOR type mask ROM memory cell array is formed.
[0005]
The column selector 2 includes a selection transistor 7 whose source is connected to the end of each bit line 9 and a selection control line 8 whose gates of adjacent selection transistors 7 are connected to each other. Are connected to the readout circuit 3. Note that the output of the row decoder 19 is connected to the word line 6 of the memory cell array constituting the data storage unit 1, and the output of the column decoder 20 is connected to the selection control line 8 of the column selector 2.
[0006]
The read circuit 3 forms a precharge transistor 10 for connecting the bit line 9 of the memory cell array of the data storage unit 1 to the precharge power supply 12, a precharge control line 11 connected to the gate thereof, and an output amplifier for the read signal. And an inverter 13.
[0007]
In the NOR type mask ROM, the write state of the stored data to the cell transistor 5 in the data storage unit 1 is defined as follows. That is, the write state of “0” data is defined by connecting the drain of the cell transistor 5 to the bit line 9, and the write state of “1” data is not connecting the drain of the cell transistor 5 to the bit line 9. Is defined by
[0008]
Therefore, storage data to be written in the data storage unit 1 is formed in advance on the mask pattern as an array of aluminum wiring, contacts, vias, etc., and the connection between the drain of the cell transistor 5 and the bit line 9 using a photo process, or If non-connection is determined, predetermined “0” and “1” data are written in the memory cell array constituting the data storage unit 1.
[0009]
Next, a method for reading data written in the data storage unit 1 will be described. First, the bit line 9 corresponding to the cell transistor 5 selected as a read target is precharged. As described above, the output of the row decoder 19 is connected to the word line 6 of the memory cell array, and the output of the column decoder 20 is connected to the selection control line 8 of the column selector 2.
[0010]
During the precharge period, the bit line 9 (BL1) corresponding to the cell transistor 5 (A1) selected as the read target is received via the selection transistor 7 of the column selector 2 in response to the output of the column decoder 20 shown in FIG. The bit line BL1 is connected to the precharge power supply 12 via the precharge transistor 10 to precharge the bit line BL1.
[0011]
During this precharge period, the timing waveform of the read operation is set so that the output voltages of the row decoder 19 and the column decoder 20 are fixed. That is, during the precharge period, in response to the output high level of the column decoder 20, the gate of the selection transistor 7 becomes high level, and the bit line BL1 is connected to the precharge power supply 12. Further, all output voltages of the row decoder 19 become low level, and all the cell transistors 5 connected to the bit line BL1 are not selected (off state) in response to the output low level of the row decoder 19.
[0012]
When this precharge period ends, the discharge period starts next. In the discharge period, the gate of the cell transistor A1 selected as a read target connected to the word line 6 (WL1) selected by the row decoder 19 in the memory cell array of the data storage unit 1 is at a high level, and other read unselected The word line 6 connected to the gate of the cell transistor 5 becomes low level. Similarly, with respect to the gate of the selection transistor 7 of the column selector 2, the gate of the selection transistor 7 corresponding to the bit line BL1 selected by the column decoder 20 is at the high level, and the selection corresponding to the other bit line 9 that is not selected for reading. The gate of the transistor 7 is at a low level.
[0013]
Thus, for example, out of the memory cell array in the data storage unit 1
If the cell transistor A1 in which "0" data is written is selected, the cell transistor A1 is turned on because the drain of the cell transistor A1 is connected to the selected bit line BL1 as described above. As a result, the precharge voltage of the selected bit line BL1 is grounded and discharged through the source terminal of the cell transistor A1.
[0014]
If "1" data is written in the selected cell transistor A1, the drain of the transistor A1 is not connected to the selected bit line BL1, so that even if the cell transistor A1 is turned on, the bit line BL1 is turned on. The precharge voltage is maintained for a certain time.
[0015]
The problem here is that “1” data is written in the cell transistor A1 selected as the object of reading in this way, and its drain terminal is not connected to the selected bit line BL1, so that the cell This is a case where the precharge voltage of the selected bit line BL1 is held for a certain time even when the transistor A1 is turned on.
[0016]
In an actual memory circuit, there are many read unselected cell transistors 5 for the selected bit line BL1, and "0" data is written in some of these read unselected cell transistors 5. For example, even if they are in an off state, a minute leak current flows through the source / drain junction, so that the precharge voltage of the selected bit line BL1 is discharged through these read unselected cell transistors 5. This causes a problem that a certain holding time required for reading is shortened.
[0017]
Usually, since the leakage current at the source / drain junction of one transistor is negligibly small, the precharge voltage holding time is not greatly affected. If the number of cell transistors 5 connected to the bit line BL1 is increased, the sum of the leakage currents of the source / drain junction becomes a value that cannot be ignored.
[0018]
In particular, when the memory circuit is operated at a low speed, the precharge voltage of the selected bit line BL1 is required to have a long holding time. When the memory circuit is operated dynamically, the limit of the low speed operation is this holding time. It will be determined depending on. In other words, if the discharge amount of the bit line BL1 due to the sum of the leak currents (hereinafter referred to as the leak amount) becomes large, the precharge voltage of the bit line BL1 is reduced before the retention time necessary for the dynamic read operation of the memory circuit. Since the battery is discharged, the “1” data written in the cell transistor A1 is erroneously read as “0” data, resulting in a malfunction of the memory circuit.
[0019]
As a result, in a large-capacity memory circuit, a slight variation in the amount of leakage that can be ignored in a normal circuit due to slight fluctuations in the manufacturing process will lead to defective products, resulting in a significant reduction in manufacturing yield. become.
[0020]
Furthermore, in order to guarantee the low-speed operation of the memory circuit, the non-defective / defective product is determined depending on the leak amount as described above. Therefore, in order to guarantee the 32 kHz operation, for example, read evaluation at 30 kHz must be performed. Don't be. In addition, since it is impossible to predict where and where this leakage current will occur in the memory circuit, this evaluation must be performed over the entire data storage unit 1 of the memory circuit. The test time required for this is, for example, in a 256 kbyte ROM.
If you read in bytes,
0.033 msec × 256 × 1024 = 8.65 sec (1)
This requires a huge amount of test time. Even if it has a 32-bit configuration, 2.16 sec is required, which causes an increase in cost.
[0021]
[Problems to be solved by the invention]
As described above, the conventional large-capacity memory circuit such as a mask ROM has a problem that a slight variation in the amount of leakage leads to the generation of defective products, thereby reducing the manufacturing yield. In addition, since the fluctuation of the leak amount has a great influence on the low-speed operation of the memory circuit in particular, an enormous amount of test time is required to guarantee the low-speed operation, which causes an increase in the cost of a large capacity memory circuit such as a mask ROM. It was.
[0022]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory circuit that can guarantee low-speed operation in a short time without adversely affecting high-speed operation.
[0023]
[Means for Solving the Problems]
A memory circuit according to the present invention includes a voltage holding circuit for a precharge voltage capable of guaranteeing a low-speed operation in a short time, a control signal input terminal for controlling the operation, and a test control circuit. .
[0024]
Specifically, the memory circuit of the present invention is a memory circuit including a read circuit including a voltage holding circuit that holds a precharge voltage, and the voltage holding circuit is configured to operate in the low-speed operation of the memory circuit. And a control signal input terminal for prohibiting the operation of the voltage holding circuit in the high-speed operation of the memory circuit, and selecting all the columns of the memory cell array in the low-speed test mode operation, A test control circuit for controlling the column decoder and the row decoder so as to be selected is provided.
[0025]
Preferably, the voltage holding circuit includes a hold transistor that holds the precharge voltage, a source of the hold transistor is connected to a source of the precharge transistor, and a connection point between the sources is a drain of a selection transistor that forms a column selector. The drain of the hold transistor is connected to the drain of the precharge transistor, and the connection point between the drains is connected to a precharge power source.
[0026]
Preferably, in the low speed operation of the memory circuit, a slow mode input signal having a first voltage level is input to the control signal input terminal of the voltage holding circuit, and the output of the voltage holding circuit is received in response to the slow mode input signal. Turns on a hold transistor that holds the precharge voltage, and the precharge power supply and the bit line are connected by the hold transistor in the on state, so that the precharge voltage precharged on the bit line is reduced. Retained,
In the high-speed operation of the memory circuit, a slow mode input signal having a second voltage level is input to the control signal input terminal of the voltage holding circuit, and the output of the voltage holding circuit is received by the slow mode input signal. The hold transistor holding a precharge voltage is turned off, and the precharge power supply and the bit line are shut off by the hold transistor in the off state.
[0027]
More preferably, the hold transistor in the voltage holding circuit is a P-channel transistor, the voltage holding circuit includes at least a NAND gate circuit, and the NAND gate circuit is a two-input NAND gate circuit, and one input thereof The terminal is an inverting input terminal,
The voltage holding circuit further includes an inverter, a source of the P-channel transistor is connected to an input terminal of the inverter, an output of the inverter is connected to the one inverting input terminal of the two-input NAND gate circuit, A slow mode input signal is input to the other input terminal of the NAND gate circuit forming the control signal input terminal of the voltage holding circuit, the output terminal of the NAND gate circuit is connected to the gate of the P channel transistor, and the P channel The drain of the type transistor is connected to a precharge voltage.
[0028]
Preferably, a drain current in an on state of the hold transistor that holds the precharge voltage is larger than a sum of leak currents of the cell transistors that form the memory cell array, and any one of the memory cell arrays is formed. The drain current is smaller than that in the on state of the cell transistor.
[0029]
Preferably, the test control circuit of the column decoder and the row decoder is configured such that the output of the column decoder selects all the selection transistors of the column selector when the test signal of the test control circuit is the first voltage level. If the test signal is at the first voltage level, the output of the row decoder deselects all the cell transistors of the memory cell array,
If the test signal of the test control circuit is at the second voltage level, the column decoder and the row decoder select the cell transistor of the memory cell array corresponding to the column input address signal and the row address input signal. Features.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
FIG. 1 is a diagram showing a configuration of a memory circuit including a NOR type mask ROM of the present invention. The main part of the memory circuit of the present invention shown in FIG. 1 is similar to the conventional memory circuit described with reference to FIG. 2, and includes a data storage unit 1 composed of a memory cell array, a column selector 2, and a read circuit 3a. Composed. Since the configurations of the data storage unit 1 and the column selector 2 are the same as those in FIG. 2, the same reference numerals are assigned to the corresponding parts, and detailed description thereof is omitted.
[0032]
The output of the row decoder 19a is connected to the word line 6 of the memory cell array of the present invention, and the output of the column decoder 20a is connected to the selection control line 8 of the column selector 2. The memory circuit of the present invention includes a test control circuit 21 that controls the row decoder 19a and the column decoder 20a in a test operation.
[0033]
The memory circuit of the present invention includes a precharge voltage holding circuit including an inverter 13, a NAND gate 14, and a hold transistor 16 inside the reading circuit 3 a, unlike FIG. 2.
[0034]
A first embodiment of the present invention will be described using the readout circuit 3a shown in FIG. In the first embodiment, the occurrence of a read error based on the fluctuation of the leak amount of the cell transistor 5 in the low-speed operation of the memory circuit and the countermeasures will be described.
[0035]
If the discharge due to the leak amount of the bit line BL1 selected by the column selector 2 becomes large corresponding to the cell transistor A1 selected as the read target, the precharge voltage of the bit line BL1 is dynamically read out from the memory circuit. Since the battery is discharged before the holding time necessary for the operation elapses, "1" data written in the cell transistor A1 is read as "0" data, which causes a read error in the memory circuit.
[0036]
In particular, when the memory circuit is operated at a low speed, the precharge voltage of the bit line BL1 is required to have a long holding time. When the memory circuit is dynamically operated, the limit of the low speed operation depends on the holding time. Will be determined. In order to prevent the occurrence of a read error based on the fluctuation of the leak amount of the cell transistor 5, a current exceeding the leak amount of the cell transistor 5 is continuously supplied from the precharge power source 12 after the precharge period is ended, and the bit line It is only necessary to avoid a decrease in the precharge voltage of BL1.
[0037]
For this reason, the precharge transistor 10 of the conventional read circuit 3 includes a hold transistor 15 for supplying a current exceeding the leakage amount to the selected bit line BL1 and a NAND gate 14 for controlling the gate 16 thereof. A charge holding voltage holding circuit was added to form a new readout circuit 3a. The hold transistor 15 serves to hold the high level of the bit line BL1 precharged by the precharge transistor 10. The output of the read control circuit 4 is connected to the control line 11 connected to the gate of the precharge transistor 10.
[0038]
Next, the operation of the readout circuit 3a will be described. In the conventional read circuit 3 shown in FIG. 2, since the voltage holding circuit does not exist, the high level of the bit line BL1 which is in a floating state after the precharge period is discharged within a predetermined time due to the leak amount. In order to read "1" data of the cell transistor A1 selected by the dynamic read operation, the high level state of the bit line BL1 must be detected within the predetermined time.
[0039]
However, in the first embodiment, the high level on the input side of the inverter 13 set to the precharge voltage by the precharge power supply 12 becomes the low level on the output side, and this output low level is the level of the NAND gate 14. Connected to one inverting input terminal 17, a slow mode input signal is input to the other input terminal 18 of the NAND gate 14. If this slow mode input signal is high level, the output of the NAND gate 14 becomes low level, and the hold transistor 15 receiving this at the gate 16 is turned on, so that even after the precharge period by the precharge transistor 10 is completed. The high level of the precharged bit line BL1 is held by this feedback path.
[0040]
Thus, in order to maintain the high level state of the bit line BL1, "1" data is written in the cell transistor A1 connected to the bit line BL1, and the on-current of the hold transistor 15 is changed to the bit line BL1. It must be larger than the leak amount of BL1. Usually, the magnitude of the drain current of the transistor is extremely larger than the leakage current at the source / drain junction of the transistor, so that the ON current of the hold transistor 15 is easily set to be larger than the leakage amount of the bit line BL1. can do.
[0041]
At this time, if "0" data is written in the cell transistor A1, the cell transistor A1 is connected to the bit line BL1, and the cell transistor A1 is connected to the high level of the word line WL1 that selects the cell transistor A1. Since the ON state is established, the high level of the bit line BL1 held by the hold transistor 15 is grounded by the cell transistor A1, and the writing state of "0" data is detected.
[0042]
Thus, in order for the high level of the bit line BL1 held by the on-current of the hold transistor 15 to transition to the ground potential by the on-current of the cell transistor A1, the drain current of the hold transistor 15 is changed to the cell transistor A1. Must be very small compared to the drain current.
[0043]
That is, if the drain current of the hold transistor 15 is set to be sufficiently larger than the leak amount of the bit line BL1 and sufficiently smaller than the drain current of the cell transistor A1, after the precharge ends, By holding the high level of the precharged bit line BL1 using the voltage holding circuit provided in the read circuit 3a, "0" data and "1" data in an arbitrary low speed range regardless of the discharge time. Can be read out. In this way, it is possible to prevent a read error due to the leak amount of the cell transistor 5 and improve the yield of the memory circuit in the low-speed operation.
[0044]
Next, a second embodiment of the present invention will be described using the read circuit 3a shown in FIG. 1 again. In the second embodiment, the problem that the voltage holding circuit including the inverter 13, the NAND gate 14, and the hold transistor 15 described in the first embodiment hinders the high-speed operation of the memory circuit and the countermeasures will be described. .
[0045]
The problem in the high-speed reading of the memory circuit is that “0” data is written in the selected cell transistor A1 in FIG. 1 and the drain is connected to the selected bit line BL1. This is a transition speed when the word line WL1 selected for reading data is set to the high level to turn on the cell transistor A1, and the high level precharged on the bit line BL1 is discharged to the low level (ground).
[0046]
At this time, since the drain current for holding the precharge voltage of the bit line BL1 flows from the precharge power supply 12 via the hold transistor 15 even after the precharge period ends, the current required for the discharge is equivalent to this drain current. As a result, the transition speed at which the high level precharged on the bit line BL1 transitions to the low level via the cell transistor A1 decreases.
[0047]
In order to avoid this decrease in transition speed, the slow mode input signal at one input terminal 18 of the NAND gate 14 is set to low level, the output of the NAND gate 14 is set to high level, and the hold transistor 15 is turned off. That's fine. At this time, the precharge voltage of the bit line BL1 decreases due to the leak amount of the cell transistors 5 other than the cell transistor A1 connected to the bit line BL1, but even if some leaks occur during high-speed reading. Since the read operation is completed before the malfunction occurs, this decrease in the precharge voltage does not cause a decrease in the yield of the memory circuit.
[0048]
That is, at the time of low speed operation, as described in the first embodiment, the slow mode input signal of the NAND gate 14 is set to high level to operate the voltage holding circuit that holds the high level precharged on the bit line, During operation, the slow mode input signal may be set to a low level to prohibit the operation of the voltage holding circuit so that the reading speed does not decrease. In this way, read errors do not occur over a wide operating speed range, and the yield of the memory circuit can be greatly improved.
[0049]
Next, a third embodiment of the present invention will be described using the column decoder 19a, the row decoder 20a, and the test control circuit 21 that controls the operation thereof shown in FIG. In the third embodiment, a method for reducing the evaluation time of the memory circuit in the low-speed operation will be described.
[0050]
As described above, for example, if a read operation in units of bytes is performed on the entire area of the data storage unit 1 to guarantee a low-speed operation of the memory circuit, an enormous test time is required. However, it is not always necessary to guarantee low-speed operation in units of bytes. In the data storage unit 1, all the bit lines 9 in the data storage unit 1 in which “0” and “1” data are written are precharged at once. Then, all the word lines 6 connected to the memory cell array may be used to deselect all the cell transistors 5 (off state) and perform a single low-speed read operation collectively. At this time, it is desirable to set the slow mode input signal of the readout circuit 3a to a low level so that the voltage holding circuit is cut off.
[0051]
In the batch read operation, all the cell transistors 5 are not selected, so that “1” data indicating that the cell transistor 5 is not connected to the bit line 9 is read unless there is a particularly large leak current. Should be. If all the cell transistors 5 are not selected, the precharge voltage of the bit line 9 is not held, and if “0” data is read, a location where a large leak current is generated in any of the memory cell arrays. I know that there is.
[0052]
In the third embodiment, such a low-speed batch reading test is performed as follows. When the test signal from the test control circuit 21 shown in FIG. 1 becomes a high level, the column decoder 20a selects (ON) all the selection transistors 7 connected to the column selector 2 via the selection control line 8, and stores data. All the bit lines 9 in the section 1 are set in a selected state.
[0053]
When the test signal from the test control circuit 21 becomes high level, the row decoder 19a deselects all the word lines 6 (low level) and deselects all the cell transistors 5 in the data storage unit 1 (off). ) State. In this way, one batch reading may be performed using one cycle of low speed operation.
[0054]
If “1” data is read by one batch reading using the test control circuit 21, the leak amount of the data storage unit 1 in which “0” and “1” data is written as the stored information is less than the low speed reading. It turns out that it is a level without a problem. In such a leak level test by one batch reading, it is impossible to know how much leakage current has occurred in which location in the data storage unit 1, but if this test is performed, the data after data writing The defective product can be selected with sufficient accuracy with respect to the leakage failure of the storage unit 1.
[0055]
As described above, the long time required for the test of the memory circuit is a low-speed operation leak amount test that is repeatedly performed in units of bytes over the entire area of the data storage unit 1. If the test method according to the third embodiment, which enables selection of non-defective / defective products by reading, can be used, the test time can be greatly shortened.
[0056]
For example, in the conventional 32-bit configuration 256 kbyte ROM, 2.16 sec was required to guarantee low-speed operation. However, if the test method of the third embodiment is used, the non-defective / defective product can be obtained in a test time of only 0.033 msec. Therefore, the test cost can be greatly reduced.
[0057]
In the third embodiment, since the high-speed reading is performed over the entire area of the data storage unit 1, all the bits of the data storage unit 1 in which “0” and “1” data are written at this time are read. The function of can be confirmed.
[0058]
The present invention is not limited to the above embodiment. For example, in the first to third embodiments, the reading circuit 3a is the voltage holding of the precharge voltage comprising the inverter 13, the two-input NAND gate 14 having an inverting input terminal at one input, and the hold transistor 15. The voltage holding circuit is operated by setting a slow mode input signal to a high level. However, the configuration and operation of the voltage holding circuit are not necessarily limited to this.
[0059]
The voltage holding circuit is a transistor in which an input signal is set to a first voltage level in a low speed operation of the memory circuit, and an output of the voltage holding circuit holds a precharge voltage in response to the input signal of the first voltage level. The on-state transistor connects the pre-charge power source and the bit line to maintain the pre-charge voltage, and the input signal is set to the second voltage level in the high-speed operation of the memory circuit. In response to the input signal of the second voltage level, the output of the voltage holding circuit turns off the transistor that holds the precharge voltage, and the transistor in the off state shuts off the precharge power supply and the bit line. If there is.
[0060]
In the first and second embodiments, high-speed and low-speed reading of the memory circuit has been described by taking one cell transistor A1 included in the memory cell array of the data storage unit 1 as an example. There is no need to select one cell transistor. Needless to say, the same applies to the case where a plurality of cell transistors are used as the object of reading.
[0061]
In the first to third embodiments, the state of writing “0” data to the cell transistor is defined by connecting the drain of the cell transistor to the corresponding bit line. The “1” data write state is defined by the fact that the drain of the cell transistor is not connected to the corresponding bit line, but conversely “0” data is not connected and “1” data is connected without any problem. The invention can be applied. Various other modifications can be made without departing from the scope of the present invention.
[0062]
【The invention's effect】
As described above, according to the memory circuit of the present invention, the precharge voltage of the selected bit line BL1 is held by setting the slow mode input signal of the voltage holding circuit provided in the read circuit to the high level after the precharge is completed. Thus, the stored information written in the data storage unit can be read out in an arbitrary speed range of low-speed operation regardless of the discharge time.
[0063]
In addition, if the slow mode input signal of the voltage holding circuit is set to a low level during high-speed operation and the operation of the voltage holding circuit is prohibited so that the reading speed does not decrease, a reading error occurs over a wide operating speed range from high speed to low speed. And the yield of the memory circuit can be greatly improved.
[0064]
In the data storage unit in which the stored information is written, all columns (bit lines) are selected and precharged, all rows (cell transistors connected to the word lines) are deselected, and once in a batch. If the low-speed operation test by low-speed reading is performed, the non-defective / defective product can be selected by only one low-speed reading operation, so that the test time can be greatly shortened.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a memory circuit including a NOR type mask ROM of the present invention.
FIG. 2 is a diagram showing a configuration of a memory circuit composed of a conventional NOR type mask ROM.
[Explanation of symbols]
1. Data storage unit
2 ... Column selector
3, 3a ... Read circuit
4. Read control circuit
5 ... Cell transistor
6. Word line
7 ... Select transistor
8 ... Selection control line
9 ... Bit line
10 ... Precharge transistor
11 ... Control line
12 ... Precharge power supply
13 ... Inverter
14 ... NAND gate
15 ... Hold transistor
16: NAND gate output terminal
17: One terminal of the NAND gate
18 ... The other terminal of the NAND gate
19, 19a ... row decoder
20, 20a ... column decoder
21 ... Test control circuit

Claims (6)

A memory circuit including a read circuit including a voltage holding circuit for holding a precharge voltage,
The voltage holding circuit includes a control signal input terminal that operates the voltage holding circuit in a low-speed operation of the memory circuit and prohibits the operation of the voltage holding circuit in a high-speed operation of the memory circuit;
And a test control circuit for controlling the column decoder and the row decoder so as to select all the columns of the memory cell array and deselect all the rows in the low-speed test mode operation of the memory circuit. Memory circuit. The voltage holding circuit includes a hold transistor that holds the precharge voltage, a source of the hold transistor is connected to a source of the precharge transistor, and a connection point between the sources is connected to a drain of a selection transistor that forms a column selector. 2. The memory circuit according to claim 1, wherein a drain of the hold transistor is connected to a drain of the precharge transistor, and a connection point between the drains is connected to a precharge power source. In the low-speed operation of the memory circuit, a slow mode input signal having a first voltage level is input to the control signal input terminal of the voltage holding circuit, and the output of the voltage holding circuit is received by the precharge in response to the slow mode input signal. The hold transistor that holds the voltage is turned on, and the precharge power supply and the bit line are connected by the hold transistor in the on state, so that the precharge voltage precharged on the bit line is held,
In the high-speed operation of the memory circuit, a slow mode input signal having a second voltage level is input to the control signal input terminal of the voltage holding circuit, and the output of the voltage holding circuit is received by receiving the slow mode input signal. 2. The memory circuit according to claim 1, wherein the hold transistor holding a precharge voltage is turned off, and the precharge power supply and the bit line are cut off by the hold transistor in the off state. The hold transistor in the voltage holding circuit is a P-channel transistor, the voltage holding circuit includes at least a NAND gate circuit, and the NAND gate circuit is a two-input NAND gate circuit, and one input terminal is inverted. Input terminal,
The voltage holding circuit further includes an inverter, a source of the P-channel transistor is connected to an input terminal of the inverter, an output of the inverter is connected to the one inverting input terminal of the two-input NAND gate circuit, A slow mode input signal is input to the other input terminal of the NAND gate circuit forming the control signal input terminal of the voltage holding circuit, the output terminal of the NAND gate circuit is connected to the gate of the P channel transistor, and the P channel 4. The memory circuit according to claim 2, wherein the drain of the type transistor is connected to a precharge voltage. The drain current in the ON state of the hold transistor that holds the precharge voltage is larger than the sum of the leak currents of the cell transistors that form the memory cell array, and the on-state of any one of the cell transistors that form the memory cell array 5. The memory circuit according to claim 2, wherein the memory circuit is smaller than a drain current in a state. The test control circuit of the column decoder and the row decoder, if the test signal of the test control circuit is at the first voltage level, the output of the column decoder selects all the selection transistors of the column selector, and the test signal If it is at the first voltage level, the output of the row decoder deselects all the cell transistors of the memory cell array,
If the test signal of the test control circuit is at the second voltage level, the column decoder and the row decoder select the cell transistor of the memory cell array corresponding to the column input address signal and the row address input signal. 5. The memory circuit according to claim 1, wherein the memory circuit is any one of claims 1 to 4.

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