JP3724736B2 - Display control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display control device that outputs display data and dimming data to control a display.
[0002]
[Prior art]
Conventionally, there is a liquid crystal display device including a microcomputer 1, a display controller 2 (display control device), and a liquid crystal display 3 (see FIG. 7). The liquid crystal display 3 includes a liquid crystal display element 4, a drive circuit 5, a light emitting element 6, and a lighting circuit 7. The liquid crystal display element 4 is a dot matrix type and has, for example, pixels of 320 × 240 dots (see FIG. 8). That is, the liquid crystal display element 4 includes the first line to the 240th line, and each line has 320 pixels.
[0003]
The light emitting element 6 is disposed on the back side of the liquid crystal display element 4 and illuminates the liquid crystal display element 4 from behind. The microcomputer 1 includes a CPU, a RAM, a ROM, and the like, and outputs display data and dimming data to the display controller 2. The display controller 2 drives the liquid crystal display element 4 via the drive circuit 5 and drives the light emitting element 6 via the lighting circuit 7.
[0004]
The display controller 2 includes a register 8, a latch pulse output circuit 9, a PWM output circuit 10, and an output buffer 11 (see FIG. 9). The display data DATA is output to the liquid crystal display 3 via the output buffer 11. The dimming data is output to the lighting circuit 7 through the output buffer 11 as a PWM signal in the PWM output circuit 10. The PWM signal represents the luminance level at the ratio of the on time t1 to the period T1 (see FIG. 10).
[0005]
The display controller 2 sequentially outputs the display data of the first line to the 240th line to the drive circuit 5, and the drive circuit 5 sequentially drives the first line to the 240th line of the liquid crystal display element 4. The latch pulse LP output from the latch pulse output circuit 9 indicates the end of the display data DATA of each line, and the falling edge of the latch pulse LP is synchronized with the end of the display data DATA of each line.
[0006]
[Problems to be solved by the invention]
However, the display controller 2 can be applied to non-self-luminous elements such as the liquid crystal display element 4, but can be applied to self-luminous display elements such as organic electroluminescence display elements (hereinafter referred to as organic EL display elements). Had the problem of not being applicable. That is, the display controller 2 can be used for the liquid crystal display 3 that independently controls the liquid crystal display element 4 and the light emitting element 6 like the liquid crystal display 3, but the display controller includes a self-luminous display element. Could not be applied. This is because in the case of a self-luminous display element, it is necessary to synchronize the dimming data (that is, PWM signal) with the display data.
[0007]
The present invention has been made in view of the demand for a highly versatile display control apparatus capable of controlling various display elements, and is not limited to non-self-luminous elements such as liquid crystal display elements, but also organic EL display elements. A display control device that can also be applied to a self-luminous display element such as the above.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention shows an output buffer 31 that temporarily stores display data DATA and outputs the display data DATA to the display units 23 and 43, and a predetermined amount of termination of the display data DATA. A latch pulse output circuit 29 for outputting a latch pulse LP to the output buffer 31, and dimming data for adjusting the luminance of the displays 23 and 43 are transmitted as PWM signals via the output buffer 31 to the displays 23 and 43. A display control device 22 having a PWM output circuit 30 for outputting to the storage unit 28a for storing synchronization instruction data for selecting whether or not the PWM signal is synchronized with the latch pulse LP, and the PWM signal. Can be synchronized with the latch pulse LP, but is not used when the display is a liquid crystal display. , In which the formed.
[0009]
In the present invention, the synchronization circuit 32 synchronizes the PWM signal with the latch pulse LP when the synchronization instruction signal SYN is input from the latch pulse output circuit 29.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. 1 to 3 show an embodiment in which a display controller 22 according to the present invention is applied to a liquid crystal display device 20.
[0011]
The liquid crystal display device 20 includes a microcomputer 21, a display controller 22 (display control device), and a liquid crystal display 23 (see FIG. 1). The liquid crystal display 23 includes a liquid crystal display element 24, a drive circuit 25, a light emitting element 26 and a lighting circuit 27. The liquid crystal display element 24 is a matrix type display element having 320 × 240 dot pixels. The light emitting element 26 is composed of, for example, a light emitting diode, a cold cathode tube or a bulb, and is disposed on the back side of the liquid crystal display element 24 to illuminate the liquid crystal display element 24 from behind.
[0012]
The microcomputer 21 includes a CPU, a RAM, a ROM, and the like, and outputs display data and dimming data to the display controller 22. The display controller 22 drives the liquid crystal display element 24 via the drive circuit 25 and drives the light emitting element 26 via the lighting circuit 27.
[0013]
The display controller 22 includes a register 28, a latch pulse output circuit 29, a PWM output circuit 30, and an output buffer 31 (see FIG. 2). The display controller 22 sequentially outputs the display data DATA of the first line to the 240th line to the drive circuit 25. The dimming data is converted into a PWM signal by the PWM output circuit 30 and output to the lighting circuit 27 via the output buffer 31.
[0014]
The latch pulse LP output from the latch pulse output circuit 29 indicates the end of the display data DATA of each line, and the falling edge of the latch pulse LP is synchronized with the end of the display data DATA of each line (FIG. 3). The PWM signal output from the PWM output circuit 30 represents the luminance level at the ratio of the on time t2 to the period T2. The PWM output circuit 30 includes a synchronization circuit 32 (matching circuit). However, when the display controller 22 is applied to the liquid crystal display 20, the synchronization circuit 32 is not used.
[0015]
The register 28 includes a storage unit 28a that stores synchronization instruction data for selecting whether to synchronize the PWM signal with the latch pulse LP. The storage unit 28a has a storage capacity of 2 bits. For example, when “10” is written in the storage unit 28a, a synchronization instruction signal is output from the latch pulse output circuit 29 to the synchronization circuit 30, and the PWM signal Is output in synchronization with the latch pulse LP, and when “00” is written in the storage unit 28a, the synchronization instruction signal is not output from the latch pulse output circuit 29, and the PWM signal is not synchronized with the latch pulse LP. . The synchronization instruction data is written into the storage unit 28 a of the register 28 by the microcomputer 21.
[0016]
4 to 6 show an embodiment in which the display controller 22 is applied to the organic EL display device 40. FIG.
[0017]
The organic EL display device 40 includes a microcomputer 41, a display controller 22, and an organic EL display 43 (see FIG. 4). The organic EL display 43 has an organic EL display element 44 and a drive circuit 45. The organic EL display element 44 is a matrix type display element having 320 × 240 dot pixels. The display controller 22 sequentially outputs the display data DATA of the first line to the 240th line to the drive circuit 45.
[0018]
The PWM signal output from the PWM output circuit 30 represents the luminance level at the ratio of the on time t3 to the period T3 (see FIG. 6). “10” is written as the synchronization instruction signal in the storage unit 28 a of the register 28, and the synchronization instruction signal SYN is output from the latch pulse output circuit 29 to the synchronization circuit 32. The PWM signal output from the PWM output circuit 30 is output to the drive circuit 45 via the output buffer 31 in synchronization with the falling edge of the latch pulse LP.
[0019]
As described above, whether or not the display controller 22 outputs the synchronization signal SYN from the latch pulse output circuit 29 to the synchronization circuit 32 by writing the synchronization instruction data into the storage unit 28a of the register 28 using the microcomputers 21 and 41. Can be selected, it is highly versatile and can be applied to the liquid crystal display 23 and the organic EL display 43.
[0020]
The display controller 22 in the organic EL display 40 synchronizes the rising edge of the PWM signal with the falling edge of the latch pulse LP, but the period T3 of the PWM signal is the same as the period of the latch pulse LP. For example, it may be delayed by a predetermined time from the fall of the latch pulse LP and synchronized so that the PWM signal rises.
[0021]
【The invention's effect】
The present invention provides an output buffer for temporarily storing display data and outputting the display data to a display, and a latch pulse output circuit for outputting a latch pulse indicating the end of a predetermined amount of the display data to the output buffer. And a PWM output circuit that outputs dimming data for adjusting the luminance of the display device to the display device via the output buffer as a PWM signal , wherein the PWM signal is the latch pulse. And a synchronization circuit that can synchronize the PWM signal with the latch pulse, but is not used when the display is a liquid crystal display. And is applicable not only to non-self-luminous elements such as liquid crystal display elements but also to self-luminous display elements such as organic EL display elements.
[Brief description of the drawings]
FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a block diagram of a display controller showing the embodiment.
FIG. 3 is a timing chart showing the embodiment.
FIG. 4 is a block diagram of an organic EL display device showing the embodiment.
FIG. 5 is a block diagram of a display controller showing the embodiment.
FIG. 6 is a timing chart showing the embodiment.
FIG. 7 is a block diagram of a liquid crystal display device showing a conventional example.
FIG. 8 is a front view of a liquid crystal display element showing a conventional example.
FIG. 9 is a block diagram of a display controller showing a conventional example.
FIG. 10 is a timing chart showing a conventional example.
[Explanation of symbols]
23 Liquid crystal display (display)
28 Register 28a Memory 29 Latch pulse output circuit 30 PWM output circuit 31 Output buffer 32 Match circuit (synchronous circuit)
43 Organic EL display (display)
DATA Display data LP Latch pulse SYN Synchronization instruction signal

Claims (2)

An output buffer for temporarily storing display data and outputting the display data to a display; a latch pulse output circuit for outputting a latch pulse indicating the end of a predetermined amount of the display data to the output buffer; and the display A PWM output circuit that outputs dimming data for adjusting the luminance of the display to the display device via the output buffer as a PWM signal, and a display control device comprising:
A storage unit for storing synchronization instruction data for selecting whether to synchronize the PWM signal with the latch pulse;
A display control device comprising: a synchronization circuit that can synchronize the PWM signal with the latch pulse but is not used when the display is a liquid crystal display.   The display control apparatus according to claim 1, wherein the synchronization circuit synchronizes the PWM signal with the latch pulse when a synchronization instruction signal is input from the latch pulse output circuit.

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