JP3726426B2 - Multi-channel display device - Google Patents

Description

[0001]
[Technical Field of the Invention]
The present invention relates to the generation of a sampling clock and a synchronization signal for image control in a display device that receives a plurality of channels and performs multi-channel display.
[0002]
[Prior art]
As shown in FIG. 3, a conventional multi-channel display device receives a large number of broadcast channels and demodulates an analog video signal, and separates the analog video signal into a luminance signal and a chromaticity signal. A YC separation unit 5 that performs RGB demodulation from the luminance signal and chromaticity signal, an A / D 7 that converts the RGB signal into digital image data, and horizontal and vertical synchronization from the analog video signal. A synchronization separation unit 2 that separates and outputs a signal, a PLL circuit 3 that generates a horizontal pulse, a vertical pulse, a sampling clock, and the like that are synchronized with the synchronization signal, and an image of a plurality of channels in units of fields of the digital image data A field memory 8 for dividing and storing the data, and a field memory 8 for controlling the filled memory. And an image control unit 4 causes the multi-screen display, said tuner, and a control unit for controlling the image control unit. The control unit 9 sequentially selects 20 or more broadcast channels, and issues a command to write image data for each channel into the field memory. The PLL circuit 3 generates a sampling clock, a horizontal pulse, and a vertical pulse that are synchronized with the synchronization signal that is synchronized and separated by the synchronization separation unit 2 every time a new channel is selected, because the synchronization cycle and the synchronization phase are different for each channel. To do. The image control unit 4 generates a writing timing signal for an image to be written in the field memory 8 on the basis of the generated horizontal pulse and vertical pulse, and inputs the signal to the field memory. As shown in FIG. 4 (a), the phase of the synchronization signal for each broadcast channel has a phase difference of less than one vertical period, and the synchronization period is slightly different. The phase difference is not constant but changes. The image control unit 4 controls to write image data during the period from the vertical pulse t2 immediately after channel selection to the second vertical pulse t3. For this reason, the image data in the period from t1 to t2 becomes invalid, and the invalid period reaches a maximum of about 1 vertical period. As a result, it takes time to select and search a large number of channels, and the movement of the multi display screen is slowed down. In order to solve this problem, there is a demand for means for speeding up phase synchronization of the synchronization signal for capturing image data at the time of channel switching.
[0003]
[Problems to be solved by the invention]
In view of this problem, it is noted that although there is a phase difference of the synchronization signal for each channel, the period error is on the order of 10 to the fifth power, and the synchronization period and the synchronization phase for each channel are determined by the standard clock unit. An object of the present invention is to generate a synchronization signal for field memory control, which is measured / stored with clock data, predicts and calculates the synchronization phase of a newly selected channel based on the stored data, and is phase-corrected.
[0004]
[Means for Solving the Problems]
As shown in FIG.
A TV tuner that receives a plurality of broadcast channels and outputs an analog video signal, an A / D that converts the video signal into digital image data, and the digital image data in units of fields and divides the image data of multiple channels A field memory that stores data, a synchronization separation unit that separates a synchronization signal from the analog video signal, a PLL circuit that generates a horizontal pulse, a vertical pulse, a sampling clock, and the like synchronized with the synchronization signal, and the field memory In a multi-channel display device comprising an image control unit that displays a plurality of reception channel images on a multi-screen and a control unit that controls the TV tuner, the image control unit, etc.
A synchronization phase measuring unit having means for measuring a synchronization phase and a synchronization period of the synchronization signals of the plurality of separated channels, and means for storing the measurement result together with the reception channel; and the stored synchronization phase data for each reception channel A synchronization phase correction unit for predicting and calculating the synchronization phase of the newly switched channel based on the synchronization cycle data and correcting the phase of the vertical pulse, the horizontal pulse, and the like is added.
[0005]
Further, the synchronous measurement unit is
A horizontal period measuring unit that measures the period of the horizontal synchronizing signal and generates horizontal period data, a horizontal period memory that temporarily stores the horizontal period data for each channel, and a phase of the vertical synchronizing signal to generate vertical phase data A vertical phase measurement unit, a vertical cycle memory that temporarily stores the vertical cycle data for each channel, and a standard clock unit that generates reference time data such as the horizontal cycle measurement, vertical synchronization phase, and synchronization phase correction calculation And consist of
[0006]
Furthermore, an order calculator for calculating the order of the channels closest in phase from the vertical synchronization phase data for each channel and storing the channel order data is additionally installed in the synchronization measuring unit.
[0007]
Furthermore, the synchronous phase correction unit,
When selecting a new channel, the vertical phase data, the horizontal cycle data, and the elapsed time data from the previous channel selection are calculated, the vertical correction calculator that calculates and outputs the vertical correction data, and the output horizontal pulse from the PLL circuit. It comprises a horizontal counter for counting and a vertical pulse generator for generating a vertical pulse when the count of the horizontal counter reaches a predetermined number and resetting the horizontal counter.
[0008]
Further, the synchronous phase measuring unit measures the phase of the horizontal synchronizing signal, generates a horizontal phase data, and a horizontal phase memory for temporarily storing the horizontal phase data for each channel,
A horizontal correction calculator for calculating horizontal correction data for correcting the horizontal phase from the horizontal phase data and the horizontal cycle data, and an output of the M / N counter of the PLL circuit based on the horizontal correction data in the synchronous phase correction unit. A phase shifter that shifts the phase is additionally installed.
[0009]
Further, the clock data generated by the standard clock unit is used as a reference clock for image data reading in the field memory and a synchronization signal.
Further, the clock data generated by the standard clock unit is used as a reference clock and a synchronization signal synchronized with the received synchronization signal of the specific channel.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The synchronization phase measurement unit measures and stores the synchronization period and the synchronization phase of the synchronization signal for each channel based on the clock data generated by the standard clock unit. The synchronization phase correction unit predicts and calculates the synchronization phase of the newly selected channel based on both stored data, and generates a phase memory-corrected synchronization signal for field memory control.
[0011]
Further, the channel having the closest phase is sequentially calculated from the vertical synchronization phase data for each channel, the channel order data is stored, and the reception channel is selected along the order of the channel order data.
[0012]
Further, the synchronization cycle and synchronization phase of the horizontal synchronization signal for each channel are measured and stored, and the horizontal synchronization phase of the newly selected channel is predicted and calculated using both stored data, and the horizontal correction data is calculated and output. The phase of the phase shifter is corrected by the horizontal correction data.
[0013]
The clock data generated by the standard clock unit is a reference clock and a synchronization signal synchronized with the image data reading reference clock and the synchronization signal of the field memory or the received synchronization signal of the specific channel.
[0014]
【Example】
FIG. 1 is a principal block diagram of one embodiment according to the present invention, and FIG. 2 is a principal block diagram of another embodiment.
In FIG.
1, 2, 3, 4, 5, 6, 7, 8, and 9 have the same functions as those described in the prior art, and will not be described. Reference numeral 11 denotes a synchronization phase measuring unit having means for measuring the synchronization phase and synchronization period of the synchronization signals of the plurality of separated channels, and means for storing the measurement result together with the reception channel, and 12 denotes the stored synchronization phase for each reception channel. A synchronization phase correction unit that predicts and calculates the synchronization phase of the newly switched channel based on the data and the period data, and corrects the phase of the vertical pulse, the horizontal pulse, and the like.
[0015]
In FIG.
3a compares the phase of the received video horizontal synchronization signal with the phase of the horizontal pulse generated inside the apparatus, outputs an error signal, 3b filters the error signal, and 3c uses the filtered error signal. VCO and 3d are frequency controlled and oscillate and output a sampling clock for image data, and M / N counters that divide the oscillation frequency of the VCO to generate horizontal pulses. 11a is a horizontal phase measurement unit that measures the synchronization phase of the horizontal synchronization signal as a deviation time from the internal reference phase and outputs horizontal phase data, and 11b is a horizontal phase that measures the synchronization period of the horizontal synchronization signal and outputs horizontal cycle data. The period measuring unit 11c measures the synchronizing phase of the vertical synchronizing signal as a deviation time from the internal reference phase and outputs the vertical phase data. 11d is a horizontal phase for temporarily storing the horizontal phase data for each channel. 11e is a horizontal cycle memory for temporarily storing horizontal cycle data for each channel, 11f is a vertical phase memory for temporarily storing vertical data for each channel, and 11g is for calculating channel numbers in the order of small difference in the vertical phase data. , An order calculator for calculating and outputting channel selection data for selecting a reception channel in this order, 11h is internal standard time data It is a standard clock unit to generate.
[0016]
When selecting a new channel, 12a calculates vertical phase data, horizontal period data, and elapsed time data from the previous channel selection, and calculates and outputs vertical correction data. 12b outputs from the PLL circuit. A horizontal counter for counting horizontal pulses, 12c generates a vertical pulse when the count value of the horizontal counter reaches a predetermined number, and a vertical pulse generator for resetting the horizontal counter, 12d is a PLL based on the horizontal correction data. A phase shifter 12e for shifting the output phase of the M / N counter of the circuit is a horizontal correction calculator for calculating and outputting horizontal correction data from horizontal phase data and horizontal period data.
[0017]
The embodiment of the present invention is configured as described above. Detailed operations will be described with reference to the vertical synchronization of the images and the image writing timing diagram of FIGS.
In the prior art, the start of image data capture is the first vertical synchronization position t2, counting from the write end timing t1 of 1 ch, as shown in FIG. From t3 to t4,..., Tn-1 to tn are in a standby state. The image writing timing in the vertical direction is such that the horizontal pulse is counted starting from the vertical pulse, and the image control unit 4 controls to start writing the image data when reaching a certain value. Not generated.
The embodiment of the present invention is configured as described above. Detailed operations will be described with reference to the vertical synchronization of the images and the image writing timing diagram of FIGS.
In the prior art, the start of image data capture is the first vertical synchronization position t2, counting from the write end timing t1 of 1 ch, as shown in FIG. From t3 to t4,..., Tn-1 to tn are in a standby state. The image writing timing in the vertical direction is such that the horizontal pulse is counted starting from the vertical pulse, and the image control unit 4 controls to start writing the image data when reaching a certain value. Not generated.
[0018]
In an embodiment according to the present invention,
The horizontal phase measurement unit 11a measures the synchronization phase of the horizontal synchronization signal for each channel based on the clock data generated by the standard clock unit 11h, and measures and outputs the horizontal phase data. Similarly, the horizontal period measurement unit 11b measures and outputs horizontal period data, and the vertical phase measurement unit 11c measures and outputs vertical phase data. The horizontal phase data, horizontal cycle data, and vertical phase data are temporarily stored for each reception channel in the horizontal phase memory 11d, horizontal cycle memory 11e, and vertical phase memory 11f, and these stored data are updated as needed. Further, the order calculation unit 11g calculates the order of the channels having the closest synchronization phase from the vertical synchronization phase data for each channel, stores the channel order data, and the stored order data is used as shown in FIG. In addition, new channel selection channels are selected and controlled in order of vertical synchronization phase. When a new channel is selected, the vertical correction calculator 12a adds data obtained by multiplying the previous n ch vertical phase data by the elapsed time data up to this time and the horizontal period data, and then predicts the current predicted vertical. The vertical correction data is calculated and output as the phase. On the other hand, the horizontal counter 12b counts the horizontal pulses from the PLL circuit 3, and outputs a vertical pulse and clears the horizontal counter when it reaches a certain value. It is also cleared by a vertical sync signal from the sync separator 2. The vertical correction data is input from the data load terminal of the horizontal counter 12b, and the current count value of the horizontal counter is replaced with the vertical correction data. As a result, the horizontal counter output is set to the vertical phase of the image data immediately after switching, and the image data can be immediately written as shown in FIG.
[0019]
Further, in order to shorten the pull-in time of the PLL circuit 3, the horizontal correction calculator 12e calculates horizontal position data, horizontal cycle data, and elapsed time data and calculates the current horizontal correction data in the same manner as the vertical correction calculator. Output. The PLL circuit 3 maintains a synchronized state on the periodic surface because the horizontal cycle of each reception channel is very small, and is in a state where only the phases do not match. Therefore, a phase shifter 12d is provided to input the horizontal pulse shifted in phase by the horizontal correction data to the phase comparison unit 3a and output it as a horizontal pulse.
[0020]
Further, FIG. 5 shows the clock data of the standard clock unit 11h as a reference clock and a synchronizing signal synchronized with the reference clock and synchronizing signal for image data reading in the field memory or the received synchronizing signal of a specific channel. is there.
[0021]
【The invention's effect】
Implemented as described above, the following effects are exhibited.
The synchronization phase measurement unit measures and stores the synchronization period and synchronization phase of the synchronization signal for each channel based on the clock data generated by the standard clock unit, and synchronizes the newly selected channel based on the stored data. A phase memory prediction signal was generated by predicting the phase and correcting the phase.
Furthermore, it becomes possible to select the receiving channel in the order of the closest phases based on the vertical synchronization phase data for each channel.
Furthermore, the clock data generated by the standard clock unit can be a reference clock and a synchronization signal for reading image data of a field memory, or a reference clock and a synchronization signal synchronized with a received synchronization signal of a specific channel. .
[Brief description of the drawings]
FIG. 1 is a block diagram of a main part of one embodiment according to the present invention.
FIG. 2 is a main part block diagram of another embodiment according to the present invention.
FIG. 3 is a main part block diagram according to the prior art.
FIG. 4 is a timing diagram of vertical synchronization and image capture of an image according to an embodiment of the prior art and the present invention.
FIG. 5 is a timing diagram of vertical synchronization and image capture of an image according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 TV tuner 2 Synchronization separation part 3 PLL circuit 3a Phase comparison part 3b Filter 3c VCO
3d M / N counter 4 Image control unit 5 YC separation unit 8 Field memory 9 Control unit 11 Synchronous phase measurement unit 11a Horizontal phase measurement unit 11b Horizontal cycle measurement unit 11c Vertical phase measurement unit 11d Horizontal phase memory 11e Horizontal cycle memory 11f Vertical phase Memory 11g Permutation calculator 11h Standard clock section 12 Synchronous phase correction section 12a Vertical correction calculator 12b Horizontal counter 12c Vertical pulse generator 12d Phase shifter 12e Horizontal correction calculator

Claims (7)

A TV tuner that receives a plurality of broadcast channels and outputs an analog video signal, an A / D (analog / digital converter) that converts the video signal into digital image data, and a plurality of channels for the digital image data in field units A field memory that divides and stores the image data; a synchronization separation unit that separates a synchronization signal from the analog video signal; a PLL circuit that generates a horizontal pulse, a vertical pulse, a sampling clock, and the like synchronized with the synchronization signal; In a multi-channel display device comprising an image control unit that controls the filled memory to display images of a plurality of reception channels on a multi-screen, the TV tuner, a control unit that controls the image control unit, and the like.
A synchronization phase measuring unit having means for measuring a synchronization phase and a synchronization period of the synchronization signals of the plurality of separated channels, and a means for storing the measurement result together with the reception channel; and the stored synchronization phase data for each reception channel And synchronization period data to predict and calculate the synchronization phase of the newly switched channel, and add a synchronization phase correction unit that corrects the phase of the vertical pulse, horizontal pulse, etc.
Measure and store the synchronization period and synchronization phase for each channel, predict and calculate the synchronization phase of the newly selected channel from the stored synchronization period data and synchronization phase data, and correct the phase for the field memory control A multi-channel display device that generates a synchronization signal. The synchronous phase measurement unit,
A horizontal cycle measurement unit that measures the synchronization cycle of the horizontal synchronization signal and generates horizontal cycle data, a horizontal cycle memory that temporarily stores the horizontal cycle data for each channel, and a vertical phase data by measuring the synchronization phase of the vertical synchronization signal A standard for generating a vertical phase measurement unit to be generated, a vertical cycle memory for temporarily storing the vertical cycle data for each channel, and a reference time data such as the horizontal cycle measurement, vertical synchronization phase measurement, and synchronization phase correction calculation The multi-channel display device according to claim 1, comprising a timepiece unit. In the synchronization phase measurement unit, an order calculator for calculating the order of the channels closest to the vertical synchronization phase from the vertical synchronization phase data for each channel and storing the channel order data is additionally installed. The multi-channel display device according to claim 2, wherein a receiving channel is selected along the channel. The synchronous phase correction unit,
When selecting a new channel, the vertical phase data, the horizontal period data, and the elapsed time data from the previous channel selection are multiplied, and a vertical correction arithmetic unit for calculating and outputting vertical correction data, and an output horizontal from the PLL circuit. 2. A horizontal counter that counts pulses, and a vertical pulse generator that generates a vertical pulse when the count value of the horizontal counter reaches a predetermined number and resets the horizontal counter. A multi-channel display device according to 1. A horizontal phase measurement unit that measures the phase of a horizontal synchronization signal and generates horizontal phase data in the synchronization phase measurement unit, and a horizontal phase memory that temporarily stores the horizontal phase data for each channel,
A horizontal correction calculator for calculating horizontal correction data for correcting a horizontal phase from the horizontal phase data and the horizontal cycle data, and an M / N (M / N (PL) of the PLL circuit based on the horizontal correction data. (Division) The output phase of the counter is additionally installed with a phase shifter to measure and store the synchronization period and synchronization phase of the horizontal synchronization signal for each channel, and according to the stored synchronization period data and synchronization phase data, The multi-channel display according to claim 1, wherein the horizontal synchronization phase of a newly selected channel is predicted and calculated, horizontal correction data is calculated and output, and the phase of the phase shifter is corrected by the horizontal correction data. apparatus. 3. The multi-channel display device according to claim 2, wherein the clock data generated by the standard clock unit is used as a reference clock and a synchronization signal for reading image data of the field memory. The multi-channel display device according to claim 2, wherein the clock data generated by the standard clock unit is a reference clock and a synchronization signal synchronized with the received synchronization signal of the specific channel.

Images