JP3728577B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor memory device including a flash memory having a floating gate and low power consumption and high density.
[0002]
[Prior art]
In general, in a flash memory with a floating gate, the size of the floating semiconductor layer for storing electric charge is reduced, and ultimately it is a quantum dot, thereby reducing power consumption and high-density integration. Can be realized.
[0003]
As a technique for producing a flash memory having quantum dots for accumulating charges with good controllability, a technique is known in which a heterojunction including a floating semiconductor layer is regrown in a TSR (tetrahedral shaped recess) structure.
[0004]
FIGS. 10 to 13 are a cutaway side view and a cutaway explanatory view (FIG. 13) of a main part showing a semiconductor memory device in a process key point for explaining the prior art relating to a flash memory using the TSR structure. If necessary, see Japanese Patent Application No. 9-317101 as prior art).
[0005]
Refer to FIG.
10- (1)
An n-type semiconductor layer (first semiconductor layer) 2, a non-doped semiconductor layer (second semiconductor layer) 3, and an n-type semiconductor layer (third semiconductor layer) 4 are formed on the n-type semiconductor substrate 1.
[0006]
The main data of each semiconductor part is
(1) n-type semiconductor substrate 1
Material: Semi-insulating GaAs
(2) n-type semiconductor layer 2
Material: n-GaAs
Impurity: Se
Impurity concentration: 5 × 10¹⁸〔cm^-3]
(3) Non-doped semiconductor layer 3
Material: i-GaAs
(4) n-type semiconductor layer 4
Material: n-GaAs
Impurity: Se
Impurity concentration: 5 × 10¹⁸〔cm^-3]
[0007]
Refer to FIG.
10- (2)
By applying plasma CVD (plasma chemical vapor deposition) method, SiO with a thickness of 200 nm₂
An insulating film 5 made of is formed.
[0008]
10- (3)
By applying electron beam lithography technology, SiO₂An opening 5A having a diameter of about 1 [μm] is formed in the insulating film 5 made of
[0009]
Refer to FIG.
11- (1)
By applying a wet etching method using bromomethanol as an etchant, anisotropic etching of the n-type semiconductor layer 4 and the non-doped semiconductor layer 3 is performed through the opening 5A, and a tetrahedron having a size larger than that of the opening 5A. Groove (TSR)
3A is formed.
[0010]
Refer to FIG.
11- (2)
An n-type semiconductor layer (channel layer) 6 having a large electron affinity and a non-doped semiconductor layer (first barrier layer) having a small electron affinity compared to the semiconductor layer 6 by applying a MOVPE (metalorganic vapor phase epitaxy) method. 7. A non-doped semiconductor layer (electron storage layer) 8 having a higher electron affinity than the semiconductor layer 7 and a non-doped semiconductor layer (second barrier layer) 9 having a lower electron affinity than the non-doped semiconductor layer 8 are formed.
[0011]
The main data of each semiconductor part is
(1) n-type semiconductor layer (channel layer) 6
Material: n-type InGaAs
Impurity: Se
Impurity concentration: 1 × 10¹⁸〔cm^-3]
Thickness: 15 [nm]
(2) Non-doped semiconductor layer (first barrier layer) 7
Material: i-AlGaAs
Thickness: 15 [nm]
(3) Non-doped semiconductor layer (electron storage layer) 8
Material: i-InGaAs
Thickness: 5 [nm]
(4) Non-doped semiconductor layer (second barrier layer) 9
Material: i-AlGaAs
Thickness: 10 [nm]
[0012]
Refer to FIG.
12- (1)
On the n-type semiconductor layer 4 and the n-type semiconductor exposed by removing a part of the insulating film 5 around the tetrahedral groove 3A by applying a lithography technique, a vacuum deposition method, or the like A drain electrode 10 and a source electrode 11 made of AuGe / Au having a thickness of 50 [nm] / 200 [nm] are formed on the back surface of the substrate 1, and an alloying heat treatment is performed at a temperature of 450 [° C.] for 1 [min]. I do.
[0013]
Refer to FIG.
12- (2)
The gate electrode 12 made of Al having a thickness of 200 [nm] is formed by applying a vacuum deposition method or a lithography technique.
[0014]
See FIGS. 13A and 13B
13- (1)
In the periphery of the element, mesa etching reaching the n-type semiconductor layer 2 as the first semiconductor layer from the surface is performed to separate the elements.
[0015]
When a semiconductor memory device is manufactured using the TSR structure described above, high integration of a flash memory can be achieved by reducing the size of the TSR and reducing the arrangement pitch. Since the size of the floating quantum dots generated at the bottom portion of the non-doped semiconductor layer 8 is not changed and only the area on the facet surface (inclined surface) of the TSR is reduced, when electrons are taken in and out of the floating quantum dots, The current flowing through the quantum well layer formed on the facet surface of the TSR, that is, the first barrier layer on the facet surface without flowing through the floating quantum dot, the non-doped semiconductor layer 7 and the electron storage layer N which is a channel layer via a non-doped semiconductor layer 8 and a non-doped semiconductor layer 9 which is a second barrier layer. Current will flow to the semiconductor layer 6 is less, therefore, it is possible to reduce power consumption.
[0016]
Conventionally, as a technique for creating the fine TSR structure as described above with good controllability, both the TSR size and the method for reducing the TSR arrangement pitch, and the TSR size only without changing the TSR arrangement pitch are reduced. How to do is known.
[0017]
In the method of reducing both the TSR size and the TSR arrangement pitch, there is a problem that the mask alignment margin is reduced because the drain electrode 10 of the memory is formed, and the yield in manufacturing the memory is deteriorated.
[0018]
In addition, in the method of reducing only the TSR size without changing the TSR arrangement pitch, the layer thickness of the semiconductor layer to be regrown can be accurately controlled unless the speed of regrowing each semiconductor layer that generates the heterojunction is sufficiently slow. In addition, there is a problem that high integration cannot be achieved because the arrangement pitch does not change.
[0019]
[Problems to be solved by the invention]
In the present invention, the power consumption at the time of writing and erasing in the flash memory using the TSR structure is reduced, and the controllability of the fine structure formation is improved to realize a higher density and an improved manufacturing yield. Try to.
[0020]
[Means for Solving the Problems]
In the present invention, a fine opening is formed in the mask film by isotropic etching, and each semiconductor layer is anisotropically etched through the opening to form a TSR having a size larger than that of the opening. In this respect, it is the same as the prior art, but after that, by forming the quantum well structure and forming the metal film for the gate electrode while leaving the mask, the gate electrode corresponding only to the floating quantum dot and its vicinity is self-aligned. Further, it is fundamental that the quantum well structure on the facet surface is etched in a self-aligning manner using the gate electrode as a mask.
[0021]
By doing so, the gate electrode becomes a minute one that is close to the opening in the mask film that was originally formed, and the underlying quantum well structure has the same size. When electrons are taken in and out, the current flowing through the quantum well in parallel with the necessary current is significantly reduced, and the power consumption during memory operation is reduced.
[0022]
In addition, although the number of steps is slightly increased, a sufficient polishing accuracy can be ensured when forming the drain electrode by adding a polishing step for flattening to the basic means, or the gate electrode It is possible to improve the manufacturing yield by allowing the drain electrode to be formed in a self-aligned manner.
[0023]
From the foregoing, in the method of manufacturing a semiconductor memory device according to the present invention,
(1)
A first semiconductor layer of one conductivity type (for example, n-GaAs layer 22), a non-doped second semiconductor layer (for example, i-GaAs layer 23), and one conductor on a conductive semiconductor substrate (for example, n-GaAs substrate 21). A step of sequentially forming a third semiconductor layer (eg, n-GaAs layer 24) having a high impurity concentration and an insulating film (eg, SiO 2)₂And forming an opening (for example, opening 25A) in the insulating film with a pitch larger than the size of the opening, and then performing etching through the opening. Forming a regular tetrahedral groove (TSR) (e.g., a regular tetrahedral groove (TSR) 23A) reaching from the third semiconductor layer into the second semiconductor layer and having a size larger than the opening; A one-conductivity type channel layer (for example, a channel layer 26 made of n-InGaAs) having a high electron affinity in the tetrahedral groove and a first barrier layer (for example, an i-type) having a smaller electron affinity than the one-conductivity type channel layer. The first barrier layer 27) made of AlGaAs and the electron storage layer (for example, the electron storage layer 28 made of i-InGaAs) and the electron storage having a higher electron affinity than the first barrier layer. A step of sequentially stacking and re-growing a second barrier layer (for example, the second barrier layer 29 made of i-AlGaAs) having a smaller electron affinity than the layer, and then an electron located at the tip of the tetrahedral groove Forming a gate electrode (for example, gate electrode 30) opposite to the quantum dot (for example, quantum dot 28D) which is a part of the storage layer on the second barrier layer, and then re-growing each semiconductor layer And mesa etching in the same pattern as the gate electrode, and then the drain electrode (eg, drain electrode 31) is formed on the third semiconductor layer exposed around the gate electrode, and the source electrode (eg, source electrode) Forming the electrodes 32) on the back surface of the conductive semiconductor substrate, respectively, or
[0024]
(2)
In the above (1), the regular tetrahedron is formed through an opening (for example, opening 25A) of an insulating film (for example, insulating film 25) used as a mask when forming a regular tetrahedral groove (for example, regular tetrahedral groove 23A). One conductivity type channel layer (for example, channel layer 26) and first barrier layer (for example, barrier layer 27), electron storage layer (for example, electron storage layer 28), and second barrier layer (for example, barrier layer 29) in the body groove. Quantum which is a part of the electron storage layer located at the tip of the tetrahedral groove by depositing a gate electrode material (for example, Al) through the opening of the insulating film and re-growing the layers in order. Forming a gate electrode (for example, gate electrode 30) facing the dot (for example, quantum dot 28D) on the second barrier layer, or
[0025]
(3)
In the above (1) or (2), the respective semiconductor layers (for example, the channel layer 26, the barrier layer 27, the electron storage layer 28, and the barrier layer) which are stacked and regrown in the regular tetrahedral groove (for example, the regular tetrahedral groove 23A). 29) is mesa-etched by self-alignment with the gate electrode (for example, the gate electrode 30), and then the drain electrode (for example, the drain electrode 31) is also self-aligned with the gate electrode for the third semiconductor layer (for example, the n-GaAs layer 24). Characterized in that it is formed on, or
[0026]
(4)
In any one of (1) to (3), after the drain electrode (for example, the drain electrode 31) is formed, the surface of the third semiconductor layer (for example, the n-GaAs layer 24) is self-aligned with the drain electrode. Or mesa-etching to separate the elements, or
[0027]
(5)
In the above (1), (2), or (4), each semiconductor layer (for example, the channel layer 26, the barrier layer 27, the electron storage layer) re-grown in the regular tetrahedral groove (for example, the regular tetrahedral groove 23A). 28, the barrier layer 29) is mesa-etched with the gate electrode (for example, the gate electrode 30) in a self-aligned manner, a side wall made of an insulating film is formed on the side surface of the mesa, and then the drain electrode is self-aligned with the gate electrode. (For example, the drain electrode 31) is formed on the third semiconductor layer (for example, the n-GaAs layer 24), or
[0028]
(6)
  In any one of the above (1) to (5), formation of a regular tetrahedral groove (for example, a regular tetrahedral groove 23A) and each semiconductor layer (for example, a channel layer 26, a barrier layer 27, an electron storage layer 28, a barrier) The layer 29) is regrown and the opening (for example, the opening 25A) of the insulating film (for example, the insulating film 25) used as a mask for forming the gate electrode (for example, the gate electrode 30) is enlarged, and then the drain is self-aligned with the gate electrode. An electrode (for example, drain electrode 31) is formed on a third semiconductor layer (for example, n-GaAs layer 24).The
[0031]
By adopting the above means, the power consumption at the time of writing and erasing in the flash memory using the TSR structure is reduced, and the controllability of the fine structure formation is improved to increase the density and the manufacturing yield. Improvements can be realized.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 to FIG. 5 are side sectional views showing a main part of the semiconductor memory device in the main points of the process for explaining the first embodiment of the present invention. The following description will be given with reference to these figures. To do.
[0033]
Refer to FIG.
1- (1)
By applying the MOVPE method, the first semiconductor layer 22, the second semiconductor layer 23, and the third semiconductor layer 24 are formed on the substrate 21.
[0034]
Examples of main data regarding each semiconductor portion in this case are as follows.
(1) Substrate 21
Material: n-GaAs
Impurity concentration: 1 × 10¹⁸〔cm^-3]
(2) First semiconductor layer 22
Material: n-GaAs
Impurity: Se
Impurity concentration: 5 × 10¹⁸〔cm^-3]
Thickness: 200 [nm]
(3) Second semiconductor layer 23
Material: i-GaAs
Thickness: 20 [nm]
(4) Third semiconductor layer 24
Material: n-GaAs
Impurity: Se
Impurity concentration: 5 × 10¹⁸〔cm^-3]
Thickness: 2 [μm]
[0035]
Here, the thickness of the second semiconductor layer 23 made of i-GaAs is determined by the size of a quantum dot formed by re-growing an InGaAs layer in a TSR to be formed later, and accordingly, ni- The n diode current is made sufficiently smaller than the TSR memory current.
[0036]
Refer to FIG.
1- (2)
By applying the plasma CVD method, the surface of the third semiconductor layer 24 has a thickness of 200 nm.₂An insulating film 25 made of is formed.
[0037]
1- (3)
By applying the electron beam lithography technique, the insulating film 25 is etched to form an opening 25A having a diameter of 0.3 [μm].
[0038]
The openings 25A are formed in a state in which a large number are arranged in order to form a memory cell array, but the arrangement pitch must be sufficiently larger than the size of the openings 25A. The reason is to ensure sufficient alignment accuracy when forming the drain electrode later.
[0039]
Refer to FIG.
2- (1)
By applying a wet etching method using an etchant as a phosphoric acid-based etchant, the third semiconductor layer 24 is isotropically etched using the insulating film 25 having the opening 25A as a mask to form the recess 24A.
[0040]
Refer to FIG.
2- (2)
By applying a wet etching method using bromomethanol as an etchant, anisotropic etching of the third semiconductor layer 24 and the second semiconductor layer 23 is performed through the opening 25A to form a tetrahedral groove (TSR). 23A is formed.
[0041]
At this time, the area of the plane of the regular tetrahedral groove 23A is substantially the same as the area of the portion where the regular tetrahedral groove 23A is not formed, and is sufficiently larger than the arrangement pitch of the regular tetrahedral grooves 23A. The layer thickness can be accurately controlled by making the growth rate sufficiently low when the growth rate when a quantum well layer or the like for later forming a heterojunction is regrowth is sufficiently slow.
[0042]
Refer to FIG.
3- (1)
By applying the MOVPE method, the channel layer 26, the first barrier layer 27, the electron storage layer 28, and the second barrier layer 29 are formed on the facet surface of the tetrahedral groove 23A through the opening 25A of the insulating film 25. Grow. In addition, the part located in the bottom part of the regular tetrahedral groove | channel 23A in the electron storage layer 28 comprises quantum dot 28D.
[0043]
As described above, since the size of the regular tetrahedral groove 23A is sufficiently larger than the arrangement pitch, the rate of regrowth of each semiconductor layer in this step is slow. It can be implemented easily and accurately.
[0044]
The main data regarding each grown semiconductor layer is exemplified as follows.
(1) Channel layer 26
Material: n-InGaAs
Electron affinity: Large
Impurity: Se
Impurity concentration: 1 × 10¹⁸〔cm^-3]
Thickness: 15 [nm]
(2) First barrier layer 27
Material: i-AlGaAs
Electron affinity: small compared to channel layer 26
Thickness: 15 [nm]
(3) Electron storage layer 28
Material: i-InGaAs
Electron affinity: Greater than the first barrier layer 27
Thickness: 5 [nm]
(4) Second barrier layer 29
Material: i-AlGaAs
Electron affinity: Small compared to the electron storage layer 28
Thickness: 10 [nm]
[0045]
Refer to FIG.
3- (2)
When an Al film having a thickness of 200 [nm] is formed by applying the vacuum deposition method, the Al film enters the tetrahedral groove 23A from the opening 25A of the insulating film 25 and is deposited on the second barrier layer 29. The resultant is the gate electrode 30 corresponding to the quantum dot 28D.
[0046]
Refer to FIG.
4- (1)
By applying a CMP (Chemical Mechanical Polishing) method, the surface of the third semiconductor layer 24 is reached from the surface and polished to a depth near the edge of the gate electrode 30 for planarization.
[0047]
Refer to FIG.
4- (2)
Each semiconductor layer is regrown by applying a dry etching method in which an etching gas is, for example, a chlorine-based gas, and reaching the first barrier layer 27 from the second barrier layer 29 using the gate electrode 30 as a mask. Etching is performed to form a mesa shape. At this time, the exposed third semiconductor layer 24 is also etched and thinned.
[0048]
Refer to FIG.
5- (1)
The drain electrode 31 and the source electrode 32 are formed by applying a vacuum deposition method and a lithography technique.
[0049]
Each electrode is made of AuGe / Au having a thickness of 50 [nm] / 200 [nm] and is made ohmic by alloying heat treatment at a temperature of 450 [° C.] for 1 [minute].
[0050]
In step 4- (1), polishing is performed to flatten the surface. In step 4- (2), the regrowth semiconductor layers are etched to form a mesa shape. Since the third semiconductor layer 24 was also etched at this time, the final tetrahedral groove 23A size was smaller than the initially set size, and the arrangement pitch was larger at this stage. Therefore, there is a sufficient area margin around the tetrahedral groove 23A, and the alignment when forming the drain electrode 31 can be performed easily and precisely, and the manufacturing yield is improved.
[0051]
Refer to FIG.
  5- (2)
    Resist process and etching gas in lithography technologyChlorine-based gas  TheThe third semiconductor layer 24 and the second semiconductor layer 23 are mesa-etched to achieve isolation between elements by applying the dry etching method.
[0052]
In the semiconductor memory device completed through the above steps, when electrons are transferred into and out of the floating quantum dot 28D, the current flowing in parallel in the portion other than that corresponding to the floating quantum dot 28D is remarkably reduced. Power consumption during memory writing and erasing is reduced.
[0053]
6 and 7 are cutaway side views showing the main part of the semiconductor memory device at the main points of the process for explaining the second embodiment of the present invention, and will be described below with reference to these figures. To do. The steps 1- (1) to 3- (2) of the first embodiment described with reference to FIGS. 1 to 3 are the same as those of the second embodiment, and are omitted. To do.
[0054]
Refer to FIG.
6- (1)
After forming the gate electrode 30, it is immersed in hydrofluoric acid, and SiO 2₂The insulating film 25 made of is etched, and the second barrier layer 29 in the regular tetrahedral groove 23A is stopped in a state where the entire surface is exposed.
[0055]
Refer to FIG.
6- (2)
By applying the CMP method, the Al film on the insulating film 25 is polished and removed.
[0056]
Refer to FIG.
7- (1)
By applying a wet etching method using an etchant as a phosphoric acid-based etching solution, mesa etching of the regrowth semiconductor layer such as the second barrier layer 29 is performed using the gate electrode 30 as a mask to form a tetrahedral groove 23A. The third semiconductor layer 24 is exposed on the inner facet surface.
[0057]
7- (2)
By applying a vacuum deposition method, an AuGe / Au film having a thickness of 50 nm / 200 nm is formed, a drain electrode 31 is formed in a self-aligned manner with respect to the gate electrode 30, and After the source electrode 32 made of the same AuGe / Au film is formed on the back surface of the substrate 21, an alloying heat treatment is performed at a temperature of 450 [° C.] and a time of 1 [minute] to make ohmic.
[0058]
Refer to FIG.
7- (3)
By applying the CMP method, the insulating film 25 and the AuGe / Au film thereon are polished and removed.
[0059]
7- (4)
SiO having a thickness of, for example, 200 nm by applying the plasma CVD method₂A film is formed.
[0060]
7- (5)
Etching gas CF_Four+ O₂By applying a dry etching method using gas, the SiO formed in the step 7- (4)₂Side walls 33 are formed by anisotropic etching of the film.
[0061]
The side wall 33 protects by filling between the mesased regrowth semiconductor layers and the drain electrode 31, so that the portion is not damaged in the subsequent etching process.
[0062]
7- (4)
By applying a dry etching method in which an etching gas is, for example, a chlorine-based gas, the third semiconductor layer 24 and the second semiconductor layer 23 are mesa-etched to complete element isolation.
[0063]
In the semiconductor memory device completed through the above steps, the drain electrode 31 can be formed on almost the entire surface of the third semiconductor layer 24 exposed on the facet surface in the tetrahedral groove 23A. The contact resistance of the element is reduced, and a high-density memory having an element size of about 1 [μm] can be obtained.
[0064]
FIG. 8 and FIG. 9 are main part cut side views showing the semiconductor memory device in the main points of the process for explaining the third embodiment of the present invention, and will be described below with reference to these figures. To do. Note that steps 1- (1) to 3- (2) of the first embodiment described with reference to FIGS. 1 to 3 are the same in the third embodiment, and are omitted, and will be described from the next step. To do.
[0065]
Refer to FIG.
8- (1)
After forming the gate electrode 30, it is immersed in hydrofluoric acid, and SiO 2₂The insulating film 25 made of is etched, and the diameter of the opening 25A of 0.3 [μm] is expanded to 0.5 [μm].
[0066]
Refer to FIG.
8- (2)
By applying the CMP method, the Al film on the insulating film 25 is polished and removed.
[0067]
Refer to FIG.
9- (1)
By applying a wet etching method using an etchant as a phosphoric acid-based etching solution, mesa etching of the regrowth semiconductor layer such as the second barrier layer 29 is performed using the gate electrode 30 as a mask to form a tetrahedral groove 23A. The third semiconductor layer 24 is exposed on the inner facet surface.
[0068]
9- (2)
An AuGe / Au film having a thickness of 50 [nm] / 200 [nm] is formed by applying a vacuum deposition method using the insulating film 25 having the opening 25A having an enlarged diameter as a mask, and the gate electrode 30 The drain electrode 31 is formed in a self-aligned manner, and the source electrode 32 made of a similar AuGe / Au film is formed on the back surface of the substrate 21, and then the temperature is set to 450 [° C.] and the time is set to 1 [minute]. It is made ohmic by alloying heat treatment.
[0069]
Refer to FIG.
9- (3)
By applying the CMP method, the insulating film 25 and the AuGe / Au film thereon are polished and removed.
[0070]
9- (4)
By applying a dry etching method in which an etching gas is, for example, a chlorine-based gas, the third semiconductor layer 24 and the second semiconductor layer 23 are mesa-etched to complete element isolation.
[0071]
In the semiconductor memory device completed through the above steps, since the drain electrode 31 is remarkably miniaturized, a high-density memory having an element size of about 0.5 [μm] can be obtained.
[0072]
【The invention's effect】
In the method for manufacturing a semiconductor memory device according to the present invention, a first semiconductor layer of one conductivity type, a second semiconductor layer that is not doped, and a third semiconductor having a high impurity concentration of one conductivity type on a conductive semiconductor substrate. The layers are sequentially stacked, an insulating film is formed on the third semiconductor layer, and openings are formed in the insulating film with a pitch larger than the size of the opening, and etching is performed through the openings. A tetrahedral groove (TSR) that reaches from the third semiconductor layer into the second semiconductor layer and has a size larger than the opening is formed, and the one-conductivity-type channel layer and the first tetrahedral groove are formed in the regular tetrahedral groove. A barrier layer, an electron storage layer, and a second barrier layer are sequentially stacked and regrown, and a gate electrode facing a quantum dot that is a part of the electron storage layer located at the tip of the tetrahedral groove is formed as a second electrode. Formed on the barrier layer and regrown the stack The semiconductor layer mesa is etched to the same pattern and the gate electrode, the third semiconductor layer being exposed to the drain electrode around the gate electrode, are formed respectively on the conductive semiconductor substrate backside source electrode.
[0073]
By adopting the above configuration, the power consumption at the time of writing and erasing in the flash memory using the TSR structure is reduced, and the controllability of the fine structure formation is improved to increase the density and the production yield. Improvements can be realized.
[Brief description of the drawings]
FIG. 1 is a cutaway side view showing a main part of a semiconductor memory device in a process essential point for explaining Embodiment 1 of the present invention;
FIG. 2 is a cutaway side view showing a main part of a semiconductor memory device in a process essential point for explaining the first embodiment of the present invention;
FIG. 3 is a cutaway side view showing a main part of a semiconductor memory device in a process essential point for explaining the first embodiment of the present invention;
FIG. 4 is a cutaway side view showing a main part of a semiconductor memory device in a process essential point for explaining the first embodiment in the present invention;
FIG. 5 is a cutaway side view showing a main part of a semiconductor memory device in a process essential point for explaining the first embodiment of the present invention;
FIG. 6 is a cutaway side view showing a main part of a semiconductor memory device in a process key point for explaining a second embodiment in the present invention;
FIG. 7 is a cutaway side view showing a main part of a semiconductor memory device in a process key point for explaining a second embodiment in the present invention;
FIG. 8 is a cutaway side view showing a main part of a semiconductor memory device in a process key point for explaining a third embodiment in the present invention;
FIG. 9 is a cutaway side view showing a main part of a semiconductor memory device in a process key point for explaining a third embodiment in the present invention;
FIG. 10 is a cutaway side view showing a main part of a semiconductor memory device at a process point for explaining the prior art related to a flash memory using a TSR structure;
FIG. 11 is a cutaway side view showing a main part of a semiconductor memory device at a process point for explaining the prior art relating to a flash memory using a TSR structure;
FIG. 12 is a cutaway side view showing a main part of a semiconductor memory device at a process point for explaining the prior art relating to a flash memory using a TSR structure;
FIG. 13 is a fragmentary cutaway explanatory view showing a semiconductor memory device in a process essential point for explaining the prior art relating to a flash memory using a TSR structure.
[Explanation of symbols]
21 Substrate
22 First semiconductor layer
23 Second semiconductor layer
23A Regular tetrahedral groove (TSR)
24 Third semiconductor layer
24A recess
25 Insulating film
25A opening
26 Channel layer
27 First barrier layer
28 Electron storage layer
28D floating quantum dot
29 Second barrier layer
30 Gate electrode
31 Drain electrode
32 source electrode

Claims (6)

A step of sequentially forming a one-conductivity-type first semiconductor layer, a non-doped second semiconductor layer, and a one-conductivity-type high impurity concentration third semiconductor layer on a conductive semiconductor substrate;
Next, forming an insulating film on the third semiconductor layer, and then forming openings in the insulating film with a pitch larger than the size of the opening;
Next, etching through the opening to form a tetrahedral groove (TSR) reaching from the third semiconductor layer into the second semiconductor layer and having a size larger than the opening;
Next, in the regular tetrahedral groove, the electron affinity is higher than that of the first barrier layer having a high electron affinity and the first barrier layer and the first barrier layer having a low electron affinity compared to the single conductivity type channel layer. A step of stacking and re-growing a second barrier layer having a small electron affinity compared to a large electron storage layer and an electron storage layer in order;
Next, forming a gate electrode on the second barrier layer that faces a quantum dot that is a part of the electron storage layer located at the tip of the regular tetrahedral groove;
Next, a step of mesa-etching each semiconductor layer that has been regrown to the same pattern as the gate electrode;
And a step of forming a drain electrode on the third semiconductor layer exposed around the gate electrode and a source electrode on the back surface of the conductive semiconductor substrate. A method for manufacturing a storage device. The one-conductivity type channel layer, the first barrier layer, the electron storage layer, and the second barrier layer are sequentially formed in the regular tetrahedral groove through the opening of the insulating film used as a mask when forming the regular tetrahedral groove. After the regrowth, the gate electrode material is deposited through the opening of the insulating film, and the gate electrode facing the quantum dot which is a part of the electron storage layer located at the tip of the tetrahedral groove is formed. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed on the second barrier layer.   Each semiconductor layer stacked and regrown in the tetrahedral groove is mesa-etched by self-alignment with the gate electrode, and then the drain electrode is formed on the third semiconductor layer by self-alignment with the gate electrode. A method of manufacturing a semiconductor memory device according to claim 1. 4. The semiconductor memory according to claim 1, wherein after the drain electrode is formed, element isolation is performed by performing mesa etching from the surface of the third semiconductor layer in a self-aligned manner with the drain electrode. Device manufacturing method. After each semiconductor layer stacked and regrown in the tetrahedral groove is mesa-etched by self-alignment with the gate electrode, a side wall made of an insulating film is formed on the side surface of the mesa and then drained by self-alignment with the gate electrode. 5. The method of manufacturing a semiconductor memory device according to claim 1, wherein the electrode is formed on a third semiconductor layer. Forming a tetrahedral groove, re-growing each semiconductor layer, and expanding the opening of the insulating film used as a mask for forming the gate electrode, and then forming the drain electrode on the third semiconductor layer in self-alignment with the gate electrode 6. A method of manufacturing a semiconductor memory device according to claim 1, wherein:

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