JP3730004B2 - Reset system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention provides a reset system.ToIn particular, a reset system that resets when the power is turned on or when the power level is low.ToRelated.
[0002]
[Prior art]
  In recent years, the miniaturization of the manufacturing process of integrated circuits and the accompanying reduction in power supply voltage have progressed. However, this trend has advanced in all cases in which digital integrated circuits are ahead of analog integrated circuits.
[0003]
  This is because it is sufficient for digital circuits to be able to distinguish between binary values of H and L, whereas analog circuits must maintain a wide input / output dynamic range without losing linearity.
[0004]
  In an analog integrated circuit including a line driver circuit for driving a transformer, the drive current is inversely proportional to the square of the power supply voltage. For this reason, even if it aims at a low power supply voltage, the level of the power supplied to a driver circuit cannot be reduced.
[0005]
  Therefore, one reason is that it is difficult to apply a miniaturization process having inferior withstand voltage performance to an analog integrated circuit.
  For this reason, in an analog / digital mixed circuit, the power supply voltage level and the manufacturing process are determined in accordance with the linearity of the analog circuit and the power consumption of the line driver circuit.
[0006]
  That is, in the conventional analog / digital mixed circuit, the same manufacturing process with the same level of the power supply voltage is used for the analog portion and the digital portion.
[0007]
[Problems to be solved by the invention]
  However, in the conventional analog / digital mixed circuit as described above, since the miniaturization process cannot be applied to the digital circuit, the area of the digital circuit block on the chip cannot be suppressed.
[0008]
  Therefore, it is considered that a miniaturization process for high-density integration is applied to the digital circuit block and a high withstand voltage process is applied to the analog circuit block (all or a part).
[0009]
  In this case, two types of voltage sources, ie, a low level voltage source for a miniaturization process and a high level voltage source for a high withstand voltage process are required. Is generally obtained from a power supply circuit and a regulator circuit for converting the output of the power supply circuit to a different level.
[0010]
  In the case of such a power supply configuration, when the power supply rises, the output start point at which the regulator circuit outputs a level sufficient to drive the miniaturization process circuit is sufficient for the power supply circuit to drive the high voltage process. It will be delayed from the time when the level is output.
[0011]
  On the other hand, a mode setting circuit that generates a test / adjustment logic signal for the power-on reset circuit preferably uses a miniaturization process (driven by a low-level voltage source) in order to achieve high-density integration.
[0012]
  However, since the rise of the regulator circuit, which is a low-level voltage source, is delayed as described above, the output of the mode setting circuit during that time becomes uncertain, and the power-on reset circuit cannot expect a desired operation. was there.
[0013]
  The power-on reset circuit performs reset control by comparing the internally generated divided signal with the reference voltage signal based on the power supply voltage, but the level of the divided signal and reference voltage signal is reversed when the power is turned on. As a result, there was a problem that normal reset could not be performed.
[0014]
  Further, in an integrated circuit in which power supplies are mixed, there is a problem that an excessive current is generated when a logic is uncertain at a low voltage level, causing a circuit failure.
  The present invention has been made in view of these points, and an object of the present invention is to provide a reset system that eliminates the logic uncertainty of reset control in a state where the output level of the regulator circuit is insufficient.
[0015]
[Means for Solving the Problems]
  In order to solve the above problems, the present invention provides a regulator for converting a high level voltage VH to a low level voltage VL in a reset system 100 that resets when the power is turned on or when the power is at a low level as shown in FIG. 10 and a reset signal generation unit 20 that generates a reset signal RST for driving and resetting by a high level voltage VH, and a control signal for controlling the reset signal generation unit 20 by driving by a low level voltage VL. A control signal generation unit 30 that generates CNT; and a control signal transmission selection unit 40 that selects whether to transmit the control signal CNT to the reset signal generation unit 20 based on the external signal Ex. A reset system 100 is provided.
[0016]
  Here, the regulator 10 converts the high level voltage VH into the low level voltage VL. The reset signal generator 20 is driven by the high level voltage VH and generates a reset signal RST for resetting. The control signal generation unit 30 is driven by the low level voltage VL and generates a control signal CNT for controlling the reset signal generation unit 20. The control signal transmission selection unit 40 selects whether or not to transmit the control signal CNT to the reset signal generation unit 20 based on the external signal Ex.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG.IsIt is a principle diagram of a set system. The reset system 100 performs a reset when the power is turned on or when the power becomes a low level.
[0018]
  The regulator 10 converts the high level voltage VH into the low level voltage VL. The reset signal generator 20 is driven by the high level voltage VH and generates a reset signal RST for resetting.
[0019]
  The control signal generation unit 30 is driven by the low level voltage VL and generates a control signal CNT for controlling the reset signal generation unit 20. The control signal transmission selection unit 40 selects whether or not to transmit the control signal CNT to the reset signal generation unit 20 based on the external signal Ex.
[0020]
  NextToA configuration and operation when the set system 100 is constructed on an integrated circuit will be described. FIG. 2 is a diagram showing a configuration when the reset system 100 is constructed on an integrated circuit.
[0021]
  The integrated circuit 100a includes an analog circuit block 110 and a digital circuit block 120. The power supply circuit 130 supplies + 5V as the high level voltage VH to the plurality of power supply terminals VDD1 to VDD3 of the analog circuit block 110.
[0022]
  Each circuit in the analog circuit block 110 operates at + 5V, which is a high level voltage VH, and each circuit in the digital circuit block 120 operates at + 3V, which is a low level voltage VL.
[0023]
  The regulator 10 converts + 5V to + 3V. The power-on reset unit 20 corresponds to the reset signal generation unit 20 and generates a reset signal RST for resetting each internal block.
[0024]
  The mode setting unit 30 corresponds to the control signal generation unit 30, generates a control signal CNT for controlling the power-on reset unit 20, and sets the mode of the power-on reset unit 20. That is, the test / adjustment mode of the power-on reset unit 20 when the power is turned on is set by the control signal CNT.
[0025]
  The selector unit 40 corresponds to the control signal transmission selection unit 40 and selects whether or not to transmit the control signal CNT to the power-on reset unit 20 based on the external signal Ex. The selection control will be described later.
[0026]
  The digital signal processing unit 121 processes digital signals in the digital circuit block 120.
  The line driver / receiver 111 performs transmission processing for transmitting information on the logical signal processed by the digital signal processing unit 121 on a line (not shown) or reception processing for the transmitted signal.
[0027]
  The A / D unit 112 performs analog / digital conversion of the signal received and processed by the line driver / receiver 111, and transmits it to the digital signal processing unit 121.
  Next, selection control for selecting whether or not to transmit the control signal CNT to the power-on reset unit 20 using the external signal Ex will be described.
[0028]
  For the power supply terminal VDDa, a slide switch 140 as shown in the figure is provided outside the integrated circuit 100a. During normal operation of the integrated circuit 100a, the slide switch 140 is connected to the power supply side. In this case, SW1 of the selector unit 40 is switched to GND in the drawing, and the control signal CNT from the mode setting unit 30 is not transmitted to the power-on reset unit 20.
[0029]
  In the test / adjustment mode of the power-on reset unit 20, the slide switch 140 is connected to the GND side. In this case, SW1 of the selector unit 40 is switched to the output terminal side of the mode setting unit 30, and the control signal CNT from the mode setting unit 30 is transmitted to the power-on reset unit 20.
[0030]
  Next, the configuration of the selector unit 40 will be described. FIG. 3 is a diagram showing the configuration of the selector unit 40. A configuration example when there are two types of control signals CNT is shown.
  The control signal CNT1IN and VDDa from the mode setting unit 30 are connected to the input terminal of the OR gate IC1. VDDa is connected to the input terminal of the inverter IC2. The control signal CNT2IN from the mode setting unit 30 and the output of the inverter IC2 are connected to the input terminal of the AND gate IC3.
[0031]
  CNT1OUT, which is the output of the OR gate IC1, has the same logic as CNT1IN when VDDa is L, and is fixed to H when VDDa is H.
  The CNT2OUT that is the output of the AND gate IC3 has the same logic as the CNT2IN when VDDa is L, and is fixed to L when VDDa is H.
[0032]
  As explained above,The set system 100 is configured to select whether to transmit the control signal CNT from the mode setting unit 30 based on the external signal Ex when setting the mode of the power-on reset unit 20.
[0033]
  The mode setting unit 30 is driven after the power-on reset unit 20 is driven because +3 V is supplied from the regulator 10 when the power is turned on.
  In the conventional case, the control signal CNT having a logic indefinite period until the mode setting unit 30 completely starts up is transmitted to the power-on reset unit 20, and the power-on reset unit 20 performs an unstable operation.
[0034]
  However,In the reset system 100,If the normal mode is set, the reset circuit (power-on reset unit 20) is not controlled by a low-level logic signal that seems to be in a logic indeterminate state.
[0035]
  Therefore, stable operation is guaranteed when the power is turned on. Note that the test adjustment work of the reset circuit is performed after the power supply level is sufficiently stabilized, and thus is not affected by the logic uncertainty.
[0036]
  NextToThe setting device will be described. FIG.IsIt is a principle diagram of a set device. The reset device 20a performs reset when the power is turned on or when the power recovers from a temporarily low level. The reset device 20a corresponds to the power-on reset unit 20 described in FIG.
[0037]
  The power supply voltage dividing unit 21 generates a power supply voltage division Vd divided from the power supply voltage V. The reference voltage generation unit 22 generates a reference voltage Vf from the power supply voltage V.
  The power supply level detector 23 compares the power supply divided voltage Vd with the reference voltage Vf and detects the power supply level L at which reset release should be started. When the power supply voltage V reaches the power supply level L, the constant current generator 24 generates a constant current I for charging the capacitor C based on the reference voltage signal Vf.
[0038]
  The reset unit 25 performs reset when the terminal voltage Vc of the capacitor C charged by the constant current I is lower than the reference voltage Vf, and performs reset cancellation when the terminal voltage Vc of the capacitor C exceeds the reference voltage Vf.
[0039]
  The mask processing unit 26 masks the reverse rotation state when the reverse rotation state occurs in which the reference voltage Vf falls below the power supply divided voltage Vd when the power supply is turned on or the power supply recovers from the temporary low level. When the resolution is eliminated, a mask signal MSK for canceling the mask is generated. The discharge controller 27 forcibly discharges the capacitor C by the mask signal MSK.
[0040]
  Next, the basic reset operation of the reset device 20a will be described. FIG. 5 is a diagram showing a basic reset operation of the reset device 20a. The horizontal axis represents time, and the vertical axis represents voltage.
[S1] Until the power supply voltage V reaches the detection level L, charging of the capacitor C, which is an external capacitor, is not started. In addition, resetting is in progress here.
[S2] When the power supply voltage V reaches the detection level L, a constant current I flows from the constant current generator 24, and charging of the capacitor C starts.
[S3] Charging of the capacitor C proceeds and the capacitance terminal level rises.
[S4] The reset is released when the capacitance terminal level of the capacitor C reaches the level of the reference voltage signal Vf.
[0041]
  Next, the reverse state of the power source voltage divider Vd and the reference voltage Vf will be described. FIG. 6 is a diagram showing the reverse state. The horizontal axis represents time, and the vertical axis represents voltage.
  The reset device 20a compares the power supply voltage division Vd with the reference voltage Vf by the power supply level detection unit 23, and sets the detection level where the power supply voltage division Vd> the reference voltage Vf as the power supply level L at which reset release should be started. .
[0042]
  However, when the power supply is turned on, the reference voltage Vf is different from the ideal as shown in the state A in the figure, and a sufficient level cannot be obtained. For this reason, the power supply voltage division Vd and the reference voltage Vf are reversed.
[0043]
  Ideally, the power supply level L should be detected at time t2, but since a reverse state has occurred in the state A, the power supply level L is detected at time t1 when the power supply has not yet risen sufficiently. It was generated.
[0044]
  Next, the detailed configuration and operation of the reset device 20a that eliminates the inconvenience of the reverse rotation state will be described. FIG. 7 is a diagram showing a detailed configuration of the reset device 20a.
  The power supply voltage divider 21 inputs the power supply voltage Vd obtained by dividing the power supply V by the resistors R1 and R2 to the + terminal of the comparator Comp1 (corresponding to the power supply level detector 23).
[0045]
  The reference voltage generator 22 inputs the reference voltage signal Vf generated from the power supply voltage V to the negative terminal of the comparator Comp1, the negative terminal of the comparator Comp2, the negative terminal of the comparator Comp3, and the constant current generator 24.
[0046]
  The output of the constant current generation unit 24 is connected to the + terminal of the comparator Comp2, the + terminal of the comparator Comp3, the capacitor C, and SW2 in the discharge control unit 27.
  The output of the comparator Comp1 is connected to the S (set) terminal of the SR flip-flop IC4, and the output of the comparator Comp2 is connected to the XR (reset) terminal of the SR flip-flop IC4.
[0047]
  The output terminal Q of the SR flip-flop IC4 is connected to one input terminal of the OR gate 27a in the discharge control unit 27, and the MSK output of the mask processing unit 26 is connected to the other input terminal of the OR gate 27a in the discharge control unit 27. To do.
[0048]
  The XMSK output of the mask processing unit 26 and the output of the comparator Comp3 are connected to the input terminal of the NAND gate IC5.
  Here, the reference voltage generation unit 22 generates and outputs a stable level of BGR (band gap reference voltage) that is less affected by power supply and temperature fluctuations.
[0049]
  The comparator Comp1 detects that the power supply voltage has reached the detection level L (= power supply level L) by comparing the power supply divided voltage Vd with the reference voltage Vf. In addition, the noise resistance is enhanced by providing hysteresis characteristics.
[0050]
  The constant current generator 24 obtains a constant current I based on the reference voltage Vf, and uses this to charge the external capacitor (capacitor C).
  The SR flip-flop IC4 has a set input and an inverting reset input. Set has priority over reset and there is no prohibition. In the set state, the capacitor C is discharged.
[0051]
  The comparator Comp2 resets the SR flip-flop IC4 when the terminal voltage Vc of the capacitor C is lower than the reference voltage Vf.
  When the terminal voltage Vc of the capacitor C exceeds the reference voltage Vf, the comparator Comp3 changes the output of the NAND gate IC5 from H to L and changes from the reset state to the normal state.
[0052]
  Next, the operation will be described. First, immediately after the power is turned on (state A), the reverse state as described with reference to FIG. 6 is present, and the power supply divided voltage Vd> the reference voltage Vf. Therefore, the MSK of the mask processing unit 26 needs to be H. The mask processing unit 26 will be described later.
[0053]
  Therefore, H is output from the OR gate 27a of the discharge controller 27, SW2 is closed, and the capacitor C is forcibly discharged.
  At the input of the comparator Comp3, Vf>VcTherefore, the output is L. Since the XMSK of the mask processing unit 26 outputs L, the NAND gate IC5 resets the H enable.signalRST outputs.
[0054]
  In the state B, the MSK of the mask processing unit 26 is L and the XMSK is H at a certain point in time until the transition to the state C. Further, the power supply divided voltage Vd <the reference voltage Vf, and the comparator Comp1 outputs H.
[0055]
  At the input of the comparator Comp2, Vf>VcTherefore, the output of the comparator Comp2 becomes L.
  In the SR flip-flop IC4, the S terminal is H, the XR terminal is L, and H is output from the Q terminal.
[0056]
  Therefore, H is output from the OR gate 27a of the discharge control unit 27, SW2 is closed, and the state where the capacitor C is forcibly discharged is continued from the state A.
  At the input of the comparator Comp3, Vf>VcTherefore, the output is L. Therefore, H enable reset from NAND gate IC5.signalRST outputs.
[0057]
  In the state C, MSK of the mask processing unit 26 is L, and MXSK is H. The comparator Comp1 detects the power supply level L and outputs L when the power supply divided voltage Vd ≧ the reference voltage Vf.
[0058]
  In the SR flip-flop IC4, the S terminal is L, the XR terminal is H, and L is output from the Q terminal.
  Therefore, L is output from the OR gate 27a of the discharge controller 27, SW2 is opened, and the discharge control of the capacitor C is not performed.
[0059]
  The constant current I from the constant current generator 24 flows into the capacitor C when SW2 opens, and charging of the capacitor C is started.
  When the terminal voltage Vc of the capacitor C becomes Vf ≦ Vc, the outputs of the comparators Comp2 and Comp3 become H. Accordingly, L is output from the NAND gate IC5 to enter the normal state.
[0060]
  Next, the mask processing unit 26 will be described. FIG. 8 is a diagram showing a mask processing unit 26a according to the first embodiment. The mask processing unit 26a uses the threshold voltage Vth of the transistor.
[0061]
  The gate G1 and drain D1 of the n-channel FET 1 are connected to + 5V, and the source S1 is connected to one of the resistors R3. The other end of the resistor R3 is connected to GND.
  The gate G2 of the n-channel FET 2 is connected to the source S1 of the FET 2. The drain D2 is connected to one of the resistors R4, and the other of the resistor R4 is connected to + 5V. Source S2 connects to GND.
[0062]
  By adopting such a transistor connection configuration, it is considered that the reference voltage Vf has not reached a sufficient level when + 5V> 2 · Vth, MSK becomes H (XMSK is L), and mask processing is performed.
[0063]
  When + 5V <2 · Vth, it is considered that the reference voltage Vf has reached a sufficient level, MSK becomes L (XMSK is H), and the mask is released.
  As described above, the mask processing unit 26a according to the first embodiment is configured by a plurality of transistors, and if even one transistor is off (+ 5V> 2 · Vth), it is recognized as a reverse state and masked. When all the transistors are turned on (+5 V <2 · Vth), it is recognized that the reverse rotation state has been resolved and the mask is released.
[0064]
  FIG. 9 is a diagram showing a mask processing unit 26b according to the second embodiment. The mask processing unit 26 b uses a part 22 a of the reference voltage generation unit 22. In the figure, VB is a driving bias voltage of the operational amplifier unit 22b.
[0065]
  In the circuit shown in the figure, immediately after the power is turned on, the voltage IMA <the voltage IPA, so that the current from the transistor MP1A does not flow to the transistor MP2A but all flows to the resistors R1A and R3A.
[0066]
  Therefore, since the same amount of current flows in the mask processing unit 26b, the voltage IMA = voltage IMB <voltage IPB = voltage IPA and MSK becomes H, and mask processing is performed.
[0067]
  As the power supply level rises, the voltage IMA = the voltage IPA is stabilized, and the reference voltage Vf is also stabilized at a constant level. This is because a surplus portion of the current from the transistor MP1A flows to the transistor MP2A in order to maintain the voltage IMA = the voltage IPA.
[0068]
  Since the mask processing unit 26b operates in the same manner, the voltage IMB> the voltage IPB and MSK = L and the mask is released. That is, the fact that Vf has stabilized means that the state is already in the state B, and the reverse phenomenon has ended.
[0069]
  FIG. 10 is a diagram showing the relationship between the reference voltage Vf and the voltage for operating the mask processing unit 26b. The horizontal axis represents time, and the vertical axis represents voltage.
  In the A state where the reverse rotation state occurs, the voltage IMA and the voltage IMB, and the voltage IPA and the voltage IPB are such that the voltage IPA> the voltage IMA and the voltage IPB> the voltage IMB.
[0070]
  In the state where the reverse rotation state ends and the reference voltage Vf sufficiently rises, voltage IMA = voltage IPA voltage IMB> voltage IPB.
  As described above, the mask processing unit 26b according to the second embodiment uses the two voltage signals (IMB and IPB) that can reliably detect that the reverse rotation state is finished and Vf is stable. The signal level is compared, and the reverse masking and unmasking are performed.
[0071]
  As explained above,The set device 20a is configured to mask the reverse rotation state when the reverse rotation state occurs where the reference voltage Vf is lower than the power supply divided voltage Vd despite the low power supply, and to cancel the mask when the reverse rotation state is resolved. .
[0072]
  Thereby, even when the power supply is turned on or the power supply becomes a low level, the reset can be surely performed, so that the reliability can be improved.
  NextToo muchThe surplus current supply preventing device will be described. 11 and 12Is overIt is a principle diagram of a surplus current supply preventing apparatus.
[0073]
  The excessive current supply preventing device 130 of FIG.− 1The low level voltage logic signal generator 121-1And fixed signal output section113And.
  Low level voltage logic signal generator 121-1Generates a low level voltage logic signal. The fixed signal output unit 113 monitors the voltage of the low level voltage logic signal. When the low level voltage logic signal is detected indeterminate from the voltage monitoring, the fixed signal output unit 113 outputs a fixed signal of a certain level to supply excess current. Prevent by fixed signal.
[0074]
  12 includes a reset signal generation control unit 20b and an excessive current supply prevention unit 114.
  The reset signal generation control unit 20b generates a reset signal RST. The excess current supply preventing unit 114 prevents the supply of excess current generated when the low-level voltage logic signal is indeterminate by the reset signal RST.
[0075]
  The excessive current supply preventing device 130 described above.-1, 130a can be used to prevent excessive current supply.
  NextToo muchSurplus current supply prevention device 130-1, 130a will be described on the configuration and operation when built on an integrated circuit. FIG. 13 shows an excessive current supply preventing device 130.-1It is a figure which shows the structure at the time of constructing | stacking on an integrated circuit. The excessive current supply preventing device 130-1Is constructed on the integrated circuit 100a described in FIG.
[0076]
  The mode setting unit 30 includes a power-on reset unit 2ZeroA control signal CNTL for performing control is generated, and the power-on reset unit 2ZeroSet the mode.
  Level converter 113, SolidThe constant signal output unit 113 converts the + 3V control signal CNTL into a + 5V control signal CNTH. Further, voltage monitoring of the low-level voltage logic signal is performed, and when the uncertainty of the low-level voltage logic signal is detected from the voltage monitoring, a fixed signal of a certain level is output.
[0077]
  Power-on reset part 20 isA reset signal RST for resetting each internal block is generated. Further, when a fixed signal is received from the level converter 113, the reset signal is forcibly generated and the reset signal RST is generated.
[0078]
  The digital signal processing unit 121 processes digital signals in the digital circuit block 120. The line driver 111a transmits information on the logic signal processed by the digital signal processing unit 121 onto a line (not shown).
[0079]
  The excessive current supply preventing unit 114 prevents the supply of excessive current generated when the low-level voltage logic signal generated by the digital signal processing unit 121 is indeterminate by the reset signal RST.
[0080]
  Next, the countermeasure against excess current will be described. In the integrated circuit 100a of FIG. 13, since the signal from the digital circuit block 120 becomes uncertain when the power is turned on, an excessive current may flow through the line driver 111a.
[0081]
  This is because the size of the transistor of the line driver 111a is extremely larger than that of a normal circuit, and therefore, the current that flows when the P-channel and the N-channel are turned on at the same time due to logic uncertainty is extremely large.
[0082]
  FIG. 14 is a diagram showing the configuration of the level converter 113. Excess current supply prevention device 130-1Corresponds to the fixed signal output unit 113 included.
  The voltage monitoring unit 113a monitors the voltage of the low level voltage logic signal generated by the digital signal processing unit 121.
[0083]
  The low level logic signal receiving unit 113b receives the control signal CNTL (XIN, IN) from the mode setting unit 30. The level converter 113c converts the logic of the control signal CNTL into a high level voltage (+ 5V) logic signal CNTH.
[0084]
  Here, when the voltage monitoring unit 113a detects that the low-level voltage logic signal is indeterminate, a fixed signal that is a constant high-level voltage logic signal regardless of the logic of the control signal CNTL output by the mode setting unit 30. Is output.
[0085]
  That is, in the figure, when the low-level voltage source VDL is insufficient, VDL <(Ra + Rb) Vth / Rb, so that the nodes n1 and n3 are H regardless of the logic of the inputs IN and XIN, and therefore the nodes n2 and OUT The signal is fixed at L.
[0086]
  FIG. 15 is a diagram showing the configuration of the level converter 113 and the line driver 111a. Signals from the digital signal processing unit 121 are connected to terminals a to d.
[0087]
  A level converter 113a is provided between the terminals ad and the line driver 111a.-1~ 113d-1Is placed. By adopting such a configuration, it is possible to prevent supply of excess current caused by a signal with uncertain logic of the terminals a to d.
[0088]
  Next, a case where the excessive current supply preventing device 130a is used will be described. FIG. 16 is a diagram showing a configuration of the excess current supply preventing unit 114 and the line driver 111a.
[0089]
  A signal from the digital signal processing unit 121 is connected to terminals a to d of the excess current supply preventing unit 114.
  And power on reset part 20Due to the reset signal RST, the outputs of the NOR gates IC6 and IC7 are fixed to L, and the transistors MN1 and MN2 are both turned off, so that excessive current supply can be prevented.
[0090]
  As explained aboveOverSurplus current supply prevention device 130-1Is configured to prevent the supply of excess current generated when the low-level voltage logic signal is indeterminate by the reset signal RST.
[0091]
  As a result, the excessive current generated at the same time is prevented by using the reset signal RST used when the power is turned on or when the power is at a low level, so that it is possible to efficiently prevent the excessive current supply.
[0092]
【The invention's effect】
  As described above, the reset system of the present invention is configured to select whether or not to transmit a control signal for controlling the reset signal generation unit based on an external signal, and thereby generate a control signal Since it can be operated from the outside after the drive voltage level of the control signal generation unit is stabilized, it is possible to reliably perform reset testing and adjustment.
[Brief description of the drawings]
[Figure 1]ReIt is a principle diagram of a set system.
[Figure 2] ResetsystemIt is a figure which shows the structure at the time of constructing | stacking on an integrated circuit.
FIG. 3 is a diagram illustrating a configuration of a selector unit.
[Fig. 4]ReIt is a principle diagram of a set device.
FIG. 5 is a diagram showing a basic reset operation of the reset device.
FIG. 6 is a diagram showing a reverse rotation state.
FIG. 7 is a diagram showing a detailed configuration of a reset device.
FIG. 8 is a diagram illustrating a mask processing unit according to the first embodiment.
FIG. 9 is a diagram illustrating a mask processing unit according to a second embodiment.
FIG. 10 is a diagram illustrating a relationship between a reference voltage and a voltage for operating a mask processing unit.
FIG. 11ExcessiveIt is a principle diagram of a surplus current supply preventing apparatus.
FIG.ExcessiveIt is a principle diagram of a surplus current supply preventing apparatus.
FIG. 13 is a diagram showing a configuration when an excessive current supply preventing apparatus is constructed on an integrated circuit.
FIG. 14 is a diagram showing a configuration of a level converter.
FIG. 15 is a diagram illustrating a configuration of a level converter and a line driver.
FIG. 16 is a diagram illustrating a configuration of an excess current supply preventing unit and a line driver.
[Explanation of symbols]
  100 reset system
  10 Regulator
  20 Reset signal generator
  30 Control signal generator
  40 Control signal transmission selection section
  CNT control signal
  Ex External signal
  RST reset signal
  VH high level voltage
  VL low level voltage

Claims (3)

In a reset system that resets when the power is turned on or when the power is at a low level,
A regulator that converts a high level voltage to a low level voltage;
A reset signal generator that is driven by the high-level voltage and generates a reset signal for performing the reset;
A control signal generator that drives with the low level voltage and generates a control signal for controlling the reset signal generator;
A control signal transmission selection unit for selecting whether to transmit the control signal to the reset signal generation unit based on an external signal;
A reset system comprising:   The reset system according to claim 1, wherein the reset system is built on an integrated circuit.   The reset system according to claim 1, wherein the control signal transmission selection unit uses a power supply voltage as the external signal.

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