JP3730185B2 - Thin film transistor manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a thin film transistor formed on an insulating material such as a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display, and more specifically, the maximum temperature of the manufacturing process is about 600 ° C. or less. The present invention relates to a method for manufacturing a thin film transistor formed by a low temperature process.
[0002]
[Prior art]
In recent years, with the increase in screen size and resolution of liquid crystal displays, the driving method has shifted from the simple matrix method to the active matrix method, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmissive display is used.
[0003]
However, in order to increase the display screen and reduce the price, it is essential to use inexpensive ordinary glass as the insulating substrate. Therefore, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix liquid crystal display with stable performance on an inexpensive glass substrate while maintaining this economy.
[0004]
As the channel layer semiconductor layer of the thin film transistor, amorphous silicon or polycrystalline silicon is usually used. However, if the drive circuit is integrated with the thin film transistor, polycrystalline silicon having a high operation speed is advantageous. .
[0005]
Conventionally, when such a thin film transistor is formed, after forming the channel portion silicon layer, the substrate is formed of oxygen (O) to form the gate insulating layer. ₂ ) Laughter gas (N ₂ O), water vapor (H ₂ O) and the like, and the temperature is set to a high temperature of about 800 ° C. to about 1100 ° C. to oxidize a part of the channel portion silicon layer to form a gate insulating layer. . On the other hand, various methods have been tried to produce a thin film semiconductor device using polycrystalline silicon at a maximum process temperature of about 600 ° C. or less that can withstand the use of an inexpensive ordinary glass substrate. For example, after forming a channel portion semiconductor layer by a low pressure vapor phase chemical vapor deposition method (LPCVD method), a gate insulating film is formed by an electron cyclotron resonance plasma CVD method (ECR-PECVD method), and further hydrogen such as hydrogen plasma irradiation. A method of applying crystallization processing. Alternatively, an amorphous silicon thin film is deposited on the channel layer semiconductor layer, followed by heat treatment at 600 ° C. for about 24 hours, and then a gate insulating film is formed by atmospheric pressure chemical vapor deposition (APCVD), and hydrogenated. There are ways to do this. (Japan J, Appl, Phys, 30L 84 '91)
[0006]
[Problems to be solved by the invention]
However, many problems have been pointed out in the conventional methods described above. First of all, SiO by thermal oxidation method ₂ In the formation of the film, high-temperature heat treatment of at least 800 ° C. or more is accompanied with the formation of the film, so that the heat resistance of the thin film layer or the substrate located below the oxide film becomes a problem.
[0007]
For example, when making a switching transistor for a large area liquid crystal display, the substrate cannot withstand such high temperatures except for a very expensive fused quartz plate. Further, even in a three-dimensional LSI element, since the lower layer transistor deteriorates at a high temperature, this thermal oxidation method is practically unusable.
[0008]
Next, a channel semiconductor layer is formed by the LPCVD method, a gate insulating film is formed by the ECR-PECVD method, and the mobility is 4 to 5 cm in the hydrogen plasma treatment method. ² / V. This is still low as a thin film semiconductor device. In addition, depending on the hydrogenation process performed to improve the characteristics of the thin film semiconductor device, some of the various thin films constituting the thin film semiconductor device are etched and some of the many thin film semiconductor devices are destroyed. There is a problem that said. Also, in the method of depositing an amorphous silicon thin film on the channel semiconductor layer, performing a heat treatment at about 600 ° C., forming a gate insulating film by the APCVD method, and further performing a hydrogenation treatment such as hydrogen plasma irradiation. Has an interface trap level of 10 ¹² It is still inadequate as a thin film semiconductor device, such as a large size and a depletion type semiconductor device characteristic. In addition, the problems associated with the Yabari hydrogenation treatment remain as before, and a thin film semiconductor device cannot be formed uniformly and stably over a large area.
[0009]
Therefore, there is a demand for a thin film semiconductor device that has a high mobility, has a clean MOS interface, has a low interface trap level, and does not exhibit depletion. There has been a need for a manufacturing method that does not require an annealing process and can uniformly and stably produce a good thin film semiconductor device as described above over a large area.
[0010]
The present invention has been made in view of the above circumstances, and the object of the present invention is a thin film having good semiconductor device characteristics in a low temperature process in which the maximum process temperature is about 600 ° C. or less in a MIS type thin film semiconductor device. The object is to provide a semiconductor device and a method of manufacturing such a thin film semiconductor device uniformly and stably over a large area.
[0011]
[Means for Solving the Problems]
According to the present invention, in a method of manufacturing a thin film transistor, a step of forming an amorphous silicon thin film serving as a channel portion on a substrate, and after forming a first insulating film by irradiating the amorphous silicon thin film with oxygen plasma, a vacuum is formed. A step of forming a gate insulating film by depositing a second insulating film made of a silicon oxide film by plasma CVD on the first insulating film continuously without breaking the process, and forming the gate insulating film A step of crystallizing the amorphous silicon thin film by heat-treating the substrate, a step of performing hydrogen plasma treatment on the substrate on which the gate insulating film is formed after the step of heat treatment, and the gate subjected to the hydrogen plasma treatment Forming a gate electrode on the insulating film, and the above-mentioned maximum temperature of the process is 600 ° C. or lower. And butterflies.
[0012]
[Examples and Reference Examples]
Hereinafter, examples and reference examples of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following examples and reference examples.
[0013]
(Reference Example 1)
FIGS. 1A to 1E are cross-sectional views showing a manufacturing process of a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-misaligned staggered structure according to the first embodiment.
[0014]
In Reference Example 1, 235 mm □ fused silica glass was used as the base substrate 101, but the type and size of the base material are not limited as long as the substrate or base material can withstand the process maximum temperature of 600 ° C. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a ceramic substrate such as silicon carbide, alumina, or aluminum nitride can be used as a base substrate.
[0015]
First, the base substrate 101 is immersed in an organic solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone, and ultrasonic cleaning is performed. After washing, drying is performed in nitrogen or under reduced pressure, and further ultrasonic washing with ethanol is performed, followed by washing with pure water that has been bubbled with nitrogen. Next, the base substrate 101 was immersed for 5 minutes in boiling nitric acid having a concentration of 60%, and further washed in pure water that was bubbled with nitrogen. When a substrate is used that is corroded by an acid such as a metal or is changed in quality, this cleaning with nitric acid is not required. Further, in this cleaning with strong acid, sulfuric acid can be used as an acid in addition to nitric acid.
[0016]
On the quartz substrate thus cleaned, a silicon dioxide film (SiO 2) serving as a base protective film by atmospheric pressure chemical vapor deposition (APCVD). ₂ 2000) of the film) 102 was deposited. This base SiO ₂ The film 102 is necessary to stabilize the film quality of a silicon thin film to be deposited later and the performance of a thin film transistor formed using the silicon thin film when various materials as described above are used as a substrate. At the same time, for example, when normal glass is used as the substrate 101, movable ions such as sodium contained in the glass are added to the substrate when various ceramic plates are used as the substrate 101. It also plays a role in preventing auxiliary materials from diffusing and mixing into the transistor section. When a metal plate is used as the substrate 101, the underlying SiO is used to ensure insulation. ₂ Is indispensable. In a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors or wirings. Base SiO ₂ The substrate temperature during deposition of the film 102 was 300 ° C., and silane 600 SCCM diluted to 20% with nitrogen was deposited together with 840 SCCM oxygen by the APCVD method. SiO at this time ₂ The deposition rate of the film was 3.9 kg / sec.
[0017]
Subsequently, a silicon thin film 103 containing impurities serving as donors or acceptors was deposited by a low pressure CVD method. In this Reference Example 1, phosphorus was selected as an impurity for the purpose of producing an n-type transistor. However, in the case of n-type, elements other than phosphorus, group 5 and 6 elements, and in the case of P-type, boron and other group 2 and group 3 elements are impurities. It can be added as an element. The silicon thin film 103 containing impurities is a part to be a source / drain region. In addition to the method of adding impurities by the CVD method as in Reference Example 1, first, an intrinsic silicon film containing no impurities is formed. There are a method in which impurities are diffused and added later from a solid phase in contact with the vapor phase or the intrinsic silicon film, and a method in which impurities are ionized and implanted into the intrinsic silicon film. By using these methods of adding impurities by diffusion or ion implantation after forming an intrinsic silicon film, it becomes possible to add impurities only to a desired portion of the intrinsic silicon film. Self-aligned transistors with the source or drain end self-aligned are possible, or the current density and specific resistance in the silicon film can be changed by changing the impurity concentration at each part to change the current to only the desired part. It is possible to flow.
[0018]
In this Reference Example 1, since phosphorus was selected as an impurity, phosphine (PH ₃ ) And silane mixed gas, a silicon thin film 103 containing impurities was deposited in a thickness of 1500 Å.
[0019]
In this reference example 1, 200 SCCM of monosilane, 6SCCM of helium / phosphine mixed gas of 99.5% helium and 0.5% phosphine and 6 SCCM of helium were further flown in a low pressure CVD furnace having a volume of 184.5 l. The deposition was performed at a temperature of 600 ° C. and a furnace pressure of 100 mtorr. The deposition rate at this time was 29.6 K / min, and the sheet resistance value immediately after film formation was 2,025 Ω / □.
[0020]
Next, a resist is formed on the silicon thin film, and carbon tetrafluoride (CF) ₄ ) And oxygen (O ₂ The thin film was patterned in accordance with the mixed plasma (1) to form the source / drain regions 103 (FIG. 1A). Subsequently, impurities such as residual resist are removed by washing in boiling nitric acid for 5 minutes, and a natural oxide film on the surface of the source / drain region 103 is removed by immersion in 1.67% hydrofluoric acid for 20 seconds. Then, a silicon thin film to be a channel portion was deposited.
[0021]
At this time, the volume of the reduced pressure CVD reactor is 184.5 l, and the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, and hydrogen are introduced into the furnace from the lower part of the reaction furnace as necessary, and exhausted from the upper part of the reaction furnace. A heater divided into three zones is installed outside the reaction furnace made of quartz glass, and by adjusting them independently, a soaking zone is formed at a desired temperature near the center of the reaction furnace. This soaking zone spreads at a height of about 350 mm, and the temperature deviation within that range is, for example, within 0.2 ° C. when set to 600 ° C. Therefore, if the interval between the inserted substrates is 10 mm, 35 substrates can be processed in one batch. In this reference example 17, 17 substrates were installed in the soaking zone at intervals of 20 mm.
[0022]
Exhaust was performed by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reactor was measured using a diaphragm type pressure gauge (MKS Baratron Manometer) whose measurement value does not depend on the type of gas. When the reactor is kept at 550 ° C., the gas introduction valve is closed and the vacuum is drawn by both pumps, the reactor internal pressure is 0 mtorr. ^-Four It is about torr or less.
[0023]
The substrate in which the source / drain region 103 was formed and the natural oxide film on the surface of the region was removed was immediately inserted into the low pressure CVD furnace with the front side facing downward. The temperature in the reaction furnace at the time of insertion is maintained at about 395 ° C. to 400 ° C. This is to minimize the formation of a natural oxide film on the source / drain region 103. Therefore, it is desirable that the temperature in the reaction furnace at the time of insertion is as low as possible. For example, it is possible to set the temperature in the reaction furnace to room temperature at the time of insertion, but in this case, it takes several hours or more to raise the temperature in the reaction furnace to the deposition temperature, and the number of arrows to return to room temperature after the deposition. Time is required. When the substrate is inserted, about 4 SLM to 10 SLM of nitrogen are flowed into the reaction furnace to keep the reaction furnace in an inert atmosphere. Furthermore, a nitrogen curtain is formed with about 6 SLM to 20 SLM of nitrogen in the vicinity of the inlet in the reactor to minimize the flow of air into the reactor when the substrate is inserted. When moisture or oxygen in the air enters the reaction furnace, they are adsorbed on the Si layer on the inner wall of the reaction furnace or react with Si and remain in the reaction furnace, and are removed during the deposition of the silicon film that becomes the channel part. It appears as a gas and causes the film quality of the deposited silicon film to deteriorate.
[0024]
After inserting the substrate, vacuuming and leakage inspection were performed. In the leak inspection, all valves connected to the reactor were closed and the reactor was completely isolated, and changes in the reactor pressure were examined. In Reference Example 1, the reactor pressure was 1 mtorr or less after complete isolation for 2 minutes at 400 ° C. in the reactor. After confirming that there is no abnormality in the leakage inspection, the temperature in the reactor is raised from the insertion temperature of 400 ° C. to the deposition temperature. In Reference Example 1, since a silicon thin film serving as a channel portion was deposited at 550 ° C., it took an hour to raise the temperature. It takes about 35 minutes for the furnace temperature to reach the deposition temperature of 550 ° C., but in order to sufficiently release the degassed from the reactor wall, a temperature rising period of at least one hour, preferably several hours is desirable. . During this temperature raising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995% or more. These gas species can be a pure gas such as hydrogen, helium, nitrogen, neon, argon, xenon, krypton, or a mixed gas of these gases. In Reference Example 1, helium having a purity of 99.9999% or more was continuously supplied at 350 SCCM, and the reactor internal pressure was 80.7 ± 1.2 mtorr.
[0025]
After reaching the deposition temperature, a predetermined amount of silane, which is a raw material gas, or a mixed gas of silane and dilution gas is introduced into the reaction furnace to deposit the silicon thin film 104. As the dilution gas, the same kind of combination as the gas flowed in the previous temperature raising period is possible, but the purity of each gas is preferably 99.999% or more. In this reference example 1, a silicon thin film 104 was deposited by flowing 100 SCCM of silane having a purity of 99.999% or more without using a dilution gas. At this time, the pressure in the reactor was maintained at 398.6 ± 1.9 mtorr by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump. In Reference Example 1, the silicon thin film 104 serving as the channel portion was deposited to a thickness of 248 mm at a deposition rate of 21.2 kg / min (FIG. 1B).
[0026]
In this reference example 1, the silicon thin film is deposited by the LPCVD method, and monosilane is also used as the source gas. However, it is also possible to deposit by a plasma CVD method, an APCVD method, a sputtering method, or the like. Further, the source gas is not limited to monosilane, and higher order silanes such as disilane and trisilane, dichlorosilane, and the like are also possible. Of course, it is also possible to deposit a silicon thin film by a combination of the above various CVD methods and the above various raw materials.
[0027]
Next, the substrate thus obtained was subjected to a heat treatment to advance the crystallization of the silicon thin film 104 and increase the crystal grains. The heat treatment furnace is a vertical furnace and is normally maintained at 400 ° C., and nitrogen gas having a purity of 99.999% or more is continuously supplied for 20 SLM to keep the inside of the heat treatment furnace in an inert atmosphere. The substrate that reached temperature equilibrium with room temperature was inserted into a vertical heat treatment furnace at 400 ° C. over 17 minutes. After the insertion, the temperature is kept at 400 ° C. for 30 minutes, and the temperature in the heat treatment furnace is raised to 600 ° C. after the inside of the furnace reaches a uniform temperature of 400 ° C. regardless of the position of the substrate. By maintaining the temperature at 400 ° C. for 30 minutes, the same thermal history can be obtained everywhere regardless of the position of the substrate, and the silicon thin film can be crystallized uniformly. Since 20 SLM of nitrogen always flows through the heat treatment furnace and the volume of the heat treatment furnace is about 176 l, the preheating at 400 ° C. completely replaces the inside of the heat treatment furnace with a nitrogen atmosphere. The temperature is raised from 400 ° C. to 600 ° C. over about 1 hour. After reaching temperature equilibrium at 600 ° C., the crystallization of the silicon thin film is advanced by heat treatment for 7 hours or more. In Reference Example 1, after reaching 600 ° C., heat treatment was performed for 23 hours.
[0028]
The silicon thin film thus obtained is patterned with a resist and then carbon tetrafluoride (CF ₄ ) And oxygen (O ₂ The channel portion silicon thin film 105 was formed by etching using the mixed plasma of FIG. (FIG. 1 (C)) The silicon thin film formed in Reference Example 1 is CF. ₄ And O ₂ Etching when the output was 700 W with a vacuum plasma discharge of 15 Pa with a ratio of 50 SCCM to 100 SCCM had an etching rate of 2.1 Å / sec.
[0029]
Next, this substrate is cleaned with boiling nitric acid having a concentration of 60%, and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to naturally oxidize the source / drain regions 103 and the channel portion silicon thin film 105. After a clean silicon surface appears after removal of SiO 2, SiO becomes a gate insulating film immediately in an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). ₂ A film 106 was deposited. (FIG. 1D) An outline of the ECR-PECVD apparatus used in Reference Example 1 is shown in FIG. When depositing the gate insulating film, a microwave of 2.45 GHz is guided to the reaction chamber 202 through the waveguide 201, and 100 SCCM of oxygen introduced from the gas introduction tube 203 is first turned into plasma. At this time, the output of the microwave is 2250 W, and the oxygen plasma in the reaction chamber 202 is applied to the oxygen plasma in the reaction chamber 202 by the external coil 204 installed outside the reaction chamber 202 to satisfy the ECR condition for the electrons in the plasma. ing. This oxygen plasma is drawn out of the reaction chamber by the divergent magnetic field, and irradiates the substrate 205 placed perpendicular to the plasma for 10 seconds. There was a heater 206 on the back of the substrate 205, and the entire substrate was kept at 100 ° C. At this time, the pressure in the reaction chamber was 1.85 mtorr. Another gas introduction pipe 207 is provided immediately after the oxygen plasma outlet, and after oxygen plasma is sufficiently stabilized in 10 seconds, silane 60SCCM having a purity of 99.999% or more is oxygen plasma from the gas introduction pipe 207. Mix in. The SiO2 film that becomes the gate insulating layer by irradiating the substrate with the oxygen silane mixed plasma thus obtained for 30 seconds ₂ 1500 Å of film 106 was deposited (FIG. 1 (d)). At this time, the pressure in the reaction chamber was 2.35 mtorr.
[0030]
Next, 1500 Å of chromium was deposited by sputtering, and the gate electrode 107 was formed by patterning. At this time, the sheet resistance value was 1.356 ± 0.047Ω / □. In this reference example 1, chromium is used as the gate electrode material, but it is needless to say that other conductive materials are possible, and the formation method is not limited to the sputtering method, and the vapor deposition method and the CVD method are also possible. Subsequently, SiO which becomes the interlayer insulating film 108 by the APCVD method. ₂ A film of 5000 ５ was deposited. This deposition was performed in this Reference Example 1 with the underlying SiO ₂ The conditions were the same as those for depositing the film 102, and only the deposition time was changed. After the interlayer insulating film is formed, contact holes are opened, and source / drain extraction electrodes 109 are formed by sputtering or the like to complete the transistor (FIG. 1E). In Reference Example 1, aluminum was used as the source / drain extraction electrode material and deposited to a thickness of 8000 mm by sputtering to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film was 42.48 ± 2.02 mΩ / □.
[0031]
An example Vgs-Ids curve of the characteristics of the thin film transistor (TFT) fabricated in this way is shown in 3-a of FIG. Here, the source-drain current Ids was measured at a source-drain voltage Vds = 4 V and a temperature of 25 ° C. The transistor size was a channel portion length L = 10 μm and a width W = 10 μm. When the transistor was turned on with Vds = 4V and Vgs = 10V, the on-current was measured at the center of the 235mm square substrate and the five square transistors. ION = 4.65 ± 0.39μA, good transistor characteristics A thin film semiconductor device having Further, the field-effect transfer μo obtained from the saturation current region of the transistor and the trap density Nt (J. Levinson et al. J. Appl. Phys. 53 . 1193.1982) is μo = 25.85 ± 0.96 cm, respectively. ² / V. sec, Nt = (6.81 ± 0.15) × 10 ¹¹ 1 / cm ² It was in. For comparison, FIG. 3B shows the transistor characteristics of a thin film semiconductor device prepared according to an example of the prior art. That is, all the thin film semiconductor devices were fabricated in the same process as in Reference Example 1 except that the channel portion silicon thin film was deposited at 600 ° C. by low pressure CVD and not subjected to heat treatment for 24 hours. At this time, the apparatus for depositing the channel portion silicon thin film by the low pressure CVD method is the same as the apparatus used in Reference Example 1, the source gas monosilane flows through 12.5 SCCM, the reactor pressure is 9.0 mtorr, and the deposition rate. Was deposited at a thickness of 256 Å at 11.75 Å / min. The on-current of the TFT of this prior art example is Ids = 0.91 ± 0.12 μA, and the field-effect mobility is μo = 4.75 ± 0.20 cm. ² / V. sec, capture density Nt = (5.18 ± 0.13) × 10 ¹¹ 1 / cm ² It was in. In addition, a channel portion silicon thin film is similarly deposited by a low pressure CVD method at a 600 ° C. monosilane flow rate of 12.5 SCCM, and after depositing a gate insulating film in the same process as in Reference Example 1, the ECR-PECVD apparatus is used. A thin film semiconductor device was fabricated in the same process as Reference Example 1 except that hydrogen plasma treatment was performed. This is also an example of a conventional technique for performing a hydrogenation process. The hydrogenation treatment was performed after the gate insulating film was deposited by the ECR-PECVD apparatus shown in FIG. 2 and then evacuated, and further the temperature of the substrate 205 was raised to 300 ° C. over 1 hour by the heater 206. Hydrogen gas 125SCCM having a purity of 99.9999% or more was introduced into the reaction chamber 202 through the gas introduction pipe 203 to generate hydrogen plasma. The microwave output was 2000 W and the pressure in the reaction chamber was 2.63 mtorr. Hydrogen plasma irradiation was performed for 30 minutes. When the TFT characteristics of the thin film semiconductor device thus fabricated were measured, the on-current Ids = 0.96 ± 0.13 μA, the field effect mobility μo = 4.68 ± 0.22 cm. ² / V. sec, capture density Nt = (5.12 ± 0.13) × 10 ¹¹ 1 / cm ² It was in. That is, in comparison with the prior art in which the channel portion silicon film is deposited by the low pressure CVD method at 600 ° C. regardless of the presence or absence of hydrogen plasma treatment, the reference example 1 has a transistor that increases the field effect mobility by about 5 times, for example. This brings about a significant improvement in characteristics.
[0032]
Next, another example of the prior art and this reference example 1 are compared. That is, as another example of the prior art, the channel portion silicon thin film is formed in the same manner as in Reference Example 1, but the conventional technique for depositing the gate insulating film by the APCVD method and the hydrogen film after depositing the gate insulating film by the APCVD method are used. The great superiority of the present Reference Example 1 over the conventional technology for performing plasma processing will be seen. In the conventional process of forming a thin film semiconductor device by depositing a gate insulating film by the APCVD method, a thin film semiconductor device is formed by the same process as in Reference Example 1 except that the gate insulating film is deposited by 1500 nm by the APCVD method. did. In the APCVD method, the substrate temperature is kept at 300 ° C., nitrogen containing 20% silane in nitrogen, silane mixed gas is supplied at 300 SCCM, oxygen is supplied at 420 SCCM, and about 140 SLM of dilution nitrogen is supplied along with these raw material gases to form SiO 2. ₂ A film was deposited. The deposition rate was 1.85 kg / sec. The transistor characteristics of the thin film semiconductor device according to the prior art prepared in this way are shown in FIG. The on-state current of this transistor is ION = 1.49 ± 0.05 μA, and the field effect mobility μo = 24.60 ± 0.72 cm. ² / V · sec, capture density Nt = (9.20 ± 0.15) × 10 ¹¹ 1 / cm ² It was in. When this prior art is compared with the present reference example 1, it becomes clear that the present reference example 1 has produced a very good thin film semiconductor device that significantly reduces the trap level and rises rapidly in the vicinity of the gate voltage Ov. In the conventional technique for depositing the gate insulating film by the APCVD method, the mobility height could be increased as much as in the first reference example, but in fact, the minimum value of the source / drain current is around -11v and the trap density is also high. The slope of the rise is gentle and not practical as a thin film semiconductor device. On the other hand, an example of another prior art is shown in FIG. Here, the channel portion silicon thin film is formed in the same manner as in the first reference example, but the gate insulating film is deposited by the APCVD method, and then a hydrogen plasma treatment is performed. A thin-film semiconductor device was fabricated through the same process as in Reference Example 1, except that the gate insulating film was deposited under the same conditions as described above, and then immediately after the hydrogen plasma irradiation was performed under the same conditions as described above using an ECR-PECVD apparatus. . The characteristics of the TFT thus obtained are shown as 3-d in FIG. On-state current is Ids = 2.91 ± 0.30 μA, field-effect mobility μo = 24.51 ± 0.67 cm ² / V · sec, capture density Nt = (7.94 ± 0.15) × 10 ¹¹ 1 / cm ² It was in. It can be seen that even in comparison with the prior art using this plasma treatment, the present Reference Example 1 shows good characteristics in all parameters. In addition, in the transistor made by the conventional technology subjected to the hydrogen plasma treatment, the threshold voltage Vth of one of the five transistors measured is shifted by about + 2V. The value of is not included. That is, in the conventional technique using the hydrogen plasma treatment, the transistor characteristics are improved as compared with the conventional technique in which the hydrogen plasma treatment is not performed, but it is difficult to produce a homogeneous transistor of uniform quality over a large area. In addition, the sample subjected to the hydrogen plasma treatment has a large variation between lots, and stable production is difficult. In particular, the threshold voltage deviation and the fluctuation of the gate voltage value at which the source / drain current is minimized are very large between lots. On the other hand, it can be seen that according to the present Reference Example 1, the hydrogenation process causing the variation was eliminated, and still better transistors than the conventional one could be uniformly formed on a large area.
[0033]
(Reference Example 2)
A thin film semiconductor device was fabricated in accordance with the same process as that of the present invention of Reference Example 1 except that the deposition time of the silicon thin film (FIG. 1.104) serving as the channel portion was changed to change the deposited film thickness of the silicon thin film 104. In this reference example 2, the silicon thin film 104 was made into six different thicknesses of 190 mm, 280 mm, 515 mm, 1000 mm, 1100 mm, and 1645 mm, and thin film semiconductor devices were respectively produced. FIG. 4 shows the result of illustrating the ratio of the on-state current to the off-state current of the thin film semiconductor device thus obtained with respect to the thickness of the channel portion silicon film. As can be seen from this figure, in the thin film semiconductor device in which the channel portion silicon film semiconductor layer has a film thickness of 500 mm or less, the on / off ratio was drastically improved and good characteristics showing 7 digits or more were obtained.
[0034]
(Reference Example 3)
A thin film semiconductor device (offset type thin film semiconductor device) having a structure in which at least one of the source region and the drain region does not overlap with the gate electrode through the gate insulating film is the same manufacturing method as in Reference Example 1. Created. In this reference example 3, the staggered thin film semiconductor device shown in FIG. 5A was prepared as an off-set type thin film semiconductor device by performing alignment with high accuracy. Other structures are possible. For example, as shown in FIG. 5B, the source / drain region 503 is formed by implanting impurity ions using an intrinsic silicon thin film as a mask and the gate electrode 505 shown in FIG. An inverted staggered thin film semiconductor device in which the source / drain regions 507 are formed using the mask material 506 is also possible.
[0035]
In Reference Example 3, an off-set type thin film semiconductor device was produced by the same manufacturing method as Reference Example 1 except that fused silica glass having a diameter of 75 mm was used as the base substrate. That is, the substrate is first cleaned and the underlying SiO ₂ After the film was deposited by the APCVD method or the like, the phosphorus-added silicon film was deposited by the LPCVD method, and the source / drain region 501 was formed by further patterning. Here, the distance between the source and drain regions, which later becomes the channel length L, was 10.5 μm. Next, in the same manner as in Reference Example 1, a silicon thin film serving as a channel portion was deposited at a film thickness of 248 mm at a deposition rate of 21.2 kg / min. However, in Reference Example 1, the substrate was inserted into the reactor with the front side of the substrate facing down, but in Reference Example 3, a 75 mm diameter substrate was placed on the 235 mm square dummy quartz plate with the front side facing up and inserted into the reactor. did. Thereafter, heat treatment was performed by exactly the same manufacturing method as in Reference Example 1, a gate insulating layer was deposited, and a gate electrode 502 was further formed. The width of the gate electrode 502 was 10.0 μm, and high-precision alignment was performed so that the center of the source-drain distance of 10.5 μm and the center of the gate electrode width of 10.0 μm coincided. As a result, the distance (offset distance) between the gate electrode end position and the source region end in the channel region is 0.25 μm. Thereafter, an interlayer insulating film was deposited by the same manufacturing method as in Reference Example 1, and wiring was performed using aluminum after opening the contact hole, thereby completing a thin film semiconductor device.
[0036]
An example Vgs-Ids curve of the transistor characteristics of the thin film semiconductor device thus produced is shown in 6-a of FIG. 6 indicates the transistor characteristics of the self-unmatched staggered thin film semiconductor device manufactured in Reference Example 1. FIG. As can be clearly seen from the figure, in this third reference example, it is possible to significantly reduce the leakage current generated when the gate voltage is negative. Actually, in this reference example 3, when the gate voltage is −2.5 V or less, the source / drain current is suppressed to about 0.1 pA. 6-b of FIG. 6 shows the transistor characteristics obtained when the offset type thin film semiconductor device is manufactured according to the prior art of Reference Example 1 for comparison. That is, the channel portion silicon thin film is deposited by a low pressure CVD method at 600 ° C., and the center of the source-drain distance of 10.5 μm and the center of the gate electrode width of 10.0 μm are aligned with high precision alignment to form an offset type thin film semiconductor device. It is a transistor characteristic obtained when it is created. Therefore, 6-b in FIG. 6 can be directly compared with 3-b in the transistor characteristic diagram of the self-aligned staggered structure thin film semiconductor device of the prior art. In the off-set type thin film semiconductor device according to the prior art, it is possible to keep the leakage current as low as about 0.1 pA or less. The positive characteristics of the transistor, such as the degree, fell and ended, and it was not practical. For example, the on-state current of an offset thin film semiconductor device according to the prior art is Ids = 0.090 ± 0.01 μA, and the on-state current is reduced by an order of magnitude or more compared to a self-unmatched thin film semiconductor device. The mobility at this time is also μo = 3.33 ± 0.15 cm. ² Similar to / v · sec, the deterioration is about 30%. For this reason, the manufacture of offset thin film semiconductor devices according to the prior art has no value. On the other hand, as shown in 6-a of FIG. 6, the reference example 3 keeps the leakage current low and keeps the on-current high. In this reference example 3, Ids = 3.71 ± 0.43 μA is obtained as the on-current, and almost no inferiority is seen compared to the on-current of the self-unmatched thin film semiconductor device. In this reference example 3, the mobility is also μo = 22.00 ± 0.95 cm. ² A good value was shown as / v · sec.
[0037]
(Reference Example 4)
In Reference Example 3, an offset-type thin film semiconductor device was created by performing high-precision alignment. Of course, Reference Example 3 is effective in addition to this. In FIG. 5B, after depositing an intrinsic silicon film and patterning the gate electrode, an offset type thin film semiconductor device was created by adding impurity ions. This method will be described in detail.
[0038]
7A to 7D are sectional views showing the structural steps of the silicon thin film semiconductor device constituting the MIS type field effect transistor having the offset type staggered structure according to the fourth embodiment. First, after cleaning the substrate 701 as in Reference Example 1, the base protective film 702 is made of SiO. ₂ A film is deposited about 2000 mm. Subsequently, a first silicon film of about 300 mm or more is deposited and patterned to form a silicon film 703 to be a pad. In this reference example, the first silicon film was deposited to 1250 mm at a deposition temperature of 600 ° C. and a silane flow rate of 12.5 SCCM using the LPCVD apparatus in which the channel part silicon film was deposited in Reference Example 1. It is also possible to deposit a silicon film at a deposition temperature of about 550 ° C. using disilane (Si ₂ H ₆ Can be deposited at a deposition temperature of about 450 ° C., or a silicon film can be deposited at about 250 ° C. by PECVD. Any method may be used as long as the film forming temperature does not exceed the maximum process temperature of 600 ° C. Next, a second silicon film 704 is deposited. The film thickness of the second silicon film is about 300 mm or more, and the resistance value of the source / drain region after the impurity implantation is that of the channel region when the transistor is operated. If the resistance value is sufficiently low, the silicon film 703 to be the first silicon film or pad is not required. In the present reference example 4, the second silicon film 704 was deposited by the same method as the silicon thin film serving as the channel portion in the reference example 1. In other words, monosilane was used as a source gas by LPCVD, and the film was deposited to a thickness of 250 mm at a deposition temperature of 550 ° C. and a silane flow rate of 100 SCCM at a deposition rate of 21.2 kg / min. However, the second silicon film forming method can be any method as long as the film forming temperature does not exceed the maximum process temperature of 600 ° C., like the first silicon film. For example, the second silicon film may be deposited at a deposition temperature of 600 ° C., a silane flow rate of 12.5 SCCM, and a reactor pressure of 9.0 mtorr, or a higher order silane such as disilane or trisilane is used as a source gas. In addition, it is possible to form a film at a lower temperature. In this manner, the second silicon film 704 was formed by some method (FIG. 7B), patterned, and then the gate insulating layer 705 was formed by the same method as in Reference Example 1. That is, SiO by ECR-PECVD method ₂ 1500 liters of film was deposited. As a means for forming the gate insulating layer 705, when the second silicon film 704 is a polycrystalline silicon film, it can be formed by the APCVD method. Next, a metal film to be a gate electrode is formed. In this reference example 4, a silicon film added with phosphorus at a high concentration was used as the gate electrode material. Here, a deposition temperature of 600 ° C., monosilane 200 SCCM, helium 90.5% and phosphine 0.5% helium / phosphine mixed gas 6 SCCM and helium 100 SCCM are flowed by LPCVD, and the film thickness is 3000 mm at a furnace pressure of 100 mtorr. Deposited. The sheet resistance value immediately after film formation was 744 Ω / □. Subsequently, after applying a resist and patterning the resist, CF ₄ And O ₂ The phosphorus-doped silicon film was patterned by using the mixed plasma. CF ₄ And O ₂ The patterning was performed at an incident wave output of 700 W with a ratio of 200 SCCM and 200 SCCM, respectively. At this time, the phosphorus-added silicon film was etched at 15.4 Å / sec for 5 minutes 57 seconds to form a gate electrode 706. Since the thickness of the phosphorus-added silicon film was 3000 mm, the gate electrode width was narrowed by about 2500 mm on the left and right sides of the resist 707 due to this plasma etching (FIG. 7C). Next, impurity ions are added while leaving the resist 707 used for forming the gate electrode 706 without peeling. In this reference example 4, phosphorus is selected as an impurity and an n-type thin film semiconductor device is aimed at, but of course other elements are possible depending on the purpose. In this reference example 4, impurity ion addition was performed using an ion implantation apparatus without a mass spectrometer. As a source gas, phosphine having a concentration of 5% diluted in hydrogen is used, and 3 × 10 at an acceleration voltage of 110 kV. ¹⁵ 1 / cm ² Typed into the concentration. In this way, a part of the first silicon film and the second silicon film becomes the source / drain region 708, and the resist 707 used for forming the gate electrode has a film thickness of about 2 μm. The second silicon film to be formed is not subjected to ion addition and constitutes the channel portion 709 (FIG. 7C). Moreover, an offset type thin film semiconductor device is produced by this method. Next, after removing the resist 707 for forming the gate electrode, the substrate is subjected to heat treatment at 600 ° C. for 7 hours or more to activate the added impurity ions and the crystal when the channel portion silicon film 709 has insufficient crystallinity. Promote In this reference example 4, the heat treatment was performed at 600 ° C. for 23 hours in a nitrogen atmosphere in the same manner as the heat treatment performed in reference example 1. Subsequently, as an interlayer insulating film, SiO ₂ 710 is deposited by 5000 nm by APCVD method or the like, and further, hydrogen is supplied at an acceleration voltage of 80 kV and 5 × 10 5 in an ion implantation apparatus without a mass spectrometer. ¹⁵ 1 / cm ² After the implantation, contact holes are opened and wiring 711 is made of aluminum or the like to complete the offset thin film semiconductor device.
[0039]
The transistor characteristics of the offset thin film semiconductor device thus prepared were measured. When L = W = 10 μm, Vds = 4 V, the on-current was 3.4 μA, and the minimum value of the source / drain current was 0 when Vgs = −3.5 V. The off current defined by 0.09 pA and Vgs = −10 V was 0.28 pA, and the leakage current when the transistor was turned off was kept low, and a good on current could be obtained.
[0040]
As described in Reference Example 3 and Reference Example 4, after the source region and the drain region are formed in the offset thin film semiconductor device, a thin film semiconductor device having a high on-current and a small leakage current can be produced by performing heat treatment. However, it is by no means limited to the manufacturing method of the offset thin film semiconductor device described in detail in Reference Example 3 and Reference Example 4. For example, although a resist having a width wider than the width of the gate electrode is used as a mask for implantation as a method for producing an offset thin film semiconductor device in Reference Example 4, there are various other methods. For example, an offset-type thin film semiconductor device can be formed by using metal as a gate electrode and oxidizing the surface and side surfaces to narrow the gate electrode and then implanting impurity ions. Further, as shown in FIG. 5C, even in the inverted staggered structure, an offset type thin film semiconductor device is obtained by making the width of the mask material 506 wider than that of the gate electrode 505. It is effective for an offset type thin film semiconductor device produced by any of these manufacturing methods.
[0041]
(Example 1)
8A to 8F are cross-sectional views showing a manufacturing process of a silicon thin film semiconductor device for forming a MIS field effect transistor.
[0042]
In the first embodiment, 235 mm square quartz glass is used as the insulating substrate 801. However, as long as it is a substrate or a base material that can withstand a temperature of 600 ° C., its type and size are of course not questioned. For example, a three-dimensional LSI formed on a silicon wafer is also possible as a base substrate. First, the upper surface of the quartz glass substrate 801 that has been subjected to organic cleaning and acid cleaning is coated with SiO ₂ A film 802 was deposited by an atmospheric pressure chemical vapor deposition method (APCVD method). Base SiO ₂ The film 802 was formed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM, and nitrogen of about 140 SLM. The deposition rate at this time was 3.9 kg / sec, and the deposition time was 8 minutes 33 seconds. Next, a silicon thin film 803 containing an impurity serving as a donor or acceptor was deposited by a low pressure vapor phase chemical deposition method (LPCVD method) (FIG. 8A). In Example 1, phosphorus is selected as an impurity, and phosphine (PH ₃ ) 0.03 SCCM, Silane (SiH ₄ ) 1500Å was deposited at a deposition temperature of 600 ° C using 200 SCCM as a source gas. The deposition rate at this time was 30 Å / min, and the sheet resistance value immediately after film formation was 1951 Ω / □. Next, a resist is formed on the silicon thin film 803, and carbon tetrafluoride (CF ₄ ), Oxygen (O ₂ ), Nitrogen (N ₂ The source / drain region 804 was formed by patterning with a mixed plasma such as). Subsequently, after removing dirt and a natural oxide film on the surface of the region 804, an amorphous silicon thin film 805 was immediately deposited by a low pressure CVD method. (FIG. 8B) The reduced pressure CVD apparatus in Example 1 is 184.5 l, and the reaction chamber is made of quartz glass. A heater divided into three zones is installed outside the reaction chamber, and an isothermal region is formed at a desired temperature near the center of the reaction chamber by independently adjusting the three heaters. The substrate was placed horizontally in this isothermal region, and an amorphous silicon thin film 805 was deposited. The amorphous silicon thin film 805 is disilane (Si ₂ H ₆ ) 100 SCCM was used, and helium (He) 100 SCCM was used as a dilution gas. The deposition temperature was 450 ° C. The vacuum CVD furnace used for depositing the amorphous silicon thin film 805 of Example 1 is exhausted by directly connecting a mechanical booster pump and a rotary pump. A conductance valve is attached between the mechanical booster pump and the reactor. By adjusting the opening / closing amount of this valve, the pressure in the reaction chamber can be adjusted and maintained at a desired value. In Example 1, the pressure in the reaction chamber was maintained at 306 mtorr during the deposition of the amorphous silicon thin film 805. The deposition rate was 18.07 Å / min, and an amorphous silicon thin film 805 was deposited to a thickness of 307 Å. Next, a resist is formed on the amorphous silicon thin film 805 formed in this way, and patterning is performed with a mixed plasma of carbon tetrafluoride, oxygen, nitrogen, or the like. 806 was left.
[0043]
Next, this substrate is cleaned with boiling nitric acid having a concentration of 60%, and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds, so that the source / drain region 804 and the channel portion are left. After the natural oxide film on the amorphous silicon thin film 806 was removed and a clean silicon film appeared, oxygen plasma 807 was immediately irradiated with an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). (FIG. 8C) The outline of the ECR-PECVD apparatus used in Example 1 is shown in FIG. As the oxygen plasma, a 2.45 GHz microwave was guided to the reaction chamber 202 through the waveguide 201, and oxygen of 100 SCCM was introduced from the gas introduction tube 203 to establish an oxygen plasma. At this time, the pressure in the reaction chamber was 1.84 mtorr and the microwave output was 2500 W. An external coil 204 is provided outside the reaction chamber, and an 875 Gauss magnetic field is applied to the oxygen plasma to satisfy the ECR condition for electrons in the plasma. The substrate 205 is placed perpendicular to the plasma, and the substrate temperature is kept at 300 ° C. by the heater 206. Under this condition, the oxygen plasma 807 is irradiated for 8 minutes and 20 seconds to oxidize the amorphous silicon thin film 806 remaining at the position to become the channel portion, and to form SiO which becomes one part of the gate insulating layer. ₂ A membrane 808 was obtained. At this time, SiO which becomes one part of the gate insulating layer ₂ An amorphous silicon thin film 809 that will eventually become a channel portion remains below the film 808. (FIG. 8D) Further, SiO which becomes a gate insulating layer continuously without breaking the vacuum ₂ A film 810 was deposited. This SiO ₂ The film 810 was deposited at a microwave power of 2250 W, a silane flow rate of 60 SCCM, an oxygen flow rate of 100 SCCM, and a substrate temperature of 300 ° C. for 18.75 seconds. The reaction chamber pressure during the deposition was 2.62 mtorr. The multilayer film thus formed is subjected to multi-wavelength dispersion ellipsometry (multi-wavelength spectroscopic ellipsometry: MOSS-ES4G manufactured by Sopra Co., Ltd.), and the film thickness of the amorphous silicon film 809 remaining as a channel portion is determined.・ SiO formed by oxidizing silicon film ₂ The film thickness of the film 808 and SiO deposited by the ECR-PECVD method ₂ When the film thickness of the film 810 was measured, the amorphous silicon thin film 809 was 205 mm, SiO 2 ₂ Film 808 is 120 mm, SiO ₂ The membrane 810 was 1500 mm. At this time, SiO at a wavelength of 632.8 nm is used. ₂ The refractive index of the film is SiO ₂ Film 808 is 1.42, SiO ₂ The membrane 810 was 1.40.
[0044]
Next, the substrate thus obtained was inserted into an electric furnace maintained at 600 ° C. and subjected to a heat treatment for 48 hours. At this time, nitrogen gas having a purity of 99.999% or more was continuously supplied to the electric furnace at a rate of 20 l / min to keep the inert atmosphere. By the heat treatment at 600 ° C. in the inert atmosphere, the amorphous silicon thin film remaining in the channel portion is crystallized and changed into a silicon thin film 811 constituting the channel portion. (FIG. 8 (e)) Subsequently, this substrate was again put into an ECR-PECVD apparatus, and hydrogen plasma was irradiated to the substrate subjected to heat treatment using the apparatus. At this time, hydrogen plasma was generated by flowing hydrogen at 100 SCCM at a substrate temperature of 300 ° C. and a microwave output of 2000 W. In this state, the pressure in the reaction chamber was 1.97 mtorr. Hydrogen plasma irradiation was performed for 45 minutes.
[0045]
Next, 1500 Å of chromium was deposited by a sputtering method, and a gate electrode 812 was formed by patterning. At this time, the sheet resistance value was 1.36Ω / □. Thereafter, a contact hole is opened in the gate insulating film, a source / drain extraction electrode 813 is formed by sputtering or the like, and patterning is performed to complete the transistor. (FIG. 8F) In Example 1, aluminum having a film thickness of 8000 mm was used as the source / drain extraction electrode material. The sheet resistance value of aluminum at this time was 42 mΩ / □.
[0046]
An example Vgs-Ids curve of the characteristics of the thin film transistor (TFT) manufactured in this way is shown in 9-a of FIG. Here, Ids was measured at a source / drain voltage, Vds = 4 V, and a temperature of 25 ° C. The transistor size was a channel portion length L = 10 μm and a width W = 100 μm. When the transistor was turned on with Vds = 4V and Vgs = 10V, the on-current was Ids = 34.5 μA, and a thin film semiconductor device having good transistor characteristics was obtained. The field effect mobility obtained from the saturation current region of this transistor is 12.52 cm. ² / V · sec. 9B shows the transistor characteristics of a thin film semiconductor device prepared according to the prior art for comparison. That is, in the prior art, a thin film semiconductor device is formed by the same process as in the first embodiment except that the channel portion silicon thin film is deposited at 600 ° C. by the low pressure CVD method and the oxygen plasma irradiation is not performed. . At this time, the apparatus for depositing the channel portion silicon thin film by the low pressure CVD method is the same as the apparatus for depositing the amorphous silicon thin film in the first embodiment. The deposition rate was 19.00 cm / min and a film thickness of 252 mm was deposited. The on-current of this conventional TFT was Ids = 4.6 μA, and the field effect mobility was 4.40 cm / v · sec. In addition, after the channel portion silicon thin film is similarly deposited at 600 ° C. by the low pressure CVD method, oxygen plasma irradiation is performed before the gate insulating film is deposited, and all other steps are the same as those in the first embodiment. The thin film semiconductor device was prepared and the TFT characteristics were measured. The TFT characteristics hardly changed with or without oxygen plasma irradiation, and the Vgs-Ids curve of the TFT subjected to oxygen plasma irradiation coincided with 9-b in FIG. did. At this time, the on-current of the TFT is Ids = 4.7 μA, and the field-effect mobility is 4.44 cm. ² / V · sec. That is, in the conventional technique in which the channel portion silicon thin film is deposited by the low pressure CVD method at 600 ° C., the effect of the oxygen plasma irradiation is very small. 9C of FIG. 9 illustrates TFT characteristics of a thin film semiconductor device prepared by another conventional technique. In this prior art, except that the oxygen plasma irradiation is not performed in the first embodiment, the thin film semiconductor device is formed by the same process as the present embodiment. That is, this is a process in which an amorphous silicon thin film is first deposited as a channel part silicon layer, and then heat treatment at 600 ° C. is performed, but oxygen plasma irradiation is not performed before forming the gate insulating layer. In accordance with this conventional technique, the produced TFT exhibits a depletion of −10 V and the rise characteristic is not good. This thin film semiconductor device has an on-current of 12.1 μA at Vds = 4 V and Vgs = 10 V, and a field effect mobility of 9.94 cm. ² / V · sec.
[0047]
From these results, as shown in Example 1, the amorphous silicon thin film that will eventually become the channel portion is irradiated with oxygen plasma, and after that, heat treatment is performed to advance the crystallization of the channel portion silicon thin film. It can be seen that the transistor characteristics are greatly improved. This is because the surface of the amorphous silicon thin film is first oxidized by oxygen plasma, so that a clean MIS interface is formed, and then crystallization proceeds. Thus, it can be seen that the embodiment of the present invention has remarkably good semiconductor characteristics as compared with the thin film semiconductor device produced by the prior art.
[0048]
(Reference Example 5)
After forming a silicon film and a silicon oxide film over the insulating material, an impurity serving as a donor or an acceptor was added to the silicon film, and a conductive layer made of the silicon film was formed.
[0049]
In Reference Example 5, a fused quartz substrate having a diameter of 75 mm was used as the substrate. However, of course, any substrate can be used as long as it can withstand heat treatment at about 600 ° C. For example, a processed silicon substrate is also possible. First, the base SiO on the upper surface of the organic cleaned and acid cleaned substrate ₂ The film was deposited by the APCVD method. Base SiO ₂ The film was deposited at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM, and nitrogen of about 140 SLM. The deposition rate at this time was 3.9 kg / sec, and the deposition time was 12 minutes 49 seconds. Next, a silicon film was deposited by the same method as in Reference Example 1 using the LPCVD apparatus used to deposit the channel portion silicon film in Reference Example 1. That is, a silicon film was deposited for 11 minutes and 20 seconds at a deposition temperature of 550 ° C., a silane flow rate of 100 SCCM, and a reaction chamber pressure of 400 mtorr. The silicon film thus obtained had a thickness of 252 mm.
[0050]
Next, the substrate thus obtained was subjected to a heat treatment to improve the crystallinity of the silicon film. This heat treatment method is the same as the heat treatment performed in Reference Example 1 to improve the crystallinity of the silicon film 104. That is, heat treatment was performed at 600 ° C. for 23 hours in a nitrogen atmosphere. After completion of the heat treatment, this silicon film is patterned with a resist, and further CF ₄ And O ₂ Etching was performed by using the mixed plasma, thereby forming a wiring pattern of the silicon film.
[0051]
Subsequently, this substrate was washed with boiling nitric acid having a concentration of 60%, and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove a natural oxide film on the silicon film, and a clean silicon surface appeared. Immediately, a silicon oxide film was deposited to a thickness of 1500 に て with an ECR-PECVD apparatus. Here, the deposition of the silicon oxide film was performed by the same method as the method of forming the gate insulating film in Reference Example 1. Next, an impurity serving as a donor or an acceptor was added to the wiring made of the silicon film using an ion implantation apparatus. In the present Reference Example 5, phosphorus was selected as an impurity to aim at producing an n-type conductive layer. Of course, other elements are possible depending on the purpose. In Reference Example 5, impurity ions were added using a bucket type mass non-separation type ion implantation apparatus. As a source gas, phosphine having a concentration of 5% diluted in hydrogen is used, and 3 × 10 at an acceleration voltage of 110 KV. ¹⁵ 1 / cm ² Implanted through the silicon oxide film to a concentration of. Next, this substrate was inserted into a furnace maintained at 300 ° C. in a nitrogen atmosphere and subjected to heat treatment. The heat treatment time was just one hour. After the heat treatment for one hour at 300 ° C., a contact hole was formed in the silicon oxide film, and an electrode was formed by taking out with aluminum. When the resistance of the impurity-doped silicon film wiring thus prepared was measured, the sheet resistance value was (71 ± 15) kΩ / □ with a 95% reliability coefficient. In general, it has been believed that it is impossible to obtain a conductive layer by adding impurity ions to a thin film having a thickness of only a few hundred mm and activating the added ions at a low temperature of about 300 ° C. However, in this reference example 5, the film quality of the heat-treated silicon film is covered with a silicon oxide film deposited on the silicon film by the ECR-PECVD method, thereby reducing the trap density of the silicon film surface. Since the silicon film quality was successfully improved, the electron scattering density was reduced, and it became possible for the first time to produce a thin film conductive layer. This is compared with the silicon film based on the prior art, and the superiority of Reference Example 5 is clarified.
[0052]
First of all, a silicon film is deposited by LPCVD at 600 ° C., and then an impurity is added to the silicon film of the prior art in which a silicon oxide film is formed by ECR-PECVD. Tried to create a layer. Here, the impurity-doped silicon film wiring was formed in exactly the same process as in Reference Example 5, except that the silicon film was flowed at 600 ° C., monosilane was flowed at 12.50 SCCM, and the reaction chamber pressure was 9.2 mtorr and deposited to a thickness of 263 mm. Created. The sheet resistance of the silicon film of the prior art thus obtained was 1 GΩ / □ or more when measured at five locations in the substrate, and virtually no current flowed.
[0053]
Secondly, the silicon film was prepared by performing a heat treatment at 600 ° C. exactly as in Reference Example 5, and then an impurity was added to the silicon film of the prior art in which a silicon oxide film was formed by the APCVD method, and the low temperature activation at 300 ° C. An attempt was made to create a silicon film conductive layer. Here, the substrate temperature of the silicon oxide film is kept at 300 ° C. by APCVD, nitrogen / silane mixed gas containing 20% silane in nitrogen is flowed at 300 SCCM, oxygen is flowed at 420 SCCM, and about 140 SLM of nitrogen for dilution is used as the source gas. And deposited with a film thickness of 1500 mm. Except for this, an impurity-added silicon film wiring was formed in exactly the same steps as in Reference Example 5. The sheet resistance value of the conventional silicon film thus obtained was (175 ± 56) kΩ / □ with a 95% reliability coefficient. Thereafter, the substrate was mounted again on the ECR-PECVD apparatus and subjected to hydrogen plasma treatment. The hydrogen plasma treatment was performed at a substrate temperature of 300 ° C. with a flow of 125 SCCM of hydrogen and a microwave output of 2000 W for 30 minutes. After the hydrogen plasma treatment, the resistance values at 5 locations in the substrate were measured. The sheet resistance at 2 locations was 1 GΩ / □ or more, the average value at the remaining 3 locations was 158 kΩ / □, and the standard deviation value was 68 kΩ / □. It was in.
[0054]
It can be seen that a high-quality silicon film can be obtained by coating the silicon film heat-treated at 600 ° C. or lower with a silicon oxide film formed by an ECR-PECVD apparatus. Therefore, as shown in Reference Example 1, a thin film semiconductor device having good characteristics can be obtained by using a silicon film for the channel portion of the thin film semiconductor device and a silicon oxide film formed by an ECR-PECVD apparatus for the gate insulating layer. Also, as shown in the present reference example 5, when impurity ions are added to the silicon film, a low resistance silicon film conductive layer can be obtained at a low temperature. Therefore, the silicon film of Reference Example 5 is not only effective for a thin film semiconductor device, but also very effectively used for a non-single crystal silicon film used for any electronic device such as a gate electrode or wiring of a charge coupled device (CCD). Can do.
[0055]
(Reference Example 6)
In the reference example 5, the step of adding impurity ions to the silicon film using the bucket type mass non-separation type ion implantation apparatus is changed to the mass separation type ion implantation apparatus, and monovalent ions of phosphorus having a mass number of 31 are implanted. Except for the change, all attempts were made in the same process as in Reference Example 5 to produce an impurity-added silicon film conductive layer. In Reference Example 6, the phosphorus ion is 3 × 10 at 90 KV. ¹⁵ 1 / cm ² Typed in. When the resistance of the impurity-added silicon film obtained in this manner was measured, no current flowed at all at 1 GΩ / □ at 5 locations in the substrate. This is because, in Reference Example 5, the impurity is added using a mass non-separation type ion implantation apparatus, and a hydrogen / phosphine mixed gas is used as the source gas. At the same time, defects generated during the ion addition are repaired by hydrogen ions, so that a low-resistance silicon conductive layer was produced only at a good quality silicon film at a low temperature.
[0056]
(Reference Example 7)
10A to 10D are cross-sectional views showing the manufacturing process of the silicon thin film semiconductor device constituting the MIS field effect transistor having the self-aligned staggered structure in the seventh embodiment. First, after cleaning the substrate 1001 as in Reference Example 1, SiO 2 is used as the base protective film 1002. ₂ A film is deposited about 2000 mm. Subsequently, a first silicon film is deposited by about 1500 mm and patterned to form a silicon film 1003 to be a pad (FIG. 10A). In this reference example 7, the first silicon film was deposited to 1500 liters at a deposition temperature of 600 ° C. and a silane flow rate of 12.5 SCCM using the LPCVD apparatus in which the channel part silicon film was deposited in reference example 1. It is also possible to deposit a silicon film at a deposition temperature of about 550 ° C. using an apparatus. ₂ H ₆ Can be deposited at a deposition temperature of about 450 ° C., or a silicon film can be deposited at about 250 ° C. by PECVD. Any method may be used as long as the film forming temperature does not exceed the maximum process temperature of 600 ° C. Next, a second silicon film 1004 is deposited. The film thickness of the second silicon film is about 300 mm or more, and the resistance value of the source / drain region after impurity implantation is that of the channel region when the transistor is operated. If it is sufficiently lower than the resistance value, the silicon film 1003 to be the first silicon film or pad is not required. In the present reference example 7, the second silicon film 1004 was deposited by the same method as the silicon thin film serving as the channel portion in the reference example 1. In other words, monosilane was used as a source gas by LPCVD, and the film was deposited to a thickness of 250 mm at a deposition temperature of 550 ° C. and a silane flow rate of 100 SCCM at a deposition rate of 21.2 kg / min. Thereafter, the same heat treatment as that performed in Reference Example 1 to improve the crystallinity of the silicon film was performed. That is, heat treatment was performed for 23 hours at 600 ° C. in a nitrogen atmosphere. (FIG. 10 (b)). Next, after patterning the second silicon film, a gate insulating layer 1005 was formed in the same manner as in Reference Example 1. That is, SiO by ECR-PECVD method ₂ 1500 liters of film was deposited. Next, a metal film to be a gate electrode is formed. In this reference example 7, a chromium film having a thickness of 2000 mm was used as the gate electrode material. The chromium film was formed by sputtering at a substrate temperature of 180 ° C. The sheet resistance value of chromium immediately after film formation was 994 mΩ / □. Subsequently, SiO2 is deposited on the chromium at a substrate temperature of 300 ° C. by the APCVD method. ₂ A film of 3000 Å was deposited. Then, patterning is performed with a resist, and the gate electrode 1006 and SiO ₂ A protective cap layer 1007 depending on the film was formed, and impurity ions were added. In this reference example 7, phosphorus was selected as an impurity and an attempt was made to produce an n-type thin film semiconductor device. However, other elements are of course possible depending on the purpose. In this reference example 7, impurity ions were added using an ion implantation apparatus without a mass spectrometer. As a source gas, phosphine having a concentration of 5% diluted in hydrogen is used, and 5 × 10 5 at an acceleration voltage of 110 kV. ¹⁵ 1 / cm ² Typed into the concentration. In this way, a part of the first silicon film and the second silicon film becomes a source / drain region 1008, and SiO 2 ₂ Since there is a protective cap layer 1007 that depends on the film, the second silicon film located under this layer is not doped with ions, and constitutes a channel portion 1009 (FIG. 10C). Next, the substrate was heat-treated at 350 ° C. for 2 hours under a nitrogen atmosphere to activate the added impurity ions. After that, SiO ₂ A film 1010 is deposited in a thickness of 5000 mm, then contact holes are opened, wiring 1011 is formed with aluminum or the like, and a self-aligned thin film semiconductor device is completed (FIG. 10D).
[0057]
The transistor characteristics of the self-aligned thin film semiconductor device thus fabricated were measured. L = W = 10 μm, Vds = 4 V, Vgs = 10 V, the on-current was 4.89 μA, and the minimum value of the source / drain current was Vgs = −. The off-current defined by 0.21 pA at 3.5 V, Vgs = −10 V is 2.65 pA, and the field effect mobility μo = 26.1 cm. ² A very good self-aligned thin film semiconductor device of / v · sec was completed.
[0058]
For comparison, a self-aligned thin film semiconductor device was fabricated in exactly the same steps as in Reference Example 7 except that the channel portion silicon film was fabricated at 600 ° C. by the LPCVD method. However, as described in detail in Reference Example 5, in the conventional silicon film, the doped impurity element in the thin film portion is not activated, and the resistance of the doped silicon film in the thin film portion is too high. .9 pA and became impractical. On the other hand, in this reference example 7, the hydrogenated plasma treatment, which is the main cause of characteristic fluctuations, was eliminated, and a good self-aligned thin film semiconductor device was successfully produced in the low temperature process. As shown in Reference Example 2, even if the channel portion silicon film semiconductor layer is thinned to a thickness of 500 mm or less to improve basic semiconductor characteristics, the thin film conductive silicon film according to Reference Example 6 is still used. Depending on the fabrication, the source and drain regions of the thin film portion can be easily formed at low temperatures. In other words, the activation of impurities serving as donors or acceptors could not be achieved unless a silicon film having a thickness of about 1000 mm or more is subjected to heat treatment at about 550 ° C. or more. For this reason, in the self-aligned thin film semiconductor device, the film thickness of the channel portion inevitably becomes about 1000 mm or more, and the characteristics are poor. In addition, after the gate insulating layer and the gate electrode are completed, a heat treatment at about 550 ° C. or more is performed for the purpose of activating the added impurity ions, so that the film quality of the gate insulating film is deteriorated and the hydrogenation process is indispensable. There was. Further, since it was difficult to use a metal material as the gate electrode, the resistance of the gate line was high, or it was necessary to prepare the gate electrode and the gate line separately. However, according to the present Reference Example 7, a metal material can be used as a gate electrode, and at the same time, hydrogen treatment which is a main cause of variation can be eliminated, and a high-performance thin film semiconductor device can be stably manufactured by a simpler manufacturing method. succeeded in.
[0059]
【The invention's effect】
As described above, according to the present invention, in the method of manufacturing a thin film transistor, the step of forming an amorphous silicon thin film serving as a channel portion on the substrate, and the amorphous silicon thin film are irradiated with oxygen plasma. After forming the first insulating film, a gate insulating film is formed by depositing a second insulating film made of a silicon oxide film on the first insulating film continuously by plasma CVD without breaking the vacuum. A step of crystallizing the amorphous silicon thin film by heat-treating the substrate on which the gate insulating film is formed, and a hydrogen plasma treatment of the substrate on which the gate insulating film is formed after the heat-treating step And a step of forming a gate electrode on the gate insulating film that has been subjected to the hydrogen plasma treatment, and the above-mentioned process maximum temperature By at 600 ° C. or less, in order to perform hydrogen plasma treatment after being heat treated gate insulating film can be a silicon film to be the channel a dense film. Therefore, it is possible to form a thin film semiconductor device having excellent transistor characteristics over a large area by a simple and simple technique, and increase the performance and cost of an active matrix liquid crystal display using multilayered LSIs and thin film transistors. Has a great effect.
[Brief description of the drawings]
[0060]
FIG. 1 is an element cross-sectional view in each process of manufacturing a silicon thin film semiconductor device showing a reference example.
FIG. 2 is a diagram showing an outline of an electron cyclotron resonance plasma CVD apparatus used in Examples and Reference Examples of the present invention.
FIG. 3 is a diagram showing the effect of one reference example.
FIG. 4 is a diagram showing an effect of one reference example.
FIG. 5 is an element cross-sectional view of a silicon thin film semiconductor device showing one reference example.
FIG. 6 is a diagram showing the effect of one reference example.
FIG. 7 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing one reference example.
FIG. 8 is a cross-sectional view of an element in each process of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention.
FIG. 9 is a diagram showing the effect of the present invention.
FIG. 10 is a cross-sectional view of an element in each process of manufacturing a silicon thin film semiconductor device showing a reference example.
[Explanation of symbols]
[0061]
101 ... Underlying substrate
102: Base protective film
103: Source / drain region
104 ... Silicon thin film
105 ... channel part silicon thin film
106 ... Gate insulating film
107 ... Gate electrode
108: Interlayer insulating film
109 ... Source / drain extraction electrode
201: Waveguide
202 ... Reaction chamber
203 ... Gas introduction pipe
204 ... External coil
205 ... Board
206 ... Heater
207 ... Gas introduction pipe
501 ... Source / drain region
502 ... Gate electrode
503 ... Source / drain region
504 ... Gate electrode
505 ... Gate electrode
506 ... Mask material
507 ... Source / drain region
701 ... Board
702: Undercoat protective film
703 ... Silicon film to be a pad
704 ... Second silicon film
705 ... Gate insulating layer
706: Gate electrode
707 ... resist
708 ... Source / drain region
709 ... Channel part silicon film
710 ... Interlayer insulating film
711 ... Wiring
801 ... Insulating substrate
802: Base SiO ₂ film
803 ... Silicon thin film containing impurities
804 ... Source / drain region
805 ... amorphous silicon thin film
806: Amorphous silicon thin film left in the channel part
807 ... Oxygen plasma
808: SiO formed by oxidizing an amorphous silicon thin film ₂ Film 809 ... Amorphous amorphous silicon thin film that will eventually become a channel part
810: SiO deposited by ECR-PECVD method ₂ film
811 ... Silicon thin film constituting the channel portion
812 ... Gate electrode
813 ... Source / drain extraction electrode
1001 .. substrate
1002: Undercoat protective film
1003 ... Silicon film used as pad
1004 ... Second silicon film
1005 ... Gate insulating layer
1006 ... Gate electrode
1007 ... Protective cap layer
1008 ... Source / drain region
1009 ... Channel part silicon film
1010: Interlayer insulating film
1011 ... Wiring

Claims (1)

In the method of manufacturing a thin film transistor,
Forming an amorphous silicon thin film to be a channel portion on the substrate;
After forming the first insulating film by irradiating the amorphous silicon thin film with oxygen plasma, the second insulating film made of a silicon oxide film is formed on the first insulating film continuously by plasma CVD without breaking the vacuum. Forming a gate insulating film by depositing an insulating film;
Crystallizing the amorphous silicon thin film by heat-treating the substrate on which the gate insulating film is formed;
A hydrogen plasma treatment of the substrate on which the gate insulating film is formed after the heat treatment step;
Forming a gate electrode on the gate insulating film treated with the hydrogen plasma,
A method of manufacturing a thin film transistor, wherein the maximum temperature of the process is 600 ° C. or lower.

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