JP3731277B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a semiconductor integrated circuit device suitable for application to a semiconductor integrated circuit device, particularly, for example, a monolithic microwave integrated circuit (hereinafter referred to as MMIC) having at least a field effect transistor (hereinafter referred to as FET) and a capacitor as circuit elements. Involved.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an MMIC having an FET as an active element and a capacitor as a passive element as a circuit element, that is, a high frequency IC, an FET 3 is formed on a semi-insulating GaAs substrate 1 as shown in a schematic sectional view in FIG. Then, the capacitor 4 is formed.
The FET in FIG. 7 has a junction gate type structure. In this case, an n-type source or drain (hereinafter referred to as source / drain) region 5 is formed facing one main surface of the substrate 1. A channel formation region 6 having a low impurity concentration is formed on the substrate, and a p-type gate region 5g is formed thereon. On the gate region 5g, the gate electrode 7g is ohmic deposited through an electrode window opened in the surface insulating layer 8 formed on the surface of the substrate 1. On the source / drain region 5, source / drain electrodes 7 are deposited ohmicably through the respective electrode windows opened in the surface insulating layer 8.
[0003]
Then, a first interlayer insulating layer 9 is formed so as to cover these electrodes, and a first wiring contacted through a predetermined portion of the electrode, for example, a contact window opened on each of the gate electrode 7g and the source / drain electrodes 7, respectively. Layer 10 is formed. At the same time as the formation of the first wiring layer 10, that is, by the same conductive layer as the first wiring layer 10, the first capacitor electrode 11 is formed on the first interlayer insulating layer 9 in the capacitor forming portion. Is done.
[0004]
Further, a second interlayer insulating layer 12 is formed so as to cover the first wiring layer 10 and the first capacitor electrode 11, and, for example, one source / drain electrode 7 is connected through a contact window opened in a predetermined portion thereof. A contacted second wiring layer 13 is formed. At the same time as the formation of the second wiring layer 13, that is, by the same conductive layer as the second wiring layer 13, the second capacitor layer 11 facing the first capacitor electrode 11 through the second interlayer insulating layer 12. Capacitor electrode 14 is formed. In this way, the capacitor having the MIM (metal-insulating layer-metal) structure in which the first and second capacitor electrodes 11 and 14 and the second interlayer insulating layer interposed between these electrodes is the dielectric layer 15 is used. 4 is formed.
[0005]
The capacitor 4 formed by this configuration and method is a single-layer capacitor formed by the first and second capacitor electrodes 11 and 15. By the way, the area occupied by the capacitor in the semiconductor chip of the MMIC is quite large, and the area occupied by the capacitor is desired to be as small as possible when the MMIC is reduced. In other words, it is desirable to increase the capacitance per unit area of the capacitor as much as possible.
[0006]
Thus, the method of increasing the capacity per unit area of the capacitor is as follows:
(i) Reduce the thickness of the dielectric layer interposed between the capacitor electrodes.
(ii) The dielectric layer is made of a high dielectric constant material such as BST (BaSrTiO).
Can be considered. However, with the configuration (i), there arises a problem of withstand voltage between the electrodes. Further, in the case of the configuration (ii), since this dielectric is constituted by an interlayer insulating layer, there are a problem in function as an interlayer insulating layer and a problem in process.
[0007]
As a configuration for solving such a problem, there has been proposed a capacitor having a structure in which only the capacitor portion is shown in FIG. 8 (for example, Japanese Patent Laid-Open Nos. 60-28260 and 61-239661). JP, 63-108763, A). In this capacitor, a first capacitor electrode is formed by a semiconductor region 22 having a low specific resistance formed by introducing impurities at a high concentration facing one main surface of a semi-insulating semiconductor substrate 21, and the substrate surface is opposed thereto. A first wiring layer 24 made of a low-resistivity polycrystalline silicon layer is formed on the insulating layer 23 and / or the insulating layer 23 made of an interlayer insulating layer, thereby forming a second capacitor electrode 25. Then, an electrode lead-out portion 26 that contacts the semiconductor region 22 to be the first capacitor electrode through a contact window opened in the insulating layer 23 by the same first wiring layer 24 is formed. A part of the capacitor electrode is exposed to form an interlayer insulating layer 27, and a third capacitor formed by a metal layer is opposed to the second capacitor electrode 25 through the interlayer insulating layer 27. Contacts the electrode 28 to the electrode lead-out portion 26 formed. Then, an external lead-out terminal 29 that contacts the second capacitor electrode 25 at the same time is formed by this metal layer.
[0008]
The capacitor 4 having this configuration includes a first capacitance formed between the first capacitor electrode formed by the low specific resistance semiconductor region 22 and the second capacitor electrode 25 formed by the low specific resistance polycrystalline silicon layer, A second capacitance formed between the second and third capacitor electrodes 25 and 28 is laminated, and a large-capacity capacitor is configured in which these are connected in parallel.
[0009]
In the capacitor having this configuration, the first capacitance component has a so-called MIS (metal-insulating layer-semiconductor) structure, so that a carrier depletion layer is generated at the interface between the insulating layer 23 and the semiconductor substrate 21. When this fluctuates in accordance with the bias voltage, an unstable parasitic capacitance is present in the capacitor 4 and the capacitance value of the entire capacitor fluctuates.
[0010]
In the semiconductor region 22 constituting the capacitor 4 having the MIS structure, impurities are introduced at a high concentration by ion implantation, diffusion or the like to reduce the specific resistance. There is a limit to the resistance, and the specific resistance is much higher than that of metal, so that the high frequency characteristics are deteriorated.
[0011]
Due to the above-described problems, a capacitor having a MIS structure is not suitable for an IC that handles a high-frequency band such as MMIC, such as a quasi-microwave band of 1 to 3 GHz or higher.
[0012]
On the other hand, as shown in a schematic cross-sectional view in FIG. 9, in a MMIC using a so-called MES-FET whose gate portion is formed by a Schottky barrier 5s as the FET 3, formation of the source / drain electrode 7 by a metal layer At the same time, the first capacitor electrode 41 is formed on the semi-insulating substrate 1 in the formation part of the capacitor 4, the second capacitor electrode 14 is formed by the first wiring layer 10, and the second wiring layer 13 is further formed by the second wiring layer 13. There has been proposed a structure in which the third electrode 30 is formed (see, for example, JP-A-5-226582). 9, parts corresponding to those in FIG. 1 are denoted by the same reference numerals and redundant description is omitted. In the configuration of FIG. 9, a lead-out terminal 31 that is in ohmic contact with the first capacitor electrode 41 is formed. The third capacitor electrode 30 is in ohmic contact with this.
[0013]
Also in this configuration, a capacitance is formed between the first to third electrodes, and these are connected in parallel, so that a capacitor with a small occupation area and a large capacity can be configured. it can.
[0014]
However, a metal generally used as an ohmic electrode for the GaAs substrate 1, for example, the source / drain electrode 7, forms AuGe- (W) -Ni- (Au) (W and Au in parentheses can be omitted) sequentially. Therefore, the first electrode 41 of the capacitor in the structure of FIG. 9 is also based on the same metal layer. For this reason, this electrode material reacts with GaAs by heat treatment (alloy treatment) performed later, and the surface morphology is deteriorated. Since the electrostatic withstand voltage of the capacitor is greatly affected by the surface flatness, it is not desirable in terms of electrostatic withstand voltage and reliability to use the capacitor electrode 41 also as the ohmic electrode.
[0015]
[Problems to be solved by the invention]
In view of the above-described problems, the present invention provides a semiconductor integrated circuit device that has a high electrostatic withstand voltage, is highly reliable, can avoid an increase in the number of manufacturing steps, and can reduce costs. .
[0016]
Furthermore, according to the present invention, a large-capacity capacitor can be formed with a small occupied area, so that the semiconductor integrated circuit device can be reduced in size.
[0017]
[Means for Solving the Problems]
  A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which circuit elements including at least a field effect transistor and a capacitor are formed on a common semiconductor substrate.The capacitor is formed by laminating a first capacitor electrode, a first dielectric layer, and a second capacitor electrode formed on a surface insulating layer formed on the semiconductor substrate. A first capacitance configured, and a second capacitance configured by sequentially stacking a second dielectric layer and a third capacitor electrode on the second capacitor electrode. The first capacitor electrode is configured by a conductive layer made of the same material and formed in the same film formation process as the gate electrode of the field effect transistor, and the first dielectric layer is formed of the first dielectric layer. The second capacitor electrode is in contact with the electrode of the field effect transistor and extends on the first interlayer insulating layer. First wiring formed The second dielectric layer is composed of the same material dielectric layer formed in the same film formation process as the second interlayer insulating layer. The second capacitor electrode is constituted by a conductive layer made of the same material and formed in the same film forming process as the second wiring layer formed extending on the interlayer insulating layer. To do.
[0018]
According to the above-described configuration of the present invention, the lowermost electrode of the capacitor, that is, the first capacitor electrode is formed by the same conductive layer as the gate electrode without being formed by the ohmic electrode with respect to the semiconductor substrate. The problem of morphological degradation can be solved.
[0019]
Further, the gate electrode of the FET and the first capacitor electrode are formed of the same conductive layer, the first dielectric layer is formed on the first capacitor electrode by the first interlayer insulating layer, and the first wiring layer Since the capacitor and the second capacitor electrode are formed of the same conductive layer, each layer of the capacitor is formed of the same layer as each part of the integrated circuit using the FET. Therefore, a special process for forming this capacitor is taken. Therefore, when manufacturing this semiconductor integrated circuit device, the number of steps is not increased, and therefore the cost can be reduced in terms of mass production.
[0020]
Further, according to the configuration of the present invention, the first capacitor electrode in the lowermost layer of the capacitor can be formed by the same conductive layer, that is, the same process as the gate electrode of the FET, so that the capacitor electrode is formed directly on the semiconductor substrate. For example, it can be formed on the surface insulating layer or interlayer insulating layer formed on the surface of the semiconductor substrate, thereby avoiding the disadvantage that the surface property is deteriorated by the composition of the electrode material and the electrostatic withstand voltage is lowered. Therefore, a highly reliable capacitor can be formed as a semiconductor integrated circuit.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a semiconductor integrated circuit device according to the present invention will be described.
FIG. 1 is a schematic cross-sectional view of a main part of an example of a semiconductor integrated circuit having at least an FET 51 and a capacitor 52 according to the present invention.
[0022]
In this example, in a semiconductor integrated circuit device in which circuit elements including at least an n-channel FET 51 and a capacitor 52 are formed on a common semi-insulating GaAs semiconductor substrate 50, for example, the gate electrode 53 and the capacitor 52 of the FET 51 are formed. The first capacitor electrode 54 is formed by the same conductive layer 55, the first dielectric layer 57 is formed on the first capacitor electrode 54 by the first interlayer insulating layer 56, and the first wiring layer 58 is formed. And the second capacitor electrode 59 are formed of the same conductive layer 60.
The first and second capacitor electrodes 54 and 59 are formed so as to face each other with the first dielectric layer 57 interposed therebetween, thereby forming a first capacitance therebetween.
[0023]
Further, the second dielectric layer 62 is formed by the second interlayer insulating layer 61 on the second capacitor electrode 59, and the second wiring layer 63 and the third capacitor electrode 64 are formed by the same conductive layer 65. To do.
The second and third capacitor electrodes 59 and 64 are formed so as to face each other with the second dielectric layer 62 interposed therebetween, thereby forming a second capacitance therebetween.
[0024]
And it is set as the structure which connected the 1st and 2nd electrostatic capacitance by the above-mentioned structure in parallel.
[0025]
Next, in order to further facilitate the understanding of the semiconductor integrated circuit having this configuration, it will be described in detail together with an example of its manufacturing method with reference to each step diagram of FIGS.
First, as shown in FIG. 1A, a semiconductor substrate 50 made of non-doped or semi-insulating GaAs is prepared, and a region 65 to be a source region or drain (source / drain) region of the FET 51 finally obtained is formed on one main surface thereof. N-type impurities such as Si⁺N-type regions of high impurity concentration are selectively formed by ion implantation of, for example, a similar Si layer between these regions 65⁺An n-type channel formation region 67 having a low impurity concentration is formed by ion implantation.
[0026]
As shown in FIG. 2B, on the main surface of the semiconductor substrate 50, for example, Si_ThreeN_FourA surface insulating layer 68 is formed by deposition, and an opening 68W is formed in part on the channel formation region 67. A p-type impurity such as Zn is introduced by diffusion, for example, through the opening 68W to form a gate region 69. Form. It is formed while maintaining a required interval by ion implantation, diffusion or the like.
[0027]
As shown in FIG. 2C, the gate electrode 53 is formed ohmically on the gate region 69 through the opening 68W, and at the same time, the first capacitor electrode 54 is formed in the capacitor forming portion. For example, the gate electrode 53 and the first capacitor electrode 54 are formed by sequentially sputtering, for example, Ti, Pt, and Au metal layers sequentially from the lower layer, or sequentially sputtering Ti, Au metal layers, for example. The conductive layer 55 is formed and formed into the required pattern by the same conductive layer 55 simultaneously, that is, in the same process, by pattern etching by photolithography.
[0028]
As shown in FIG._ThreeN_FourA first interlayer insulating layer 56 such as is formed.
Next, an electrode window is formed on the source / drain region 66 through the first interlayer insulating layer 56 and the surface insulating layer 68 below the first interlayer insulating layer 56, and the source / drain electrode is formed through these electrode windows. I do. Therefore, for example, as shown in FIG. 3E, first, a photoresist layer 70 is formed on the first interlayer insulating layer 56 by spin coating, and pattern exposure and development are performed on the photoresist layer 70 on each source / drain region 66. An opening 70W is drilled in.
[0029]
As shown in FIG. 4F, the photoresist layer 70 is used as an etching mask, and Si is passed through the opening 70W._ThreeN_FourThe first interlayer insulating layer 56 and the surface insulating layer 68 are subjected to anisotropic etching by, for example, RIE (reactive ion etching) to form an opening 71W corresponding to the opening 70W.
[0030]
Further, using the photoresist layer 70 as an etching mask, side etching by isotropic etching by, for example, chemical etching is performed on the first interlayer insulating layer 56 and the surface insulating layer 68 through the opening 70W as shown in FIG. 4G. Then, the side surface of the opening 71W is etched to form the opening 71W wider than the opening 70W, and the eaves 70A protruding from the inner edge of the opening 71 is formed on the opening 71W.
[0031]
In this state, as shown in FIG. 5H, with the photoresist layer 70 as a mask, an electrode material layer 72, for example, an AuGe and Ni layer, for the source / drain region 66 is deposited from above by sputtering or the like. In this way, the electrode material layer 72 forms the source / drain electrode 73 that is in ohmic contact with the source / drain region 66 through the opening 70W. At this time, since the eaves 70A are formed under the opening 70W of the photoresist layer 70, these electrodes 73 and the electrode material layer 72 deposited on the photoresist layer 70 are formed separately. Can do.
[0032]
As shown in FIG. 5I, the photoresist layer 70 is removed. As a result, the electrode 73 on the source / drain region 66 and the electrode material 72 deposited on the photoresist layer 70 are formed separately as described above, leaving only the electrode 73. The electrode material 72 on the photoresist layer 70 is removed, that is, lifted off together with the photoresist layer 70.
In this way, after the electrode 73 is formed, the entire surface is Si._ThreeN_FourA first interlayer insulating layer 56 is deposited and formed, and this is subjected to pattern etching by photolithography, so that one end of the first capacitor electrode 54, for example, the source / drain electrode 73, and the gate electrode 53 are formed. Contact windows are drilled on the top and the bottom. After that, ohmic contact is made on the first capacitor electrode 54, the source / drain electrode 73, and the gate electrode 53 exposed to the outside through these contact windows, respectively, for example, Ti, Pt and Au. A conductive layer 60 is formed by sequentially sputtering each metal layer, for example, or by sequentially sputtering each metal layer of Ti and Au.
[0033]
As shown in FIG. 6J, pattern etching using photolithography is performed on the conductive layer 60 to form a contact conductive layer 74 at one end portion of the first capacitor electrode 54 by the conductive layer 60, and at the same time, A second capacitor electrode 59 is formed at a position facing most of the capacitor electrode 54, and at the same time, a desired pattern is formed on the source / drain electrode 73 and the gate electrode 53 by the same conductive layer 60. A first wiring layer 58 is formed. Thus, the first capacitance in which a part of the first interlayer insulating layer 56 interposed between the first capacitor electrode 54 and the second capacitor electrode 59 is the first dielectric layer 57 is used. C₁Is formed.
Then, for example, Si_ThreeN_FourA second interlayer insulating layer 61 is formed by deposition.
[0034]
As shown in FIG. 6K, pattern etching using photolithography is performed on the second interlayer insulating layer 61 so that, for example, one source / drain to be contacted with the contact conductive layer 74 and the second wiring layer. A contact window is formed on the electrode 73, and a photoresist layer 75 is formed on the entire surface including the contact window, and pattern exposure and development are performed on the photoresist layer 75 to form the second interlayer insulating layer 61. Openings 75W are formed on the contact window and on the upper portion of the second capacitor electrode 59, respectively. After that, the conductive layer 65 is formed on the entire surface by sequentially sputtering, for example, Ti, Pt and Au or Ti and Au metal layers.
[0035]
Thereafter, pattern etching using photolithography is performed on the conductive layer 65, and the second wiring layer 63 is formed on the first wiring layer 58 on one source / drain electrode 73, for example, as shown in FIG. In addition, the third capacitor electrode 64 is formed in contact with the contact conductive layer 74 so as to face the second capacitor electrode 59, that is, electrically connected to the second capacitor electrode 59. In this way, the second capacitance C is formed by interposing the second dielectric layer 62 made of the second interlayer insulating layer 61 between the second capacitor electrode 59 and the third capacitor electrode 64.₂ Is formed.
The first capacitance C described above₁And the second capacitance C₂ Are connected in parallel to form a capacitor 52 having a large capacity.
[0036]
Thereafter, the photoresist layer 75 is removed. In this case, since the photoresist layer 75 is present, the third capacitor electrode 64 can be formed inside the edges of the first and second capacitor electrodes 54 and 59. It is possible to prevent the capacitor 52 from being formed in the unstable portion where the breakdown voltage tends to decrease.
[0037]
In this way, the semiconductor integrated circuit device according to the present invention shown in FIG. 1 can be configured. According to the semiconductor integrated circuit device having this configuration, the first, second, and third capacitor electrodes 54, 59, and 64 are stacked at substantially the same position, that is, without causing an increase in the occupied area. 1 and 2nd 2nd electrostatic capacitance C₁And C₂ Are connected in parallel to form a large-capacitance capacitor 52.
[0038]
As described above, in the device of the present invention, all of the electrodes and the dielectric layers are integrated in the semiconductor integrated circuit despite the multilayer structure in which the first to third capacitor electrodes are laminated via the dielectric layers. In the manufacture of this semiconductor integrated circuit device, the gate electrode, the first and second wiring layers, and the first and second interlayer insulating layers that constitute the FET 51 constituting the circuit device are formed in the same layer. A capacitor having a large capacity and a small occupied area can be formed without requiring a process and without increasing the number of processes.
[0039]
Further, in the above-described configuration, when the 52 capacitor electrodes are formed by the electrode configuration of Ti, Pt, and Au or the conductive layer of Ti and Au, the surface resistance is excellent, that is, the electrostatic withstand voltage is high. An excellent capacitor can be configured.
[0040]
In the illustrated example, each of the FET 51 and the capacitor 52 is representatively shown. However, the present invention is not limited to the one FET 51 and the capacitor 52. Needless to say, the present invention can be applied to a semiconductor integrated circuit device or the like in which other circuit elements are formed together.
In the above-described example, the FET 51 is composed of an n-channel junction type FET. However, a p-channel type similar FET, a Schottky junction type conductivity channel FET, a so-called MES-FET, Needless to say, the present invention is not limited to the semiconductor integrated circuit described with reference to FIGS. 1 to 6, such as a field effect transistor such as HEMT (High Electron Mobility Transistor).
[0041]
【The invention's effect】
As described above, according to the semiconductor integrated circuit device of the present invention, the lowermost electrode of the capacitor, that is, the first capacitor electrode is not formed by the ohmic electrode with respect to the semiconductor substrate of the field effect transistor, and the gate electrode By using the same conductive layer, the above-described problem of deterioration in morphology can be solved, the electrostatic withstand voltage can be improved, and a highly reliable capacitor, that is, a semiconductor integrated circuit can be configured.
[0042]
In addition, the capacitor is formed with a first capacitor electrode by the same conductive layer as the gate electrode of the field effect transistor, and a first dielectric layer on the first capacitor electrode is formed by the first interlayer insulating layer. Further, since the second capacitor electrode is formed of the same conductive layer as the first wiring layer, the semiconductor integrated circuit device according to the present invention avoids an increase in the number of manufacturing steps in the manufacture. .
[0043]
Further, a second dielectric layer made of a second interlayer insulating layer is formed on the second capacitor electrode, and a third capacitor electrode is constituted by a conductive layer constituting the second wiring layer thereon. A first capacitance C between the first and second capacitor electrodes.₁And a second capacitance C between the second and third capacitor electrodes₂ Are formed using a laminated structure, and these capacitances C₁And C₂ By configuring in parallel with each other, a large-capacity capacitor can be configured with a small occupied area, and therefore, an MMIC with excellent characteristics can be configured with the entire size being reduced.
[0044]
And as mentioned above, in the manufacture, since the increase in the number of processes can be avoided, it is possible to avoid mass production, and hence an increase in cost.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of an example of a semiconductor integrated circuit device according to the present invention.
FIG. 2 is a process diagram (part 1) illustrating an example of a method of manufacturing an apparatus according to the present invention;
AC is sectional drawing in each process.
FIG. 3 is a process diagram (part 2) of an example of a method for producing the apparatus of the present invention;
D and E are sectional views in the respective steps.
FIG. 4 is a process diagram (part 3) of an example of a method for producing the apparatus of the present invention; F and G are cross-sectional views in the respective steps.
FIG. 5 is a process diagram (part 4) of an example of the method for producing the apparatus of the present invention;
H and I are cross-sectional views in the respective steps.
FIG. 6 is a process diagram (part 5) illustrating an example of a method of manufacturing an apparatus according to the present invention;
J and K are cross-sectional views in the respective steps.
FIG. 7 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device.
FIG. 8 is a cross-sectional view of another example of a conventional semiconductor integrated circuit device.
FIG. 9 is a cross-sectional view of another example of a conventional semiconductor integrated circuit device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 50 Semiconductor substrate, 51 Field effect transistor FET, 52 Capacitor, 53 Gate electrode, 54 1st capacitor electrode, 55 Conductive layer, 56 1st interlayer insulation layer, 57 1st dielectric material layer, 58 1st wiring layer 59 second capacitor electrode, 60 conductive layer, 61 second interlayer insulating layer, 62 second dielectric layer, 63 second wiring layer, 64 third capacitor electrode, 65 conductive layer, 66 source / drain Region, 67 channel formation region, 68 surface insulating layer, 69 gate region, 70 photoresist layer, 70W, 71W opening, 72 electrode material layer, 73 source / drain electrode, 74 contact conductive layer, 75 photoresist layer

Claims (1)

A semiconductor integrated circuit device in which a circuit element including at least a field effect transistor and a capacitor is formed on a common semiconductor substrate ,
The capacitor is formed by laminating a first capacitor electrode, a first dielectric layer, and a second capacitor electrode formed on a surface insulating layer formed on the semiconductor substrate. 1 is connected in parallel with a second capacitance formed by sequentially laminating a second dielectric layer and a third capacitor electrode on the second capacitor electrode. Consisting of
The first capacitor electrode is composed of a conductive layer of the same material formed in the same film forming step as the gate electrode of the field effect transistor;
The first dielectric layer is composed of a dielectric layer of the same material formed in the same film formation process as the first interlayer insulating layer,
The second capacitor electrode is in contact with the electrode of the field effect transistor and is made of the same material and formed in the same film formation step as the first wiring layer formed to extend on the first interlayer insulating layer Composed by
The second dielectric layer is composed of a dielectric layer of the same material formed in the same film formation step as the second interlayer insulating layer;
The second capacitor electrode is composed of a conductive layer of the same material formed in the same film formation process as the second wiring layer formed extending on the interlayer insulating layer. Integrated circuit device.

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