JP3735524B2 - Table conversion by difference data in SIMD type microprocessor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor, and more particularly to a SIMD (Single Instruction-stream Multiple Data-stream) type microprocessor.
[0002]
[Prior art]
In the SIMD type microprocessor, the same arithmetic processing can be executed simultaneously on a plurality of data with one instruction. This structure is frequently used in applications related to processing (for example, image processing) that has the same calculation but a very large amount of data.
[0003]
In normal arithmetic processing in a SIMD type microprocessor, a plurality of arithmetic units (Processor Elements [PE]; processor elements) are arranged and the same arithmetic is simultaneously performed on a plurality of data. However, in “non-linear processing” in which the contents of the arithmetic processing cannot be expressed by a single arithmetic expression, the arithmetic expression is changed according to the data to be calculated, and therefore the same processing cannot be executed simultaneously. In this case, it is necessary to perform sequential processing for each data, and eventually the effect of being SIMD is lost.
[0004]
Even in a normal SISD (Single Instruction-stream Single Data-stream) type processor, in non-linear processing in which an arithmetic expression is changed in accordance with operation target data, a program for performing arithmetic processing is very Can be complicated. In order to prevent this, there is a general method in which all processed data after calculation is preliminarily prepared for pre-calculation data, and these are converted into a table, and table conversion is performed based on the pre-calculation data to obtain post-calculation data. Specifically, the table is stored in a RAM (Random Access Memory), and data obtained from the RAM is obtained by using the value obtained by adding the head address of the table to the pre-computation data as post-computation data. For example, when the operation data (pre-operation data / post-operation data) is 8 bits, a conversion table having a size of 256 bytes is required.
[0005]
Since the size of this conversion table increases by a power of 2 (unit) as the bit width of the operation data increases, if the bit width of the operation data is considerably large, the operation data is divided into arbitrary sections, There is also disclosed a method having an approximate expression in a section as a table.
[0006]
When this table conversion is adopted in a SIMD type microprocessor, it has been considered that a table is required for each operation unit. For example, in a processor of 256 SIMD (that is, SIMD having 256 arithmetic units [arithmetic unit, PE]), when converting table of 8-bit arithmetic data (pre-operation data / post-operation data), 256 bytes ( The table (on the RAM) is required for the operation unit, that is, 256 pieces. Therefore, there was a big problem in cost. Therefore, various inventions have been devised and disclosed for non-linear operation table conversion of SIMD type microprocessors.
[0007]
In Japanese Patent Laid-Open No. 5-67203, data before calculation is sequentially output to the outside from an output register built in PE (Processor Element) in each SIMD unit, and the table conversion is sequentially performed outside, and the converted data is converted into the converted data. There has been proposed a method of sequentially inputting to an input register built in PE. In this method, since the number of conversion tables is one, an increase in cost can be suppressed. However, since it is a sequential process in the end, the calculation processing time is at least appropriate for the number of PEs, which is disadvantageous in terms of calculation speed. Also, if this conversion process is executed in parallel with the normal process in PE, the processing time can be reduced as a whole, but the input / output registers are dedicated to this conversion work and cannot be used for other purposes. However, there is still a problem that parallel processing is impossible because it is necessary to wait for the calculation processing time.
[0008]
Further, in Japanese Patent Laid-Open No. 9-305550, data before conversion and data after conversion are sequentially input from the outside, the data before conversion input at each PE is compared with the data before calculation, and the matched PE is converted into the data after conversion. A method for storing data and using this value as post-computation data has been proposed. In this case, since the computation processing time depends on the number of combinations of values that can be taken by the pre-computation data (that is, the number of words in the conversion table), if this number of words is less than the number of PEs, speeding up is realized. The However, when the pre-computation data is 8-bit data, the number of cycles is about 256 times regardless of the number of PEs. Even in this case, there is a problem that the computation processing time becomes long. A method of performing this conversion processing in parallel with other normal processing can also be assumed, but in this case, the same problem as in the above-mentioned Japanese Patent Laid-Open No. 5-67203 arises. A method of loading the coefficients of the approximate expression by using an expression that approximates the transformation in each section divided into a plurality of sections has also been proposed, but in this case, it is expressed by a common expression that is different only by the coefficient for each section. There is a problem that it can only deal with non-linear conversion that can be done.
[0009]
Furthermore, Japanese Patent No. 2812292 proposes a method for obtaining post-computation data by giving pre-computation data from each PE as an address pointer to a conversion table RAM having the same number of output ports as the number of PEs. Has been. In this method, the conversion speed is completed in about one cycle, but an increase in output ports increases the cost of the RAM, and in particular, it is impossible to have more than several tens of ports. Therefore, there is a problem that it cannot cope with a SIMD type microprocessor having a large number of PEs.
[0010]
[Problems to be solved by the invention]
An object of the present invention is to perform non-linear processing in a SIMD type microprocessor at higher speed using an inexpensive apparatus.
[0011]
[Means for Solving the Problems]
The present invention has been made to achieve the above object. The processing method of the SIMD type microprocessor according to claim 1 according to the present invention is as follows:
Has multiple arithmetic units In SIMD type microprocessor,
input Calculation Data before conversion and output Calculation One or more conversion tables for associating post-conversion data, which is data, are set, and each association defines a conversion process,
In the individual conversion table, it is assumed that the plurality of pre-conversion data is arranged in ascending order or descending order, and the plurality of pre-conversion data and the plurality of post-conversion data are divided into predetermined sections,
In the converted data of the above conversion table,
The actual value is stored in the converted data at the beginning of each section, and the difference data from the previous converted data is stored for the converted data other than the section head,
Conversion target Calculation When obtaining post-conversion data for data,
For the above multiple arithmetic units , The above conversion target data is stored,
By associating the pre-conversion data and post-conversion data in the conversion table, the post-conversion data section to which the post-conversion data of the conversion target data should belong is determined,
Furthermore, the necessary difference data is added to the converted data at the beginning of the section to which the converted data belongs,
Obtaining converted data for the conversion target data,
This is a processing method of a SIMD type microprocessor.
[0012]
The processing method of the SIMD type microprocessor according to claim 2 according to the present invention is as follows:
Has multiple arithmetic units In SIMD type microprocessor,
input Calculation Data before conversion and output Calculation One or more conversion tables for associating post-conversion data, which is data, are set, and each association defines a conversion process,
In each of the above conversion tables, it is assumed that a plurality of pre-conversion data is arranged in ascending or descending order, and the plurality of pre-conversion data and the plurality of post-conversion data are similarly divided into predetermined sections. And
In the converted data of the above conversion table,
For the converted data at the head of each section, the first difference value from the section head data of the previous section is stored, and for the converted data other than the head of the section, second difference data from the previous converted data is stored. Is stored,
Conversion target Calculation When obtaining post-conversion data for data,
For the above multiple arithmetic units , The above conversion target data is stored,
By associating the pre-conversion data and post-conversion data in the conversion table, the post-conversion data section to which the post-conversion data of the conversion target data should belong is determined,
First, the section head data of the section to which the converted data belongs is obtained by cumulative addition of the first difference values,
Furthermore, the second difference data is added as much as necessary to the section head data of the section to which the converted data belongs,
Obtaining converted data for the conversion target data,
This is a processing method of a SIMD type microprocessor.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0015]
FIG. 1 is a block diagram showing a schematic configuration of a SIMD type microprocessor 2 according to the present invention. The SIMD type microprocessor 2 generally includes a global processor 4, a register file 6, and an arithmetic array 8.
[0016]
(1) Global processor 4
The global processor 4 itself is a so-called SISD type processor, which includes a program RAM 10 and a data RAM 12 (see FIG. 2), decodes the program, and generates various control signals. This control signal is supplied to the register file 6 and the arithmetic array 8 in addition to the various built-in blocks. When a GP (global processor) instruction is executed, various arithmetic processes and program control processes are performed using a built-in general-purpose register, an ALU (arithmetic logic unit), and the like.
[0017]
(2) Register file 6
It holds data processed by PE (processor element) instructions. As is well known, the PE (processor element) 3 is a structural unit that executes individual operations in a single instruction-stream (SIMD) type processor. As shown in the register file 6 and the operation array 8 in FIG. 2, the SIMD type microprocessor 2 in FIG. 2 includes 256 PE3. The PE instruction is a SIMD type instruction, and simultaneously performs the same processing on a plurality of data held in the register file 6. Control of reading / writing of data from the register file 6 is performed by control from the global processor 4. The read data is sent to the arithmetic array 8 and written into the register file 6 after arithmetic processing in the arithmetic array 8.
[0018]
Further, the register file 6 can be accessed from the outside of the processor 2, and reading / writing to a specific register is performed from the outside separately from the control of the global processor 4.
[0019]
(3) Arithmetic array
Processing of PE instruction is performed. All processes are controlled from the global processor 4.
[0020]
FIG. 2 is a block diagram showing a more detailed configuration of the SIMD type microprocessor 2 according to the present invention.
[0021]
The global processor 4 includes a program RAM 10 for storing the program of the processor 2 and a data RAM 12 for storing operation data. Furthermore, a program counter (PC) 14 that holds a program address, G0, G1, G2, and G3 registers (16, 18, 20, and 22), which are general-purpose registers for storing data for arithmetic processing, A stack pointer (SP) 24 that holds the address of the save destination data RAM, a link register (LS) 26 that holds the address of the call source at the time of a subroutine call, and an NMI (Non-Non−) when IRQ (Interrupt Request) A LI register 28 and an LN register 30 that hold a branch source address at the time of Maskable Interrupt ReQuest (prohibited interrupt request), and a processor status register (P) 32 that holds the state of the processor are incorporated.
[0022]
A GP instruction is executed using these registers, an instruction decoder (not shown), an ALU, a memory control circuit, an interrupt control circuit, an external I / O control circuit, and a GP operation control circuit.
[0023]
When executing the PE instruction, the instruction decoder, the register file control circuit 56 (shown in FIG. 6), and the PE operation control circuit 58 are used to control the register file 6 and the operation array 8. Furthermore, it is set so that data can be transferred from the data RAM 12 to a plurality of PE register files 6.
[0024]
In the register file 6, 32 8-bit registers 34 are built in one PE unit, and a set of 256 PEs (32) has an array configuration. Register 34 is R0, R1, R2,. . . It is called R31. Each register 34 has one read port and one write port for the arithmetic array 8 and is accessed from the arithmetic array 8 by an 8-bit read / write bus. Of the 32 registers, 24 (R0 to R23) can be accessed from the outside of the processor, and the clock (CLK), address (Address), and read / write control (RWB) can be input from the outside. Can be read from and written to the register 34. The remaining eight (R24 to R31) registers 34 are used for temporarily storing PE operation data.
[0025]
The arithmetic array 8 includes a 16-bit ALU 36, a 16-bit A register 38, and an F register 40. The operation by the PE instruction is performed by using the data read from the register file 6 or the data supplied from the global processor 4 as an input on one side of the ALU 36 and the content of the A register 38 as an input on the other side. The calculation result is stored in the A register 38. Therefore, an operation is performed on the data supplied from the R0 to R31 register 34 or the global processor 4 and the data stored in the A register 38.
[0026]
A 7 to 1 (7 to 1) multiplexer 42 is placed between the register file 6 and the operation array 8. As shown in FIG. 2, when viewed from a certain multiplexer 42, the data in the R0 to R31 register 34 included in the three PE3 in the left direction, the data in the R0 to R31 register 34 included in the three PE3 in the right direction, It is set so that the data in the R0 to R31 register 34 included in the PE 3 to which it belongs can be selected as an operation target. The 8-bit data of the register file 6 is shifted to the left by an arbitrary bit by the shift / extension circuit 44 and input to the ALU 36. Further, the execution / invalidation control of each PE 3 is controlled by the 8-bit condition register 54 (shown in FIG. 6), and only a specific PE 3 can be selected as an operation target.
[0027]
<< First Embodiment >>
FIG. 3 is a flowchart of the difference data utilization table conversion procedure in the SIMD type microprocessor according to the first embodiment of the present invention. The procedure in FIG. 3 is realized by program code that operates the SIMD type microprocessor 2 in FIGS. 2 and 6. The flowchart will be described below.
[0028]
Step S00: First, a post-conversion table 50 as shown in FIG. 4 is prepared. In the present invention, it is assumed that the entire pre-conversion data / post-conversion data is divided into predetermined sections. Therefore, the post-conversion table 50 is also divided into the same (predetermined) sections. The number of divisions is
(1) Converted data / converted data bit width,
(2) Number of bits required for the difference value of the converted data,
(3) Register bit width that can be temporarily loaded into each PE3
Determined by For example, (1) the bit width of the pre-conversion data and the post-conversion data is 8 bits, (2) the difference value is 2 bits at the maximum, and (3) the bit width that can be temporarily loaded into each PE 3 is 16 bits. As shown in FIG. 4, the data after the section head conversion is 8 bits, and the subsequent difference value is 2 bits each and 3 combinations (the 4th invalid 2-bit data is inserted. As a result, data is aligned on an 8-bit boundary, and processing relating to the table is simplified.) Four converted data are included in one section. Therefore, since the table conversion of 8-bit data is performed, 256 tables are divided. However, since four pieces of data for 256 are set as one section, there are 64 sections in total.
[0029]
Step S02: Under the condition that the post-conversion table 50 is prepared, the processing of the flowchart of FIG. 3 is actually started. First, the number of designated sections is set to “0”.
[0030]
Step S04: The data (0) before conversion (corresponding to) at the head of the section 0 is compared with the conversion target data held in each PE 3 (step S06).
[0031]
Step S08: In PE3 where the conversion target data held in PE3 is larger, convert 8 bits of converted data at the head of section 0 and three 2-bit difference values (including one 2-bit invalid data). After reading from the table 50, it is loaded into a temporary register.
[0032]
Steps S10, S12 and S04; Next, the section is counted up by “1”. The equivalent data before conversion (4) at the head of section 1 is compared with the conversion target data held in each PE 3 (step S06).
[0033]
Step S08: In PE3 where the conversion target data held in PE3 is larger, the 8-bit converted data at the head of section 1 and three 2-bit difference values (including one 2-bit invalid data) are converted. After reading from the table 50, it is loaded into a temporary register.
[0034]
Step S12: Counting up the section is repeated up to the section 63, and when the section specified value n reaches 64, the process proceeds to the next process.
[0035]
The section head data is a multiple of 0, 4, 8, 12, 16, 20, and 4 because a set of four data is one section.
[0036]
Step S14: In the latter half of the flowchart of FIG. 3, it is determined which position in the section (before conversion) the conversion target data corresponds to. In this embodiment, since one section includes four data, the lower 2 bits of the conversion target data indicate the position (m) in the section.
[0037]
Step S16: The value of this position (m) is compared with 0. If it is 0, the process proceeds to “END” (S22).
[0038]
Step S18: In the comparison of Step S16, in “m is not 0” PE3, the difference value between the first converted data and the next converted data in the section is added to the first converted data, and the accumulated value is obtained. To do. The difference value to be added here is the lower 2 bits of the loaded difference value data.
[0039]
Step S20: Thereafter, 1 is subtracted from m, and the process returns to Step S16.
[0040]
Step S16: Next, the value of the position (m) is compared with 0. If it is 0, the process proceeds to “END” (S22).
[0041]
Step S18: In step S16, in “m is not 0” PE3, the difference value between the first converted data at the head and the second converted data in the section is added to the accumulated value. Since the difference value to be added here is bits 2 to 3 of the loaded difference value data, the difference value data is shifted to the right by 2 bits before the addition to become the lower 2 bits.
[0042]
Step S20: Thereafter, 1 is subtracted from m, and the process returns to Step S16.
[0043]
Step S16: Next, the value of the position (m) is compared with 0. If it is 0, the process proceeds to “END” (S22).
[0044]
Step S18; In step S16, in “PE is not m” PE3, the difference value between the first second-order converted data and the third-order converted data in the section is added to the accumulated value. Since the difference value to be added here is bits 4 to 5 of the loaded difference value data, the difference value data is shifted to the right by 2 bits before addition (a 4-bit shift is necessary, but 2 bits are the previous processing) To the lower 2 bits.
[0045]
Step S20: Thereafter, 1 is subtracted from m, and the process returns to Step S16.
[0046]
Step S16: Next, the value of the position (m) is compared with 0. In the present embodiment, m is 3 at the maximum, so the process is always terminated by the repetition up to this point. The accumulated value obtained by this process becomes the converted data.
[0047]
Above, description of the flowchart of FIG. 3 is complete | finished.
[0048]
Of course, the present invention is not limited to the above-described embodiment. That is, the number of divisions and the difference value may be realized with other predetermined values.
[0049]
In addition, there are many methods for determining a section in the first half of the processing of the flowchart of FIG. 3 other than the size comparison between the pre-conversion equivalent data at the head of the section and the pre-conversion data held in each PE. For example,
A method in which the lower bits (2 bits in the example) indicating the position in the section of the pre-conversion data are masked and compared with the pre-conversion equivalent data at the beginning of the section;
A method in which the pre-conversion data is right-shifted by the lower bits (2 bits in the example) indicating the position in the section and is compared with an integer from 0 to the number of sections;
・ Sequential comparison from the largest section to section 0 in smaller order
It can also be realized. In addition, when iterative processing by a loop is performed, it takes time to detect the end condition of the iteration. Therefore, it is faster to perform processing by arranging each section detection process in series without performing the iterative processing by a loop. come true.
[0050]
In the second half of the processing of the flowchart of FIG. 3, in the difference value addition, the intra-section position of the pre-conversion data is obtained from the lower two bits, but other methods are also possible. For example,
A method of subtracting the pre-conversion equivalent data at the beginning of the section from the pre-conversion data,
-Method of performing the subtraction in the (first half) section determination process
Etc. Also, the difference value is obtained by right bit shift,
A method of cutting out valid bits directly from the packed data of difference values,
-Specifying the difference value using the position value as a pointer to the register that stores the difference value
Etc. are also feasible. When iterative processing is performed by a loop, it takes time to detect the end condition of the iteration. Therefore, it is faster to perform the processing by arranging the difference values in the intervals in series without performing the iterative processing by the loop. Suitable for conversion.
[0051]
The process in the first embodiment is briefly described above.
(1) Compare the conversion target data with the data corresponding to the data before conversion at the head of each section, and load the difference value between the head converted data of the section including the conversion target data and each data in the section.
(2) The difference value is added to the first converted data of the section including the conversion target data according to the position in the section (before conversion) of the conversion target data.
It becomes. The concept for determining the post-conversion data in the first embodiment is schematically shown in the graph of FIG.
[0052]
The number of processing steps in the flowchart of FIG. 3 which is the first embodiment is as follows.
(1) Comparison of sections is 64 steps, data loading is 64 steps
(2) Difference value addition required / non-detection is 3 steps, difference addition is 6 steps
As a result, some other steps are added to the 137 steps.
[0053]
On the other hand, in the conventional well-known example, it becomes a flowchart as shown in FIG. If the bit width of the pre-conversion data and the post-conversion data is 8 bits, there are 256 tables, so the number of steps is
(1) Table comparison is 256 steps, data loading is 256 steps
Thus, 512 steps are required.
[0054]
FIG. 6 shows a block diagram of the configuration of the SIMD type microprocessor 2 that can realize the first embodiment. Components necessary for realizing the first embodiment are added to the SIMD type microprocessor 2 of FIG.
[0055]
The 8-bit data stored in the register of each PE is the pre-conversion data. The ALU 36 performs a size comparison between this data and the pre-section conversion data transferred from the global processor (GP) 4 via the immediate data bus 52. The result of the comparison is stored in the condition register 54, and the condition is satisfied in PE3 where the pre-conversion data is larger, and the subsequent data load is executed. In the data load, the global processor (GP) 4 stores the section head converted data in the lower 8 bits of the F register 40 and the difference data in the upper 8 bits via the immediate data bus 52.
[0056]
When the above comparison / loading in each section is completed, the difference data stored in the upper part of the F register 40 is stored in the register 34 included in each PE 3, but is shifted to the right by the shifter 44 at the time of the storage. Is done.
-The difference data in section 1 (between data 0 and data 1 in section n) is not shifted, for example, to register (R0)
The difference data in section 2 (between data 1 and data 2 in section n) is shifted by 2 bits to the right, for example to register (R1)
The difference data in section 3 (between data 2 and data 3 in section n) is shifted 4 bits to the right, for example, to register (R2)
Stored. The data stored in the registers R0 to R2 is masked (ie, ANDed with 3) by the ALU 36 for only the lower 2 bits, and returned to the respective registers R0 to R2.
[0057]
In order to detect the position in the section, the ALU 36 compares the lower 2 bits of the pre-conversion data stored in the register 34 of each PE 3 first. Here, if it is 1 or more, it is set so that T1 = 1 with respect to a predetermined bit of the condition register 54, for example, T1. Similarly, if 2 or more, the setting is made to T2 = 1 in the condition register 54, and if 3 or more, the setting is made to T3 = 1 in the condition register 54. The section head converted data stored in the lower part of the F register 40 is loaded into the A register 38, and with respect to the section head converted data (in the condition register 54), the register (R0) in PE3 where “T1 = 1” is satisfied. The difference value stored in the ALU 36 is added by the ALU 36, the difference value stored in the register (R1) is added by the ALU 36 in the PE3 of T2 = 1, and the difference value stored in the register (R2) in the PE3 of the T3 = 1. Are added by ALU36. Thus, the value remaining in the A register as the addition result becomes the converted value.
[0058]
<< Second Embodiment >>
FIG. 7 is a flowchart of the difference data use table conversion procedure in the SIMD type microprocessor according to the second embodiment of the present invention. The procedure of FIG. 7 is implemented by program code that operates the SIMD type microprocessor 2 of FIG. The flowchart will be described below.
[0059]
Step S100: First, a post-conversion table 60 as shown in FIG. 8 is prepared. It is assumed that the entire pre-conversion data / post-conversion data is divided into predetermined sections. Therefore, the post-conversion table 60 is also divided into the same (predetermined) sections. The number of divisions is
(1) Converted data / converted data bit width,
(2) Number of bits required for the difference value of the converted data,
(3) Register bit width that can be temporarily loaded into each PE3
Determined by For example, (1) the bit width of the pre-conversion data and the post-conversion data is 8 bits, (2) the difference value is 2 bits at the maximum, and (3) the bit width that can be temporarily loaded into each PE 3 is 16. As shown in FIG. 8, the difference data after the section head conversion is 6 bits, and the subsequent difference values are 5 bits each in 2 bits, and 6 sections of converted data are included in one section. Therefore, since the table conversion of 8-bit data is performed, 256 tables are divided. However, since six pieces of data for 256 are set as one section, there are 43 sections in total.
[0060]
Here, the difference data after the section head conversion is a value obtained by subtracting the head converted data of the previous section from the head converted data of the section (see FIG. 10).
[0061]
Step S102: Under the condition that the post-conversion table 60 is prepared, the processing of the flowchart of FIG. 7 is actually started. First, the number of designated sections and the data after cumulative conversion are set to “0”.
[0062]
Step S104: The pre-conversion data (0) at the beginning of the section 0 is compared with the conversion target (pre-conversion) data held in each PE 3 (step S106).
[0063]
Step S108; In PE3 where the conversion target data held in PE3 is larger, 6 bits of the converted differential data at the head of section 0 are added to the cumulative converted data, and five 2-bit differential values are converted. Read from table 60 and load into temporary register.
[0064]
Steps S110, S112 and S104; Next, the section is counted up by “1”. The pre-conversion equivalent data (4) at the beginning of the section 1 is compared with the conversion target (pre-conversion) data held in each PE 3 (step S106).
[0065]
Step S108: In PE3 where the conversion target data held in PE3 is larger, 6 bits of the converted differential data at the head of section 1 are added to the cumulative converted data, and five 2-bit differential values are converted. Read from table 60 and load into temporary register.
[0066]
Step S112: Counting up the section is repeated up to the section 42, and when the section specified value n becomes 43, the process proceeds to the next process.
[0067]
The section head data is a multiple of 0, 6, 12, 18, 24, 30 and 6 because a set of 6 data is one section.
[0068]
Step S114: In the latter half of the flowchart of FIG. 7, it is determined which position in the section (before conversion) the conversion target data corresponds to. In this embodiment, since one section includes six data, the remainder obtained by dividing the conversion target data by “6” indicates the position (m) in the section.
[0069]
Step S116: The value of this position (m) is compared with 0. If it is 0, the process proceeds to “END” (S122).
[0070]
Step S118: In the comparison of step S116, in “PE is not m” PE3, the difference value between the first converted data and the first converted data in the section is added to the cumulative converted data. The difference value to be added here is the lower 2 bits of the loaded difference value data.
[0071]
Step S120: Thereafter, 1 is subtracted from m, and the process returns to Step S116.
[0072]
Step S116: Next, the value of the position (m) is compared with 0. If it is 0, the process proceeds to “END” (S122).
[0073]
Step S118; In step S116, in “PE is not m” PE3, the difference value between the first converted data at the head and the second converted data in the section is added to the cumulative converted data. To do. Since the difference value to be added here is bits 2 to 3 of the loaded difference value data, the difference value data is shifted to the right by 2 bits before the addition to become the lower 2 bits.
[0074]
Step S120: Thereafter, 1 is subtracted from m, and the process returns to Step S116.
[0075]
Step S116: Next, the value of the position (m) is compared with 0. If it is 0, the process proceeds to “END” (S122).
[0076]
Step S118; In step S116, "m is not 0" PE3, the difference value between the first second-order converted data and the third-order converted data in the section is added to the cumulative converted data. To do. Since the difference value to be added here is bits 4 to 5 of the loaded difference value data, the difference value data is shifted to the lower 2 bits by further shifting to the right by 2 bits before addition.
[0077]
Step S120: Thereafter, 1 is subtracted from m, and the process returns to Step S116.
[0078]
In step S116, the loop processing from step S116 to step S120 is continued until “m = 0” is satisfied. However, the difference value added in step S118 shifts to the higher 2 bits of the loaded difference value data.
[0079]
The cumulative pre-conversion data obtained by the above processing becomes post-conversion data. Above, description of the flowchart of FIG. 7 is complete | finished.
[0080]
The processing in the second embodiment is briefly described above.
(1) Compare the conversion target data with the data before conversion at the head of each section, add the difference data after the head conversion of the section including the conversion target data to the accumulated value, Load the difference value,
(2) The difference value is added to the accumulated value according to the position in the section (before conversion) of the conversion target data.
It becomes. The concept for determining the post-conversion data in the second embodiment is schematically shown in the graph of FIG.
[0081]
The number of processing steps in the flowchart of FIG. 7 that is the second embodiment is as follows.
(1) Section comparison is 43 steps, data loading and addition is 43 steps
(2) Difference value addition required / non-detection is 5 steps, difference addition is 10 steps
Eventually, some other steps are added to the 101 steps. If the load process and the addition process are not performed simultaneously in (1) above, 43 steps are added.
[0082]
≪About extraction to difference value≫
In the description of the embodiment so far, the method of extracting the difference value has not been particularly mentioned, but in the normal processing as shown in the description of the block diagram of FIG. 6, bits other than the addition target are set to 0. Perform mask processing. For example, in the case of addition of lower 2 bits, 2-bit clipping can be performed by performing AND processing with the value 0x3 of the immediate data.
[0083]
On the other hand, in the case of the microprocessor 2 as described below, as described in the description related to FIG. 6, the process of cutting out the differential data individually and temporarily storing them in separate registers may be omitted. it can. That is, register data and immediate data are input to the input unit on one side of the ALU 36. At that time, by appropriately selecting and inputting 0 data at the same time, an arbitrary bit can be set in the above input to the ALU 36. The microprocessor 2 can be set to 0. In the embodiment shown in FIG. 6, the lower 2 bits of the input of the ALU 36 are data stored in the register, and the remaining bits are input of 0, so that the lower 2 bits can be added simultaneously with the mask process. Become.
[0084]
In the above description, the lower 2 bits were cut out.
・ Cut out bits 2 to 3
-Extraction of bit 4 to bit 5,
・ Cut out bits 6 to 7
In this case, a shift / extension unit 44 disposed immediately before the input of the ALU 36 is appropriately used to cut out and add predetermined bits. With the above configuration, addition performed by cutting out only arbitrary bits can be realized with a smaller number of steps.
[0085]
≪How to have difference data≫
In the first embodiment and the second embodiment according to the present invention described above, the conversion is such that the post-conversion data increases smoothly and monotonously as the pre-conversion data counts up. It is particularly effective in processing. That is, the conversion process as shown in the graphs of FIGS.
[0086]
The present invention can also be used in a conversion process in which post-conversion data is reduced (unlike the graphs of FIGS. 9 and 10). In this case, however, a bit indicating whether the difference data is increase data or decrease data, that is, a sign bit is required for each difference data.
[0087]
【The invention's effect】
As is apparent from the above description, the following effects can be obtained by using the present invention.
[0088]
By using the method according to the first aspect of the present invention, nonlinear conversion can be performed at high speed without using any approximate expression in the SIMD type microprocessor.
[0089]
By using the method according to the second aspect of the present invention, the number of steps required for nonlinear conversion can be reduced and the size of the post-conversion table can be reduced in the SIMD type microprocessor.
[0090]
By using the SIMD type microprocessor according to the third aspect of the present invention, it is possible to realize data extraction at an arbitrary bit position of input data and addition processing related to the bit with a small number of steps.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a SIMD type microprocessor according to the present invention.
FIG. 2 is a block diagram showing a more detailed configuration of a SIMD type microprocessor according to the present invention.
FIG. 3 is a flowchart of a difference data utilization table conversion procedure in the SIMD type microprocessor according to the first embodiment of the present invention;
FIG. 4 is an example (1) of a configuration of a post-conversion table.
FIG. 5 is a flowchart of a table conversion procedure in a SIMD microprocessor according to a conventional example.
FIG. 6 is a block diagram showing a configuration of a SIMD type microprocessor capable of realizing the first embodiment.
FIG. 7 is a flowchart of a difference data utilization table conversion procedure in the SIMD type microprocessor according to the second embodiment of the present invention;
FIG. 8 is an example (2) of a configuration of a post-conversion table.
FIG. 9 is a graph schematically showing a concept for determining post-conversion data in the first embodiment.
FIG. 10 is a graph schematically showing a way of thinking when determining post-conversion data in the second embodiment.
[Explanation of symbols]
2 ... SIMD type microprocessor, 3 ... Processor element (PE), 4 ... Global processor (GP), 6 ... Register file, 8 ... Arithmetic array, 34 ... Register 36 ... ALU, 38 ... A register, 40 ... F register, 42 ... multiplexer, 44 ... shift / expander, 50, 60 ... converted data.

Claims (2)

In a SIMD type microprocessor having a plurality of arithmetic units ,
One or more conversion tables for associating the pre-conversion data that is the input arithmetic data and the post-conversion data that is the output arithmetic data are set, and the correspondence defines the conversion process,
In the individual conversion table, it is assumed that the plurality of pre-conversion data is arranged in ascending order or descending order, and the plurality of pre-conversion data and the plurality of post-conversion data are divided into predetermined sections,
In the converted data of the above conversion table,
The actual value is stored in the converted data at the beginning of each section, and the difference data from the previous converted data is stored for the converted data other than the section head,
When calculating post-conversion data for conversion target operation data,
The conversion target data is stored in the plurality of arithmetic units ,
By associating the pre-conversion data and post-conversion data in the conversion table, the post-conversion data section to which the post-conversion data of the conversion target data should belong is determined,
Furthermore, the necessary difference data is added to the converted data at the beginning of the section to which the converted data belongs,
Obtaining converted data for the conversion target data,
Processing method of SIMD type microprocessor. In a SIMD type microprocessor having a plurality of arithmetic units ,
One or more conversion tables for associating the pre-conversion data that is the input arithmetic data and the post-conversion data that is the output arithmetic data are set, and the correspondence defines the conversion process,
In each of the above conversion tables, it is assumed that a plurality of pre-conversion data is arranged in ascending or descending order, and the plurality of pre-conversion data and the plurality of post-conversion data are similarly divided into predetermined sections. And
In the converted data of the above conversion table,
For the converted data at the head of each section, the first difference value from the section head data of the previous section is stored, and for the converted data other than the head of the section, second difference data from the previous converted data is stored. Is stored,
When calculating post-conversion data for conversion target operation data,
The conversion target data is stored in the plurality of arithmetic units ,
By associating the pre-conversion data and post-conversion data in the conversion table, the post-conversion data section to which the post-conversion data of the conversion target data should belong is determined,
First, the section head data of the section to which the converted data belongs is obtained by cumulative addition of the first difference values,
Furthermore, the second difference data is added as much as necessary to the section head data of the section to which the converted data belongs,
Obtaining converted data for the conversion target data,
Processing method of SIMD type microprocessor.

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