JP3736062B2 - Dual process I/O unit - Google Patents

Description

[0001]
[Technical field to which the invention pertains]
The present invention relates to a duplicated process input/output device in which a process input/output device that directly interfaces with a process in a controller is duplicated in order to improve the reliability in a distributed control system.
[0002]
2. Description of the Related Art
Figure 11 shows an example of the configuration of a distributed control system. In Figure 11, 1 is a man-machine interface device, 2 is a control LAN, and 31 to 3n are controllers. As shown in Figure 11, a distributed control system is a system in which multiple controllers (several dozen in a large-scale system) installed in a distributed manner are connected by a control LAN and managed by one to several man-machine interface devices. Figure 12 shows an example of the configuration of the controller in Figure 11. In Figure 12, 4 is a control MPU, 5 is an IO link, and 61 to 6n are process I/O devices. In Figure 12, the control MPU performs calculations for process control and exchanges data with multiple process I/O devices (e.g., 32 devices) installed in a distributed manner via the IO link. The process I/O devices are connected to various sensors and actuators of the process and convert analog quantities of the process into digital quantities that can be calculated by the control MPU. Such controllers are generally required to be highly reliable. An example of a highly reliable controller is shown in Figure 13. In Fig. 13, 4A and 4B are control MPUs, 5A and 5B are IO links, and 61 to 6n are process I/O devices. As shown in Fig. 13, the control MPU and the IO links are duplicated, and the process I/O devices 61 to 6n are connected to the IO links of 5A and 5B, respectively.
[0003]
Fig. 14 shows an example of the configuration of a process input/output device corresponding to the duplication of the control MPU and IO link. In Fig. 14, 5A and 5B are IO links, 7A and 7B are transmission control modules, 8 is an IO bus, and 91 to 9n are IO modules. In Fig. 14, the transmission control module interfaces with the IO link and IO bus and relays data exchange between the control MPU and the IO module. On the other hand, the IO module directly interfaces with the process and converts analog and digital quantities. In the example of Fig. 14, the transmission control module is duplicated corresponding to the duplication of the control MPU and IO link, and the transmission control modules 7A and 7B are switched corresponding to the switching between operation/standby of the control MPU and IO link.
[0004]
FIG. 15 shows an example of the configuration of a process I/O device in which not only the transmission control module but also the IO module and IO bus are duplicated. In FIG. 15, 61 is an IO shelf, which has two transmission control modules and 16 mounting slots for IO modules, and one IO shelf constitutes one process I/O device. 8A and 8B are IO buses, and 91A, 91B to 98A, 98B are IO modules. As shown in FIG. 15, the same type of IO modules 91, 92, ..., 98 are mounted in slot numbers 00, 01, 02, 03, ..., 14, and 15, respectively, and are duplicated in pairs A and B. One of the pair A and B is active and the other is standby, and both are connected to the process. An input signal from the process is input to both the active and standby, and only the active side outputs a signal to the process.
[0005]
[Problem to be solved by the invention]
However, the conventional technique shown in FIG. 15 has the following problems.
(1) If there is an abnormality in the working side of a duplicated IO module, the standby side becomes working and takes over the processing, but at that time, the abnormality in the working side must be reliably detected. In addition, the standby side that takes over the processing must be constantly confirmed to be normal. Furthermore, it must be ensured that the failure of one of the IO module pair does not affect the other.
[0006]
(2) The IO modules must be capable of being inserted and removed while the power is on. However, when the standby IO module is being inserted or removed while the power is on, the output signal to the process must not be disturbed, particularly in the output module.
(3) IO module pairs must be of the same type, but a state in which modules of different types are paired must be quickly detected and notified to the operator.
(4) If an abnormality occurs in the operation/standby switching signal, it is possible that both of the IO module pairs may be in operation or in standby. To resolve this situation, it is necessary to notify the operator of the abnormal state.
[0007]
[Means for solving the problem]
In order to solve the above problem, the present invention uses the following means to detect an abnormality in the working/standby IO modules.
(1) In the pulse input module, the process interface section and pulse counter are duplicated, and the two pulse count values are compared. If they do not match, it is determined that there is an abnormality in the pulse input module.
(2) In the pulse output module, the on/off state of the output transistor is constantly read back, and if the readback is abnormal, it is considered that there is an abnormality in the pulse output module.
(3) As for the IO module on the standby side, since it does not output to the process, readback is performed at the stage preceding the final output stage.
[0008]
(4) In addition, in order to prevent disturbances when the IO module is connected or disconnected while the IO module is in a live state, or to prevent a drop in input impedance when the power supply is abnormal, a normally-off photoMOS relay is inserted in the process interface section of the IO module, and this is linked to the on/off of the power supply of the IO module and controlled with a specified time constant.
(5) In addition, in preparation for the case where different types of IO modules are paired, the transmission control module constantly monitors the IDs of the IO module pair, and in the event of an ID mismatch, notifies the control MPU of an alarm.
(6) In addition, in case the IO module pair goes into an operating/operating or standby/standby state, the transmission control module constantly monitors the state of the IO module pair, and if it detects an operating/operating or standby/standby state, it sends a command to the IO module pair via the IO bus to switch to operating or standby, and notifies the control MPU of an alarm.
[0009]
That is, the invention described in claim 1 is a process input/output device that is connected to a control MPU via an IO link to form a controller,
The system is composed of a plurality of IO modules, a transmission control module that controls the plurality of IO modules via an IO bus, and an IO shelf that stores the transmission control module and the IO modules.
A duplicated process input/output device in which the same type of IO module is mounted in each of two adjacent mounting slots of an IO shelf, one of which is active and the other is in standby to duplicate the IO modules, output data to a process is provided to both of the IO module pair via a transmission control module, and only the active side determined by an active/standby switching circuit between the IO module pair outputs to the process, and input from the process is connected to both of the IO module pair so that the transmission control module notifies a control MPU of only data of the active side determined by the switching circuit;
a means for duplicating a process interface unit and a pulse counter in a pulse input module of an IO module pair;
a means for comparing the two pulse count values obtained by duplication and determining that a major fault has occurred if they are not the same, and switching the IO module pair between operation and standby;
a means for converting an input current into a voltage using a reference resistor and then A/D converting the voltage, the means being provided in the working module of the IO module pair;
The standby module of the IO module pair is provided with a means for converting the input current into a voltage using a resistance obtained by adding the reference resistance of the operating module and the on resistance of a change-over switch that is turned on when the module is operating, and then converting the voltage into an A/D signal .
[0019]
[0023]
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
Fig. 1 shows a first embodiment of the present invention. In Fig. 1, reference numeral 100 denotes a processor such as a one-chip microcomputer, 101A and 101B denote input filters, 102A and 102B denote comparators, 103A and 103B denote counters, 104A and 104B denote registers, 105 denotes a latch signal of the counter output to the register, 106A and 106B denote read signals of the register, and 107 denotes an output signal of the register.
[0020]
In Fig. 1, a pulse input signal is connected to input filters 101A and 101B, where noise components are removed, and then the signal is converted from a 24V level to a 5V level by a comparator, waveform-shaped, and input to the clock input terminals of counters 103A and 103B. The counters 103A and 103B count the waveform-shaped pulse input signals that are almost in phase. The processor 100 latches the outputs of the counters 103A and 103B into registers 104A and 104B using a latch signal 105 obtained using the parallel output port of the processor. The timing of this latching is when the counter output is not changing, that is, during the period when the pulse input signal is at a low level.
[0021]
This is because the counter output signal changes at the rising edge of the pulse input signal. After the above latching, the processor 100 outputs register read signals 106A, 106B to read the outputs of the registers 104A, 104B and check whether they match. If they match, the data is notified to the control MPU via the transmission control module. If they do not match, it is considered that the own module has failed, the right of operation is abandoned, and processing is handed over to the other module in the duplicated module pair. The register read signals 106A, 106B are usually generated as an AND signal of the processor read signal and the register selection signal obtained by decoding the address.
[0022]
FIG. 2 shows a first embodiment of the present invention. In FIG. 2, 100 is a processor such as a one-chip microcomputer, 110 is a pulse width output signal, 111 is an operating/standby state signal, 112 is a NAND gate, 113 is an inverter, and 114 is a read-back signal. In FIG. 2, the pulse width output signal 110 is output from a parallel output port of the processor 100 by a program. On the other hand, the operating/standby state signal 111 is a signal determined by an operating/standby switching circuit between an IO module pair, and is at a high level when in an operating state. 112 is a NAND gate such as a 74LS38, and only modules in an operating state are output to the process. The read-back signal 114 is a signal that monitors the on/off state of an output transistor Tr2 to the process, is connected to a parallel input port of the processor 100, and is compared with the state of the parallel output port by a program.
[0023]
This comparison is performed only by the module in operation, and if there is a mismatch, it is considered to be a failure of the own module, the right of operation is abandoned, and the processing is handed over to the other module of the duplicated module pair. In Fig. 2, a diode with a high threshold voltage, such as 74HC14, is used for inverter 113 so that the voltage obtained by adding the on-voltage of transistor Tr2 and the forward voltage of diode D1 can be judged as low when transistor Tr2 is on. Diode D1 is inserted to prevent current from flowing from the process side to Vcc when transistor Tr2 is off, since the process side voltage applied to the collector of transistor Tr2 is usually +24V, which is higher than Vcc's +5V.
[0024]
Fig. 3 shows a second embodiment of the present invention. Fig. 3 shows an example in which a diode D2 is added to Fig. 2. By adding the diode D2, even if the output readback check of the working module is normal, if the output state is abnormal, it can be assumed that the transistor Tr2 of the standby module, which should be in the off state, is in the on state due to some abnormality, so that it becomes easier to take measures such as replacing the standby module with a good one. In Fig. 3, if the diode D2 is in the conductive state and a stuck-at failure occurs, the failure of the standby module will spread to the working module and the above-mentioned state will disappear, but since the failure rate of a single diode is sufficiently low compared to other parts, such cases are rare and the insertion of the diode D2 is sufficiently effective.
[0025]
Fig. 4 shows a third embodiment of the present invention. In Fig. 4, 100 is a processor such as a one-chip microcomputer, 111 is an operating/standby state signal, 120 is a current input signal which is a process load, 123 is a multiplexer, 124 is a selection signal for the multiplexer 123, 125 is a voltage signal to be AD converted, Q1 is a FET (field effect transistor), and R1 is a reference resistor. In Fig. 4, the operating/standby state signal 111 is determined by an operating/standby switching circuit between the IO module pair as described above, and only the operating module becomes high level, causing the FET Q1 to conduct.
[0026]
In the working module, a process current input signal 120 (usually 4 to 20 mA) is converted to a voltage (usually 1 to 5 V) using a reference resistor R1 (usually 250 Ω) and the input signal 122 is selected by a multiplexer 123 and subjected to AD conversion as a voltage signal 125. Meanwhile, in the standby module, FET Q1 is off. If an abnormality occurs in the working module, the standby module must immediately take over the processing. In that case, it is necessary to constantly AD convert an input voltage equivalent to that of the working module and warm up the operational amplifier and AD converter.
[0027]
Therefore, in this embodiment , the standby module converts the current input signal 120 into a voltage using the resistance obtained by adding the on-resistance of the FET Q1 of the operating module and the resistance of the resistor R1, and selects the input signal 121 using a multiplexer 123 to perform AD conversion as a voltage signal 125. Since the on-resistance of the FET Q1 is about several Ω, which is sufficiently small compared to the resistor R1, the standby module also constantly AD converts an input voltage substantially equivalent to that of the operating module. In this embodiment , it is assumed that the time fluctuation of the current input signal is sufficiently long compared to the switching time between operating and standby, and when the standby module takes over the processing, it is sufficient to consider the output response time to the voltage fluctuation equivalent to the on-resistance of the FET Q1, and the AD conversion accuracy can be guaranteed with a short takeover time.
[0028]
Fig. 5 shows a fourth embodiment of the present invention. In Fig. 5, 100 is a processor such as a one-chip microcomputer, 111 is an operating/standby state signal, 120 is a process load, 123 is a multiplexer, 124 is a selection signal for the multiplexer 123, 125 is a voltage signal to be AD converted, Q1, Q2, and Q3 are FETs (field effect transistors), and R1 is a reference resistor. Since this module is a current output module, the processor 100 outputs a PWM signal ( pulse width modulation signal ) 130 corresponding to the digital value of the output, which is smoothed and amplified by a smoothing and amplification circuit 140 and converted into a voltage signal 131. This is further converted into a current by a voltage/current conversion circuit 141 and output to the process load 120.
[0029]
5, the operating/standby state signal 111 is determined by the operating/standby switching circuit between the IO module pair as described above, and only the operating module goes High, causing the FETs Q1 and Q2 to conduct. Therefore, only the operating module supplies current to the process load 120, and this current output signal is converted to a voltage by the reference resistor R1, which is selected by the multiplexer 123 and AD converted as a voltage signal 125, which is compared with the digital value described above to perform self-diagnosis of the module.
[0030]
On the other hand, in the standby module, FETs Q1 and Q2 are off and FET Q3 is on. Here, signal 111 is a signal that goes High when in standby. The standby module does not output the output of the voltage/current conversion circuit to the process, but instead leads it to reference resistor R1 via FET Q3, and the resulting voltage signal is selected by multiplexer 123 and converted into voltage signal 125, which is then compared with the digital value mentioned above to perform self-diagnosis of the module. By doing this, even in the standby module, self-diagnosis of the circuits excluding FETs Q1 and Q2 is always possible.
[0031]
Fig. 6 shows a fifth embodiment of the present invention. The components of Fig. 6 are the same as those of Fig. 5. In Fig. 6, unlike Fig. 5, the standby module uses the output voltage of the smoothing and amplifying circuit 140 as a readback signal 121, which is selected by a multiplexer 123 and converted into a voltage signal 125 by AD conversion, which is compared with the digital value described above to perform self-diagnosis of the module. In the embodiment of Fig. 6, the standby module does not perform self-diagnosis of the voltage/current conversion circuit 141, but does not supply a current of 4 to 20 mA, so that the power consumption of the module is reduced, heat generation is suppressed, and reliability is improved accordingly.
[0032]
Fig. 7 shows a sixth embodiment of the present invention. In Fig. 7, R1 is a resistor, PR1 is a photoMOS relay, ZD1 is a Zener diode, D1 to D4 are diodes, and Vdd and Vss are power supplies. In general, in the analog input section of the process input, in order to protect the module when a voltage exceeding the rated voltage is applied, a circuit is usually provided to clamp the overvoltage to the power supply voltage of the analog input module. In Fig. 7, diodes D1 to D4 are clamping diodes provided for the above purpose. In such an analog input module pair with a protection circuit, if the power supply of the working module fails, switching between working and standby is performed, but the input impedance of the working module that has failed is reduced due to the diodes D1 to D4, and the accuracy of the AD conversion is no longer guaranteed.
[0033]
If the protection circuit is eliminated, this problem will be eliminated, but if an overvoltage is applied, the module will be damaged. PR1 in FIG. 7 is inserted to solve this problem, and is driven by the module power supply of the clamp circuit. ZD1 is provided to detect an abnormality in the module power supply of the clamp circuit, and if the module power supply of the clamp circuit fails, the photoMOS relay PR1 turns off, and the input impedance of the operating module does not decrease. On the other hand, if the module power supply of the clamp circuit is normal, the photoMOS relay PR1 is always on, and the protection circuit is effective.
[0034]
Fig. 8 shows a seventh embodiment of the present invention. In Fig. 8, reference numeral 100 denotes a processor such as a one-chip microcomputer, 111 denotes an operating/standby state signal, 150 denotes a voltage monitoring circuit, 151 denotes a reset signal, PR1 denotes a photoMOS relay, R1 denotes a resistor, C1 denotes a capacitor, D1 and D2 denote diodes, and Tr1 denotes a transistor. When an IO module is mounted on an IO shelf 61 and the power supply Vcc of the IO module is turned on, the voltage monitoring circuit 150 outputs a reset signal 151 for a certain period of time and then releases it.
[0035]
The processor 100 starts operation after the reset signal is released, and outputs an active/standby state signal 111 determined by an active/standby switching circuit between the IO module pair. In the active state, the transistor Tr1 is driven. During the reset period, the reset signal is low and a signal is present, and the capacitor C1 is discharged through the diode D1. After the reset is released, charging begins through the resistor R1.
When the charging voltage exceeds the sum of the forward voltage of diode D2 and the forward voltage of the LED of photoMOS relay PR1, current flows through the LED, and photoMOS relay PR1 becomes conductive.
[0036]
Therefore, if the charging time determined by resistor R1 and capacitor C1 is set longer than the time required for the processor 100 to determine the state of the registers and output ports by the program after the processor 100 releases the reset, an erroneous signal will not be output to the process side. When the IO module is removed from the IO shelf, it is removed in the standby state, so the transistor Tr1 is in the off state, and therefore the photoMOS relay PR1 is also in the off state. When Vcc drops, there is an undefined voltage region in which the transistor Tr1 cannot be turned off, but the voltage monitoring circuit 150 generates a reset signal at about +4.5V relative to Vcc +5V, which causes the capacitor C1 to discharge, so that an erroneous signal will not be output to the process side even when the IO module is removed.
[0037]
Fig. 9 shows an eighth embodiment of the present invention. The components in Fig. 9 are the same as those in Fig. 15, but a signal 160 is added to the IO shelf 61 to notify the transmission control module that the IO module is duplicated. In other words, this embodiment is based on the premise that the IO module is duplicated on an IO shelf basis. When the transmission control module is installed in such an IO shelf, the processor in the transmission control module reads the signal 160 and recognizes that the IO module is duplicated.
[0038]
In this case, a fixed-period processing task is started in the transmission control module, and an ID read command is sent to the IO modules installed in each slot of the IO shelf. In response, each IO module responds with its own ID (model). The transmission control module and each IO module are connected by an IO bus, which is a serial communication bus, and the communication method is a polling selecting method. When the transmission control module reads the ID of each IO module, it checks whether the IDs of the IO module pair match, and if they do not match, it notifies the control MPU of the slot number and ID together with an alarm via the IO link. This alarm is notified to the operator.
[0039]
A ninth embodiment of the present invention will be described with reference to Figures 9 and 10. Figure 9 shows a configuration method for duplexing IO modules, and switching between active and standby modes between IO module pairs is performed by an active/standby switching signal D. Figure 10 shows the details of this switching circuit, with *WDTE being the overflow signal of the watchdog timer and *RST being the reset signal, both of which are generated by hardware. Also, *MSTC is a signal that is started by the program of the processor of each module. After the processors of the IO module pair are released from reset, they each activate (high) the *MSTC signal with a certain time delay.
[0040]
Between IO module pairs, there is a difference in the time delay depending on the mounting slot number; for example, if IO module A enables the *MSTC signal earlier, IO module A will be in operation and IO module B will be in standby. At this time, the *WDTE signal is inactive (High). The operation/standby state of the IO module pair is indicated by the M/S signal, and when the M/S signal is High, it indicates the operation state. Also, once the operation/standby state has been determined, if an abnormality occurs in the operating module, for example if there is a power supply abnormality, the *RST signal will be enabled, and if the program has run away, the *WDTE signal will be enabled.
[0041]
Also, in the case of a self-diagnostic abnormality, the program disables the *MSTC signal, and the active module transitions to a standby state, causing the standby module to become active. This type of active/standby switching circuit has the advantage that it can switch between active and standby instantly, but it also has a disadvantage: if the active/standby switching signal D suffers a stuck-at fault, active/standby switching cannot be performed normally. For example, if the active/standby switching signal D suffers a stuck-at fault in the low state, both of the IO module pairs may be in a standby state, and if it suffers a stuck-at fault in the high state, both may be in a standby state.
[0042]
In order to resolve these conditions, the transmission control module transmits input/output data to each IO module via the IO bus, and in response, each IO module notifies the transmission control module of its own operating/standby state. When the transmission control module receives this response, it checks the operating/standby state of the IO module pair, and if it detects an operating/operating or standby/standby state, it issues a transition command to standby or operating to one side of the corresponding IO module pair. If the corresponding IO module pair can return to the operating/standby state by issuing the command, it notifies the control MPU of a minor fault alarm, and if it cannot return to the operating/standby state, it notifies the control MPU of a major fault alarm.
[0043]
Effect of the Invention
As described above, according to the present invention, in a remote process input/output device connected to a control MPU via an IO link, problems that arise when IO modules are duplicated are solved, and the reliability of the process control system is further improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a third embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a fourth embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a fifth embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a sixth embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a seventh embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of an eighth embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a ninth embodiment of the present invention.
FIG. 11 is a block diagram showing an example of the configuration of a distributed control system to which the present invention is applied.
12 is a block diagram showing an example of a main part of FIG. 11.
13 is a block diagram showing another example of the main part of FIG. 11.
14 is a block diagram showing an example of a main part of FIG. 13.
15 is a block diagram showing another example of the main part of FIG. 13.
[Explanation of symbols]
4A, 4B Control MPU
5A, 5B IO link 7A, 7B Transmission control module 8A, 8B IO bus 61 IO shelf (process input/output device)
100 Processor 101A, 101B Input filter 102A, 102B Comparator 103A, 103B Counter 104A, 104B Register 105 Latch signal 106A, 106B Read signal 107 Output signal 110 Pulse width output signal 111 Run/standby state signal 112 NAND gate 113 Inverter 114 Readback signal 120 Process load (current input signal)
121 Readback signal 123 Multiplexer 124 Selection signal 125 Voltage signal 130 PWM signal 131 Voltage signal 140 Smoothing and amplifying circuit 141 Voltage/current conversion circuit 150 Voltage monitoring circuit 151 Reset signal 160 Dual setting signal *WDTE Overflow signal *RST Reset signal

Claims (1)

A process input/output device that is connected to a control MPU via an IO link to form a controller,
The system is composed of a plurality of IO modules, a transmission control module that controls the plurality of IO modules via an IO bus, and an IO shelf that stores the transmission control module and the IO modules.
A duplicated process input/output device in which the same type of IO module is mounted in each of two adjacent mounting slots of an IO shelf, one of which is active and the other is in standby to duplicate the IO modules, output data to a process is provided to both of the IO module pair via a transmission control module, and only the active side determined by an active/standby switching circuit between the IO module pair outputs to the process, and input from the process is connected to both of the IO module pair so that the transmission control module notifies a control MPU of only data of the active side determined by the switching circuit;
A means for duplicating a process interface unit and a pulse counter in a pulse input module of an IO module pair;
a means for comparing the two pulse count values obtained by duplication and determining that a major fault has occurred if they are not the same, and switching the IO module pair between operation and standby;
a means for converting an input current into a voltage using a reference resistor and then A/D converting the voltage, the means being provided in the working module of the IO module pair;
a means for converting an input current into a voltage using a resistance obtained by adding a reference resistance of the module on the standby side of the IO module pair and an on-resistance of a changeover switch that is turned on when the module is on, and then A/D converting the voltage;
1. A duplicated process input/output device comprising:

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