JP3739364B2 - CMOS output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CMOS output circuit for preventing latch-up in a complementary metal-oxide semiconductor (CMOS) type semiconductor integrated circuit.
[0002]
[Prior art]
FIG. 2 is a schematic cross-sectional view of a CMOS output circuit in a conventional general CMOS type semiconductor integrated circuit, and FIG. 3 shows a connection relationship between bipolar transistors and resistors formed parasitically in the CMOS output circuit of FIG. It is a circuit diagram.
[0003]
The CMOS output circuit shown in FIG. 2 is formed on, for example, an N-type substrate (substrate) 1. A P-well 2 is formed in the N-type substrate 1, a P-channel MOS transistor (hereinafter referred to as “PMOS”) 10 is formed on the main surface of the substrate 1, and further on the main surface of the P-well 2. An N-channel MOS transistor (hereinafter referred to as NMOS) 20 is formed. The PMOS 10 includes a source 10S and a drain 10D made of a p ⁺ diffusion layer formed on the main surface of the substrate 1, and a gate 10G formed between the source 10S and the drain 10D. The NMOS 20 is composed of a source 20S and a drain 20D made of an n ⁺ diffusion layer formed on the main surface of the P well 2, and a gate 20G formed between the source 20S and the drain 20D. Further, an n ⁺ diffusion layer 31 is formed in the vicinity of the source 10S of the PMOS 10 and a p ⁺ diffusion layer 32 is also formed in the vicinity of the source 20S of the NMOS 20.
[0004]
The source 10S and n ⁺ diffusion layer 31 of the PMOS 10 are connected to a high-level power supply (hereinafter referred to as VCC), the gate 10G of the PMOS 10 and the gate 20G of the NMOS 20 are commonly connected to the input terminal IN, and the drain 10D of the PMOS 10 and the drain of the NMOS 20 20D is commonly connected to the output terminal OUT. The source 20S and the p ⁺ diffusion layer 32 of the NMOS 20 are connected to a low power supply (hereinafter referred to as VSS).
[0005]
In such a CMOS output circuit, as shown in FIG. 3, bipolar transistors T1, T2, T3, T4 and a parasitic resistance R2 are usually formed in a parasitic manner. In FIG. 2, a PNP transistor T1 is formed parasitically between the drain 10D and the P well 2, and a PNP transistor T3 is also formed between the source 10S and the P well 2. Further, parasitic NPN transistors T2 and T4 are also formed between the substrate 1 and the source 20S and drain 20D. The bases of the transistors T1 and T3 are connected to the n + diffusion layer 31, and the bases of the transistors T2 and T4 are connected to the p + diffusion layer 32.
[0006]
Further, as shown in FIG. 3, a parasitic resistance R1 is formed in the P-well 2, which is the collector of the transistor T1, the base of the transistor T2, the collector of the transistor T3, the base of the transistor T4, and the emitter of the transistor T2. And VSS. The resistor R2 in the substrate 1 is connected between VCC and the emitter of the transistor T3 and the base of the transistor T1, the collector of the transistor T2, the base of the transistor T3, and the collector of the transistor T4. Note that i1 and i2 in FIG. 3 are collector currents.
[0007]
In this type of CMOS output circuit, when an “H” level (VCC level) signal is input to the input terminal IN, the PMOS 10 is turned off, the NMOS 20 is turned on, and the output terminal OUT is turned “L” level (VSS level). ) When an “L” level signal is input to the input terminal IN, the PMOS 10 is turned on, the NMOS 20 is turned off, and the output terminal OUT is set to the “H” level.
[0008]
[Problems to be solved by the invention]
However, in the CMOS output circuit configured as described above, a latch-up phenomenon peculiar to the CMOS circuit occurs due to a trigger (generally, a voltage applied higher than the VCC level or a voltage applied lower than the VSS level) from the output terminal OUT. There was a problem that it was easy to do.
[0009]
Here, the mechanism leading to the occurrence of latch-up will be described with reference to FIG. For example, when a trigger voltage higher than the VCC level is applied to the output terminal OUT, the transistor T1 is turned on. As a result, the collector current i1 flows from the output terminal OUT to the VSS through the transistor T1 and the parasitic resistance R1 of the P well 2. At this time, the base potential of the transistor T2 rises due to the parasitic resistance R1 in the P-well 2, and the base and emitter of the transistor T2 are forward-biased and turned on. When the transistor T2 is turned on, the collector current i2 of the transistor T2 flows from the VCC through the resistor R2 in the substrate 1 and further flows to the VSS through the transistor T2. Therefore, the resistor R2 in the substrate 1 causes the transistor T2 The base potential of T3 drops, and the base and emitter are forward biased and turned on.
[0010]
Thus, when the transistors T2 and T3 are turned on, positive feedback is applied to them, and even if there is no trigger from the output terminal OUT, a current continues to flow from VCC to VSS, so-called a latch-up state. This may cause malfunction of the integrated circuit, melting of the power supply line, or destruction of the element.
[0011]
Similarly, when a trigger voltage lower than the VSS level is applied to the output terminal OUT, the transistors T4, T3, and T2 are turned on in the order of the transistors T4, T3, and T2, and the latch-up state is also reached. .
[0012]
The present invention provides a CMOS output circuit that solves the problem that the prior art has had that latch-up is likely to occur due to a trigger from the output terminal OUT and it is difficult to reduce it with a relatively simple configuration. It is to provide.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, a first invention of the present invention is a CMOS output circuit that operates by being supplied with a high voltage and a low voltage, and includes a first NMOS, a second NMOS, PMOS and a resistance component.
[0014]
The first NMOS has a first portion of a first gate, an N-type source, and an N-type first drain. The second NMOS is electrically connected to the first portion of the first gate and extends in the same direction, and is common to the first NMOS and the second NMOS. N-type source and N-type second drain. The first PMOS has a first portion of a second gate, a P-type source, and a P-type first drain. The second PMOS is electrically connected to the first portion of the second gate and is shared with the first PMOS, the second portion of the second gate extending in the same direction. A P-type source and a P-type second drain.
[0015]
Further, the resistance component is added in series to the source of at least one of the first and second NMOS and the first and second PMOS transistors. The resistance component can be obtained by making the number of contacts with the source of the one MOS transistor smaller than the number of contacts with the drain of the one MOS transistor.
[0016]
A second invention is a CMOS output circuit that operates by being supplied with a high voltage and a low voltage, and includes a substrate having a main surface and first, second, third, and fourth MOS transistors.
[0017]
Here, the first MOS transistor is formed in a first region of the main surface of the substrate, and has a first conductivity type source, a first gate, to which one of the high voltage or the low voltage is supplied. A first portion; and a first drain of the first conductivity type connected to the output terminal. The second MOS transistor is formed in a first region of the main surface of the substrate, and has a first conductivity type common to the first MOS transistor to which one of the high voltage and the low voltage is supplied. A second portion of the first gate electrically connected to the first portion of the first gate and extending in the same direction; and the first conductivity type connected to the output terminal. It has a second drain.
[0018]
The third MOS transistor is formed in a second region of the main surface of the substrate, and is supplied with the other of the high voltage and the low voltage, the second conductivity type source, and the first of the second gate. And a second drain of the second conductivity type connected to the output terminal. Further, the fourth MOS transistor is formed in a second region of the main surface of the substrate, and has a second conductivity type common to the third MOS transistor to which the other of the high voltage and the low voltage is supplied. A second portion of the second gate electrically connected to the first portion of the second gate and extending in the same direction, and the second conductive connected to the output terminal A second drain of the mold;
[0019]
Then, the number of contacts on the source side of any one of the first, second, third, or fourth MOS transistors is the number of contacts on the first drain side of the one MOS transistor. It has resistance means connected in series to the source of the one MOS transistor formed by making the number less than the number.
[0020]
According to the first and second aspects of the present invention, the number of the plurality of contacts on the source side of the MOS transistor is made smaller than the number of the plurality of contacts on the drain side, whereby the high voltage (VCC) and the low voltage (VSS). A resistance component (resistance means) is added in series to the emitter portion of the bipolar transistor parasitically formed between the two, and the on-state of the bipolar transistor when the trigger voltage is applied to the output terminal by the resistance component (resistance means) Transition to is suppressed. Therefore, the problem can be solved.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a circuit diagram of a connection relationship between a parasitic bipolar transistor and a resistor in a CMOS output circuit showing the principle of the embodiment of the present invention. Elements common to those in FIGS. Is attached.
[0022]
The CMOS output circuit of FIG. 4 has a structure in which parasitic resistors R3 and R4 as resistance means are added in series to the emitter of the parasitic NPN transistor T2 and the emitter of the PNP transistor T3 shown in FIG. Others are the same as the conventional structure. That is, the CMOS output circuit of FIG. 4 has a structure in which parasitic resistors R3 and R4 are added in series to the sources 10S and 20S of the PMOS 10 and NMOS 20 of FIG.
[0023]
In the CMOS output circuit of FIG. 4, for example, when a trigger voltage higher than the VCC level is applied to the output terminal OUT as in the conventional description, the emitter and base of the transistor T1 are forward-biased and turned on. The base potential of the transistor T2 rises due to the parasitic resistance R1 in the P-well 2, and the emitter-base is forward-biased, and the transistor T2 is turned on. Thus, the transistors T1 and T2 are turned on as in the conventional case, but the collector current i2 flowing through the resistor R2 in the substrate 1 is limited by the resistor R3 connected in series with the emitter of the transistor T2. As a result, the decrease in the base potential of the transistor T3 is moderated. As a result, the transistor T3 does not easily shift to the on state, so that the transistors T2 and T3 are not positively fed back to each other, and the latch-up state is hardly generated.
[0024]
Conversely, even when a trigger voltage lower than the VSS level is applied to the output terminal OUT, the collector current of the transistor T3 is limited by the resistor R4 connected in series to the emitter of the transistor T3. It becomes difficult to shift to the on-state, thereby preventing the occurrence of latch-up. Accordingly, the latch-up can be accurately reduced with a simple structure in which parasitic resistors R3 and R4 are added to the emitter portions of the transistors T2 and T3 formed in a parasitic manner.
[0025]
FIG. 1 is a schematic layout diagram of a CMOS output circuit showing an embodiment of the present invention using the principle of FIG.
[0026]
In the CMOS output circuit of FIG. 1, for example, a plurality of PMOSs 10 (10-1, 10) each including a source 10S, a drain 10D, and a gate 10G are disposed in the second region above the main surface of the N-type substrate (substrate) 1. −2,... Are arranged in the horizontal direction, and a plurality of NMOS 20 including a source 20S, a drain 20D, and a gate 20G are formed on the main surface of the P well 2 which is the lower first region. (20-1, 20-2,...) Are arranged in the horizontal direction.
[0027]
In the plurality of PMOSs 10 (10-1, 10-2,...) Of FIG. 1, for example, the first PMOS 10-1, which is the third MOS transistor at the left end, is connected to the output terminal OUT. 1 drain 10D1, a source 10S1 connected to VCC on the right side opposite to this, and a first portion 10G1 of a second gate 10G disposed between the drain 10D1 and the source 10S1 and connected to the input terminal IN It consists of and. A second PMOS 10-2, which is a fourth MOS transistor adjacent to the right side, has a left source 10S1 connected to VCC (this is common with the source of the PMOS 10-1) and an output terminal on the right side opposite to the source 10S1. The second drain 10D2 connected to OUT, the second drain 10D2 disposed between the drain 10D2 and the source 10S1, electrically connected to the first portion 10G1 of the second gate 10G and extending in the same direction And the second portion 10G2 of the gate 10G.
[0028]
In the plurality of NMOS 20 (20-1, 20-2,...) Shown in FIG. 1, for example, the first NMOS 20-1 that is the first MOS transistor at the left end is connected to the left terminal connected to the output terminal OUT. 1 drain 20D1, a source 20S1 connected to VSS on the right side opposite to this, and a first portion 20G1 of the first gate 20G disposed between the drain 20D1 and the source 20S1 and connected to the input terminal IN It consists of and. The second NMOS 20-2, which is the second MOS transistor adjacent to the right side, has a left source 20S1 (common to the source of the NMOS 20-1) connected to VSS and an output terminal on the right side opposite to the source 20S1. The second drain 20D2 connected to OUT, and the first drain 20D2 disposed between the drain 20D2 and the source 20S1, electrically connected to the first portion 20G1 of the first gate 20G and extending in the same direction. And the second portion 20G2 of the gate 10G.
[0029]
On the source 10S (10S1,...) Of each PMOS 10 (10-1, 10-2,...), A plurality of contacts 41 are arranged in series along the longitudinal direction (longitudinal direction). A plurality of contacts 42 are also arranged in series along the longitudinal direction (vertical direction) on the drain 10D (10D1, 10D2,...). Similarly, a plurality of contacts 51 are arranged in series along the longitudinal direction (vertical direction) on the source 20S (20S1,...) Of each NMOS 20 (20-1, 20-2,...). Further, a plurality of contacts 52 are arranged in series along the longitudinal direction (vertical direction) on the drain 20D (20D1, 20D2,...).
[0030]
In order to add the parasitic resistances R3 and R4 of FIG. 4 as resistance means, the number of contacts 41 on the source 10S side of each PMOS 10 is made smaller than the number of contacts 42 on the drain 10D side. Thus, the contact resistance component of the source 10S portion is increased. Similarly, the number of contacts 51 on the source 20S side of each NMOS 20 is made smaller than the number of contacts 52 on the drain 20D side to increase the contact resistance component of the source 20S portion. Thereby, the parasitic resistances R3 and R4 can be easily added, and the latch-up can be accurately reduced.
[0031]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of such modifications include the following.
[0032]
(A) In the above embodiment, the parasitic resistances R3 and R4 are respectively formed on the sources 10S and 20S side of the PMOS 10 and the NMOS 20, but even if the parasitic resistance R3 or R4 is formed on either of them, the output terminal OUT Latch-up can be reduced depending on the polarity of the trigger voltage applied to.
[0033]
(B) In the above embodiment, the CMOS type integrated circuit formed on the N type substrate 1 has been described. However, the CMOS type integrated circuit formed on the P type substrate has the same operation as the above embodiment. The effect is obtained.
[0034]
【The invention's effect】
As described above in detail, according to the first and second inventions, the number of the plurality of contacts on the source side of the MOS transistor is smaller than the number of the plurality of contacts on the drain side. ) And a low voltage (VSS), a resistance component (resistance means) is added in series to the emitter portion of the bipolar transistor parasitically formed, and the resistance component (resistance means) of the bipolar transistor at the time of applying the trigger voltage is added. The transition to the ON state is suppressed, and the occurrence of latch-up can be accurately reduced with a simple structure.
[Brief description of the drawings]
FIG. 1 is a schematic layout diagram of a CMOS output circuit showing an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a conventional CMOS output circuit.
3 is a circuit diagram showing a connection relationship between a parasitic bipolar transistor and a resistor in the CMOS output circuit shown in FIG. 2;
FIG. 4 is a circuit diagram of a connection relationship between a parasitic bipolar transistor and a resistor in a CMOS output circuit showing the principle of the embodiment of the present invention.
[Explanation of symbols]
1 N-type substrate 2 P well 10 PMOS
10D, 20D Drain 10G, 20G Gate 10S, 20S Source 20 NMOS
T1, T3 PNP transistor T2, T4 NPN transistor R1, R3, R4 Parasitic resistance R2 N-type substrate resistance IN Input terminal OUT Output terminal VCC High level power supply VSS Low level power supply 41, 42, 51, 52 Contacts

Claims (2)

A CMOS output circuit that operates by being supplied with a high voltage and a low voltage,
A first N-channel MOS transistor having a first portion of a first gate, an N-type source, and an N-type first drain;
A second portion of the first gate electrically connected to the first portion of the first gate and extending in the same direction; an N-type common to the first N-channel MOS transistor A second N-channel MOS transistor having a source of N and an N-type second drain;
A first P-channel MOS transistor having a first portion of a second gate, a P-type source, and a P-type first drain;
A second portion of the second gate electrically connected to the first portion of the second gate and extending in the same direction; a P-type common to the first P-channel MOS transistor; A second P-channel MOS transistor having a source and a P-type second drain;
A resistance component added in series to the source of at least one of the first and second N-channel MOS transistors and the first and second P-channel MOS transistors, wherein the resistance component is: A CMOS output circuit, wherein the number of contacts with the source of the one MOS transistor is less than the number of contacts with the drain of the one MOS transistor. A CMOS output circuit that operates by being supplied with a high voltage and a low voltage,
A substrate having a main surface;
Connected to a first conductivity type source formed in a first region of the main surface of the substrate and supplied with either the high voltage or the low voltage, a first portion of a first gate, and an output terminal A first MOS transistor having a first drain of the first conductivity type,
The first conductivity type source and the first gate of the first gate formed in the first region of the main surface of the substrate and common to the first MOS transistor to which one of the high voltage or the low voltage is supplied. A second portion of the first gate that is electrically connected to the first portion and extends in the same direction; and a second drain of the first conductivity type connected to the output terminal. MOS transistors of
A second conductivity type source formed in a second region of the main surface of the substrate and supplied with the other of the higher voltage or the lower voltage; a first portion of a second gate; and the output terminal A third MOS transistor having a first drain of the second conductivity type connected thereto;
A source of the second conductivity type, which is formed in a second region of the main surface of the substrate and is supplied with the other of the high voltage or the low voltage, and a first of the second gate and the second gate. A second portion of the second gate electrically connected to the second portion and extending in the same direction, and a second drain of the second conductivity type connected to the output terminal. With a MOS transistor,
The number of contacts on the source side of any one of the first, second, third, or fourth MOS transistors is set to the number of contacts on the first drain side of the one MOS transistor. A CMOS output circuit comprising resistance means connected in series to the source of the one MOS transistor formed by reducing the number of the MOS transistors.

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