JP3744772B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a semiconductor element is formed on a silicon substrate and a semiconductor element is assembled using an extraction electrode provided on the silicon substrate.
[0002]
[Prior art]
In the assembly process of a conventional semiconductor device, a semiconductor chip diced and separated from a wafer is fixed to a lead frame, the semiconductor chip is sealed by a transfer mold using a mold and resin injection, and the lead frame is cut to obtain individual chips. A process of separating each semiconductor device is performed. In the semiconductor device obtained by this method, as shown in FIG. 11, the periphery of the semiconductor chip 1 is covered with the resin layer 2, and the lead terminals 3 for external connection are derived from the side portions of the resin layer 2. It becomes a structure (for example, JP-A No. 05-129473).
[0003]
This structure has limitations in reducing the external dimensions and mounting area due to the projecting of the lead terminals 3 outside the resin layer 2, the problem of the processing accuracy of the lead frame and the accuracy of alignment with the mold. It was visible.
[0004]
In recent years, a wafer scale CSP (chip size package) that can reduce the outer dimensions to a size that is the same as or close to the size of a semiconductor chip has begun to attract attention. Referring to FIG. 12A, the semiconductor wafer 11 is subjected to various pretreatments such as diffusion to form a large number of semiconductor chips 12, and the upper portion of the semiconductor wafer 11 as shown in FIG. As shown in FIG. 12C, the electrode 14 for external connection is led out on the surface of the resin layer 13, and then the semiconductor chip 11 is divided along the dicing line of the semiconductor wafer 11. It is a finished product. The resin layer 13 only covers the front surface (which may cover the back surface) of the semiconductor chip 12, and the silicon substrate is exposed on the side wall of the semiconductor chip 12. The electrode 14 is electrically connected to an integrated circuit network formed under the resin layer 13, and the semiconductor device can be mounted by adhering the electrode 14 to a conductive pattern formed on the mounting substrate. .
[0005]
Such a semiconductor device has the advantage that the mounting occupation area can be greatly reduced because the device package size is equivalent to the chip size of the semiconductor chip, and it is only necessary to adhere to the mounting substrate. Moreover, it has the advantage that the cost associated with the post-process can be greatly reduced. (For example, JP-A-9-64049)
Therefore, chips having a chip size less than 1 mm square are mounted as shown in FIGS. 13A, 13B, and 13C.
[0006]
In the figure, reference numeral 21 denotes an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are stacked so that the plate thickness is 250 to 350 μm and the mechanical strength in the manufacturing process can be maintained, and the long side X The short side has a rectangular shape of about 1.0 mm x 0.8 mm.
[0007]
On the surface of the insulating substrate 21, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by electrolytic plating, thereby forming island portions 22 and electrode portions 23a and 23b. . A semiconductor chip 25 is fixed on the island portion 22 by a conductive adhesive 24 such as an Ag paste.
[0008]
An aluminum electrode pad 26 is formed on the surface of the semiconductor chip 25, and the electrode pad 26 and the electrode portions 23 a and 23 b are electrically connected by a bonding wire 27. A 1st bond is made on the electrode pad 26 side, and a 2nd bond is made on the electrode portion 23 side. If it is a bipolar transistor, the electrode parts 23a and 23b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.
[0009]
On the back side of the insulating substrate 21, a first external connection electrode 28 and second external connection electrodes 29a and 29b are also formed of a gold plating layer. The insulating substrate 21 is formed with circular first via holes 30 and second via holes 31a and 31b penetrating therethrough, and the insides of the via holes 30, 31a and 31b are buried with a conductive material such as tungsten. As a material, it is embedded with a material excellent in electrical conductivity and thermal conductivity. Via the via holes 30, 31a and 31b, the island part 22 and the first external connection electrode 28 are electrically connected, and the electrode parts 23a and 23b and the second external connection electrodes 29a and 29b are electrically connected. The first external connection electrode 28 is, for example, a collector electrode, and the second external connection electrodes 29a, 29b are, for example, a base and an emitter electrode.
[0010]
The upper portion of the insulating substrate 21 is covered with a resin layer 32 that seals the semiconductor chip 25 and the bonding wires 27. The resin layer 32 constitutes the package outer shape together with the insulating substrate 21. 4 side surfaces of the package are formed by the cut surfaces of the resin layer 32 and the insulating substrate 21, the upper surface of the package is formed by the flattened surface of the resin layer 32, and the lower surface of the package is formed by the back surface side of the insulating substrate 21.
[0011]
[Problems to be solved by the invention]
However, there are various problems in the mounting structure shown in FIG. First, since an expensive substrate material such as ceramic or glass epoxy is used, and an expensive metal paste such as tungsten is used, it cannot be said to be a low-cost mounting structure. Second, in order to connect the electrodes on both sides and the like, a via hole penetrating the insulating substrate is indispensable, and this processing accuracy is limited to about 0.15 mm, which is an obstacle to further miniaturization. Thirdly, since the inside of the via hole is filled with a metal paste, workability is extremely poor, resulting in high costs. Fourthly, it is divided into a pre-process for forming a semiconductor chip and a post-process for assembling a semiconductor chip using an insulating substrate, and many problems such as a long lead time and a high manufacturing cost have occurred.
[0012]
[Means for Solving the Problems]
The present invention has been made in view of the various problems described above, and includes a step of forming a semiconductor element in a predetermined element formation region of a silicon substrate, and a step of being located outside the element formation region of the silicon substrate. Forming a trench groove in a portion to be an extraction electrode; forming an oxide film on at least a side surface and a bottom surface of the trench groove; and removing the oxide film on a bottom surface of the trench groove; and embedding in the trench groove Forming a lead electrode made of a conductive metal, electrically connecting the electrode of the semiconductor element and the lead electrode, coating the surface of the silicon substrate with an insulating resin, and silicon Removing the substrate from the back surface and exposing the back surface of the extraction electrode; and dicing the insulating resin into individual semiconductor elements. Characterized in that is constituted.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
A method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS.
[0014]
The present invention includes a step of forming a semiconductor element in a predetermined element formation region of a silicon substrate, a step of forming a trench groove in a portion to be a predetermined extraction electrode located outside the element formation region of the silicon substrate, Forming an oxide film on at least a side surface and a bottom surface of the trench groove, and then removing the oxide film on the bottom surface of the trench groove; and forming an extraction electrode made of a conductive metal embedded in the trench groove; Electrically connecting the electrode of the semiconductor element and the extraction electrode; covering the surface of the silicon substrate with an insulating resin; and removing the silicon substrate from the back surface to expose the back surface of the extraction electrode A step of forming a connection electrode in the element formation region exposed on the back surface of the silicon substrate and the extraction electrode, and the insulating property By dicing the fat and a step of separating the individual semiconductor elements.
[0015]
The first step of the present invention is to form a semiconductor element 410 in a predetermined element formation region 41 of the silicon substrate 40 as shown in FIG.
[0016]
In this step, a silicon substrate 40 having a thickness of about 400 μm is prepared, and an annular ring is formed in the element formation region 41 of the silicon substrate 40 so as to surround the base region 411, the emitter region 412 and the base region 411 using a known selective diffusion method. Region 413 is formed. The silicon substrate 40 is formed by stacking an N− type epitaxial layer on an N + type silicon substrate, and forms a P type base region 411, an N + type emitter region 412, and an N + type annular ring region 413. Here, an NPN type planar transistor is taken as an example, but a semiconductor element 410 such as a PNP type planar transistor or MOSFET may be formed.
[0017]
As shown in FIG. 2, the second step of the present invention is to form a trench groove 42 in a portion that will be located outside the element formation region 41 of the silicon substrate 40 and that will become the planned extraction electrode 44.
[0018]
In this step, a portion that is to be the lead-out electrode 44 located outside the element formation region 41 is exposed, the other portion is covered with a photoresist layer, and the surface of the silicon substrate 40 is selectively dry etched to have a thickness of about 100 μm. A trench 42 having a depth is formed. The planned extraction electrode 44 is formed with a trench groove 42 in a square shape with a side of 200 μm so that the bonding wire can be fixed. The semiconductor element 410 is covered and protected by an oxide film (not shown).
[0019]
The third step of the present invention is to remove the oxide film 43 on the bottom surface of the trench groove 42 after forming the oxide film 43 on at least the side surface and the bottom surface of the trench groove 42 as shown in FIGS. .
[0020]
In this step, a thick oxide film 43 having a thickness of about 5000 to 10,000 mm is formed on the entire surface of the silicon substrate 40 by low pressure CVD (FIG. 2). Therefore, the oxide film 43 is formed on the surface of the silicon substrate 41 and the side and bottom surfaces of the trench groove 42. Subsequently, the oxide film 43 is anisotropically dry etched to selectively remove the oxide film 43 on the surface of the silicon substrate 40 and the bottom surface of the trench groove 42 (FIG. 3). As a result, the oxide film 43 remains on the side surface of the trench groove 42.
[0021]
The fourth step of the present invention is to form an extraction electrode 44 made of a conductive metal embedded in the trench groove 42 as shown in FIG.
[0022]
In this step, at least the trench groove 42 is filled by electroplating a conductive metal such as copper or gold. After the conductive metal plating film is formed on the silicon substrate 40 including the trench groove 42, the conductive metal plating film is etched away by photoetching leaving the conductive metal plating film in the trench groove 42.
[0023]
The fifth step of the present invention is to electrically connect the electrode 45 of the semiconductor element 410 and the extraction electrode 44 as shown in FIG.
[0024]
In this step, the electrode pad 45 and the extraction electrode 44 of the semiconductor element 410 are connected to each other by a bonding wire 46 by ball bonding.
[0025]
The aluminum electrode pad 45 is formed on the surface of the semiconductor element 410 in the first step described above, and the electrode pad 45 and the extraction electrode 44 are electrically connected by the bonding wire 46. A 1st bond is made on the electrode pad 45 side, and a 2nd bond is made on the extraction electrode 44 side. If it is a bipolar transistor, the extraction electrode 44 corresponds to an emitter and a base, respectively, and if it is a power MOSFET, it corresponds to a source and a gate.
[0026]
The sixth step of the present invention is to coat the surface of the silicon substrate 40 including the semiconductor element 410 with an insulating resin 47 as shown in FIG.
[0027]
In this step, a predetermined amount of epoxy-based liquid resin is dropped (potted) from a dispenser (not shown) transferred above the silicon substrate 40, and all the semiconductor elements 410 are covered with the common resin layer 47. For example, CV576AN (manufactured by Matsushita Electric Works) was used as the liquid resin. Since the dropped liquid resin has a relatively high viscosity and surface tension, the surface is curved. In order to process the curved surface of the resin layer 47 into a flat surface, a method of pressing a flat molding member to process it into a flat surface before the resin is cured, and the dropped resin layer 47 at a number of 100 to 200 degrees A method of processing a curved surface to a flat surface by grinding the curved surface with, for example, a dicing blade after curing by heat treatment (curing) for a time is considered.
[0028]
The seventh step of the present invention is to remove the silicon substrate 40 from the back surface to expose the back surface of the extraction electrode 44 as shown in FIG.
[0029]
This step is a feature of the present invention, and the silicon substrate 40 is ground from the back surface. Since the silicon substrate 40 has a thickness of about 400 μm, most of the silicon substrate 40 is mechanically ground by back grinding, and the remaining 10 to 20 μm is chemically removed by spin etching to be ground to a thickness of about 100 μm. Since the surface of the silicon substrate 40 is covered with the resin layer 47, the silicon substrate 40 is not broken by the mechanical strength of the resin layer 47. As a result, the back surface of the extraction electrode 44 is exposed to the back surface side of the resin layer 47. At this time, the oxide film 43 functions as an electrical insulating material for the extraction electrode 44.
[0030]
The eighth step of the present invention is to form a connection electrode 48 in the element formation region 41 and the extraction electrode 44 exposed on the back surface of the silicon substrate 40 as shown in FIG.
[0031]
In this step, a protective film 48 such as a silicon oxide film, a silicon nitride film, PIX, or SOG is formed on the exposed back surface of the silicon substrate 40 by CVD or spin-on to cover the entire back surface of the silicon substrate 40. Subsequently, contact holes are formed on the element formation region 41 and the extraction electrode 44 by selective etching, and a conductive metal such as gold is deposited by sputtering or the like, and then etched into a desired shape to form the connection electrode 49. The connection electrode 49a is in ohmic contact with the element formation region 41 and functions as a collector electrode, and the connection electrode 49b functions as an emitter and a base electrode.
[0032]
The final step of the present invention is to divide the insulating resin 47 into individual semiconductor elements 410 as shown in FIG.
[0033]
In this step, the resin layer 47 and the silicon substrate 40 are cut for each semiconductor element 410 and separated into the respective semiconductor elements 410. A dicing apparatus is used for cutting, and the resin layer 47 and the silicon substrate 40 are simultaneously cut by the dicing blade 51 along the dicing line 50 indicated by a dotted line, thereby forming a semiconductor device divided for each semiconductor element 410. In the dicing process, a blue sheet (for example, a trade name: UV sheet, manufactured by Lintec Corporation) is pasted on the back side of the silicon substrate 40, and cutting is performed with a cutting depth such that the dicing blade reaches the surface of the blue sheet. .
[0034]
【The invention's effect】
As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size as compared with a semiconductor device using a lead frame. At this time, since the lead terminal does not protrude, the occupied area when mounted can be reduced, and high-density mounting can be realized.
[0035]
In addition, since the extraction electrode is formed directly on the silicon substrate on which the semiconductor element is formed,
There is no need to use a ceramic substrate as in the prior art, and it is not necessary to fix the semiconductor element to another mounting member, and the cost can be greatly reduced.
[0036]
Furthermore, the silicon substrate can be processed with existing equipment, and no new equipment is required. Since the silicon substrate can also be processed in the previous process, there is no subsequent process, and the lead time can be greatly shortened.
[0037]
Furthermore, since no via hole is required, the through-hole process can be completely eliminated, and the process can be greatly shortened.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining the present invention.
FIG. 2 is a cross-sectional view for explaining the present invention.
FIG. 3 is a cross-sectional view for explaining the present invention.
FIG. 4 is a cross-sectional view for explaining the present invention.
FIG. 5 is a cross-sectional view for explaining the present invention.
FIG. 6 is a cross-sectional view for explaining the present invention.
FIG. 7 is a cross-sectional view for explaining the present invention.
FIG. 8 is a cross-sectional view for explaining the present invention.
FIG. 9 is a cross-sectional view for explaining the present invention.
FIG. 10 is a plan view for explaining the present invention.
FIG. 11 is a cross-sectional view for explaining a conventional example.
FIG. 12 is a diagram for explaining a conventional example.
FIG. 13 is a diagram for explaining another conventional example.

Claims (5)

Forming a semiconductor element in a predetermined element formation region of the silicon substrate;
Forming a trench groove in a portion to be a predetermined extraction electrode located outside the element formation region of the silicon substrate;
Removing the oxide film on the bottom surface of the trench groove after forming an oxide film on at least the side surface and the bottom surface of the trench groove;
Forming an extraction electrode made of a conductive metal embedded in the trench groove;
Electrically connecting the electrode of the semiconductor element and the extraction electrode;
Coating the silicon substrate surface with an insulating resin;
Removing the silicon substrate from the back surface to expose the back surface of the extraction electrode;
And a step of dicing the insulating resin and separating the resin into individual semiconductor elements. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a connection electrode in the element formation region exposed on the back surface of the silicon substrate and the extraction electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive metal is formed by plating gold or copper. The method of manufacturing a semiconductor device according to claim 1, wherein the electrode of the semiconductor element and the extraction electrode are connected by a bonding wire. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon substrate is removed from the back surface by grinding.

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