JP3744880B2 - Memory access circuit - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a memory access circuit, and in particular, accesses a memory in response to a second clock faster than the first clock, for example, for writing / reading data burst-transferred in response to the first clock. The present invention relates to a memory access circuit.
[0002]
[Prior art]
An example of this type of memory access circuit is shown in FIG. In the circuit 1 shown in FIG. 5, a CPU (Central Processing Unit) 2 accesses an SDRAM (Synchronous Dynamic RAM) 4 via a memory controller 3. The operation clock frequency fc ′ of the CPU 2 is fc ′ = 64 [MHz], and the operation clock frequency fs ′ of the SDRAM 4 is 1.5 times the operation clock frequency fc ′ of the CPU 2, that is, fs ′ = 96 [MHz]. is there. As described above, the memory controller 3 includes the buffer 5 in order to enable data transfer based on the burst transfer method between the CPU 2 and the SDRAM 4 having different operation clock frequencies fc ′ and fs ′.
[0003]
That is, data transferred from one of the CPU 2 and the SDRAM 4 to the memory controller 3 is temporarily stored in the buffer 5 and then transferred to the other. At this time, burst transfer is performed between the CPU 2 and the memory controller 3 according to the operation clock frequency fc ′ of the CPU 2, and burst transfer is performed between the SDRAM 4 and the memory controller 3 according to the operation clock frequency fs ′ of the SDRAM 4. By interposing the buffer 5 in this way, burst transfer between the CPU 2 and the SDRAM 4 becomes possible regardless of the difference between the operation clock frequencies fc ′ and fs ′.
[0004]
If the buffer 5 is not provided, that is, if the data burst-transferred from one of the CPU 2 and the SDRAM 4 to the memory controller 3 is directly burst-transferred to the other, the following inconvenience occurs. For example, at the time of data writing (writing), as shown in FIG. 6A, the data (D0 to D4) to be written burst from the CPU 2 to the memory controller 3 in accordance with the operation clock frequency fc ′ of the CPU 2. Transferred. If the data transferred to the memory controller 3 is burst transferred from the memory controller 3 to the SDRAM 4 according to the operation clock frequency fs' of the SDRAM 4 as shown in FIG. 6B, the operation clock frequency fc of the CPU 2 is assumed. Due to the difference from ', some data (D1 and D3) are transferred redundantly. As a result, there is a difference between the address planned by the CPU 2 as the data write destination and the address where the data is actually written, and the access operation fails. The same applies to data reading (reading). Therefore, conventionally, by providing the buffer 5 as described above, burst transfer is appropriately performed between the CPU 2 and the SDRAM 4 having different operation clock frequencies fc ′ and fs ′.
[0005]
[Problems to be solved by the invention]
However, the above-described conventional technique has a problem that since the data to be transferred is once stored in the buffer 5, the transfer process of the data takes time, and the access operation of the entire memory access circuit 10 is delayed. .
[0006]
SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a memory access circuit that can perform burst transfer between memories having different operation clocks without providing a buffer.
[0007]
[Means for Solving the Problems]
The present invention provides a memory access circuit for accessing a memory in response to a second clock faster than the first clock for writing / reading data burst-transferred in response to the first clock. A fetching means for fetching a numerical value updated in response to the second clock, a comparing means for comparing two numeric values successively fetched by the fetching means, and a memory when the comparison result of the comparing means indicates coincidence A memory access circuit comprising disabling means for disabling the second clock supplied to the memory.
[0008]
[Action]
In the present invention, the capturing means captures the numerical value updated in response to the first clock in response to the second clock. Then, the comparison unit compares the two numerical values successively captured by the capture unit with each other. Here, when the comparison result of the comparison means indicates coincidence, the same data as the data already written in the memory is the current write target, or the same data as the data already read from the memory is the current read It will be the subject. In this case, since the disabling means disables the second clock, the same data is not written to the memory again, or the same data is not read from the memory again. On the other hand, when the comparison result of the comparison means indicates a mismatch, the data currently being written has not yet been written to the memory, or the data currently being read has not yet been read from the memory. It will be. In this case, since the second clock is not disabled by the disabling means, data is appropriately written or read in response to the second clock.
[0009]
The memory is preferably a clock synchronous memory having a clock enable terminal. In this case, the disabling unit disables the second clock by supplying a predetermined signal to the clock enable terminal.
[0010]
【The invention's effect】
According to the present invention, data transferred in response to the first clock is written to the memory in response to the second clock without being passed through the buffer, or is read from the memory. That is, burst transfer can be performed between memories having different operation clocks without providing a buffer.
[0011]
The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
[0012]
【Example】
Referring to FIG. 1, a memory access circuit 10 according to this embodiment is applied to a digital camera. CPU 12 executes various processes according to an operator's operation, SDRAM 14 as a main memory, and SDRAM 14 by CPU 12. A memory controller 16 for controlling the access of the first and second oscillation circuits 18 and 20. The CPU 12 and the memory controller 16 are integrally formed by an ASIC (Application Specified IC) 22. The ASIC 18 also includes an interface circuit 24 described later.
[0013]
The CPU 12 operates in synchronization with a clock signal having a frequency fc = 64 [MHz] oscillated from the oscillation circuit 18 (hereinafter referred to as CK64 signal), and the SDRAM 14 has a frequency fs = 96 oscillated from the oscillation circuit 20. It operates in synchronization with a clock signal of [MHz] (hereinafter referred to as CK96 signal). Thus, in order to enable data transfer based on the burst transfer method between the CPU 12 and the SDRAM 14 having different operation clock frequencies fc and fs, the memory controller 16 is configured as follows.
[0014]
That is, the memory controller 16 includes a control signal generation circuit 26, an address converter 28, an ACK (Acknowledge) signal generation circuit 30, a Ready signal generation circuit 32, a counter 34, a comparator 36, two flip-flops 38 and 40, CKE (Clock Enable ) Includes a signal generation circuit 42 and five flip-flop groups 44 to 52 each having a plurality of flip-flops (for the number of bits of data handled by the memory access circuit 10 of this embodiment). Of these, the Ready signal generation circuit 32, the counter 34, and the flip-flop groups 44 and 52 operate in synchronization with the CK64 signal, and the other circuits operate in synchronization with the CK96 signal.
[0015]
Here, when a control signal including a data write instruction or a data read instruction is output from the CPU 12, the control signal is input to the control signal generation circuit 26. At the same time, the CPU 12 outputs an address signal for designating a data write destination address or a read source address, and this address signal is input to the address converter 28. The control signal generation circuit 26 controls the output timing of the address converter 28 in response to the input of the control signal. As a result, the row address signal and the column address signal included in the address signal are output from the address converter 28 at appropriate timing and input to the SDRAM 14 via the address bus 60.
[0016]
The control signal generation circuit 26 also performs predetermined memory control such as a CS (Chip Select) signal, a RAS (Row Address Strobe) signal, a CAS (Column Address Strobe) signal, and a WE (Write Enable) signal based on the above-described control signal. Generate a signal. The generated memory control signal is input to the SDRAM 14 via the control bus 62.
[0017]
Further, the control signal generation circuit 26 controls the input / output switching operation of the interface circuit 24 in response to the input of the control signal from the CPU 12. As a result, when data is written, the output gate 24a constituting the interface circuit 24 is activated and the input gate 24b is disabled. On the other hand, when reading data, the output gate 24a is disabled and the input gate 24b is enabled.
[0018]
The control signal output from the CPU 12 is also input to the ACK signal generation circuit 30. In response to the input of the control signal, the ACK signal generation circuit 30 generates an active “L (low)” ACK signal for permitting the CPU 12 to access the SDRAM 14, and generates the generated ACK signal as a Ready signal. Input to the circuit 32.
[0019]
The Ready signal generation circuit 32 generates an active “H (High)” Ready signal in response to the input of the ACK signal, and inputs the generated Ready signal to the CPU 12. In response to the input of the Ready signal, the CPU 12 starts data transfer based on the burst transfer method.
[0020]
Further, the ACK signal described above is also input to the counter 34, and the counter 34 starts a counting operation in response to the input of the AKC signal. Specifically, the counter 34 repeatedly counts numerical values “1” and “2” alternately in synchronization with the rising edge of the CK64 signal. The counted CNT (Count) signal is input to the comparator 36 and the flip-flop 38.
[0021]
The flip-flop 38 generates a CNT ′ signal by capturing a numerical value (signal level) represented by the input CNT signal in synchronization with the rising edge of the CK96 signal, and generates the generated CNT ′ signal by the comparator 36 and the flip-flop 40. To enter. The flip-flop 40 generates a CNT "signal by capturing the numerical value represented by the input CNT 'signal in synchronization with the rising edge of the CK96 signal, and inputs the generated CNT" signal to the comparator 36. The CNT "signal is a signal delayed in phase by one cycle of the CK96 signal from the CNT 'signal.
[0022]
In addition to the CNT signal, the CNT ′ signal, and the CNT ”signal, the comparator 36 receives the above-described control signal from the CPU 12 and an ACK signal generation circuit 30 for activating the operation of the comparator 36. An L ″ CMPE (Comparator Enable) signal is input.
[0023]
The comparator 36 is instructed by the control signal from the CPU 12 to write data, and when the level of the CMPE signal is “L” level, the numerical value represented by the CNT signal and the numerical value represented by the CNT ′ signal Are output, and a COMP (Comparison) signal representing the comparison result is output. On the other hand, when the data reading is instructed by the control signal from the CPU 12 and the level of the CMPE signal is “L” level, the comparator 36 is represented by the numerical value represented by the CNT ′ signal and the CNT ”signal. Compared with the numerical value and outputs the COMP signal Note that when the comparison result by the comparator 36 indicates coincidence, the level of the COMP signal becomes “H” level, and when the comparison result indicates disagreement, the level of the COMP signal is When the CMPE signal level is “H” level, the operation of the comparator 36 is disabled and the COMP signal level is “L” level.
[0024]
The CKE signal generation circuit 42 includes an inverting circuit 70 and a flip-flop 72 as shown in FIG. The COMP signal input from the comparator 36 is subjected to level inversion processing in the inversion circuit 70 and then input to the flip-flop 72. The flip-flop 72 generates the CKE signal by capturing the level of the signal after the level inversion in synchronization with the CK96 signal. The generated CKE signal is input to the SDRAM 14 via the control bus 62. The CKE signal is used to temporarily disable the operation of the CK96 signal in the SDRAM 14 as will be described later.
[0025]
At the time of data writing, data WD (Write Data) to be written is output from the CPU 12. This data WD is input to the flip-flop group 44 in the memory controller 16, where phase delay processing for one cycle of the CK64 signal is performed, and then input to the flip-flop group 46. The flip-flop group 46 captures the value of the delayed data WD ′ input from the flip-flop group 44 (the signal level of each bit) in synchronization with the CK96 signal. The data WD "processed by the flip-flop group 46 is input to the flip-flop group 48, where phase delay processing for one cycle of the CK96 signal is performed, and then the interface circuit 24 (output gate 24a) and the data The data is input to the SDRAM 14 via the bus 64.
[0026]
On the other hand, when reading data, the data SD read from the SDRAM 14 is input to the flip-flop group 50 via the data bus 64 and the interface circuit 24 (input gate 24b). The flip-flop group 50 delays the phase of the input data SD by one cycle of the CK96 signal, and then inputs the delayed data SD ′ to the flip-flop group 52. The flip-flop group 52 takes in the value of the input data SD ′ in synchronization with the CK64 signal, and the data RD processed by the flip-flop group 52 is input to the CPU 12. Note that the Ready signal is supplied from the above-described Ready signal generation circuit 32 to the flip-flop group 52, and the flip-flop 52 outputs the data RD only when the level of the Ready signal is “H” level. .
[0027]
With reference to FIG. 3, the operation timing of each main part at the time of data writing will be described. When a control signal including a write instruction is output from the CPU 12, the level of the ACK signal shown in FIG. 3B is “H” at a certain time t1 in synchronization with the rising edge of the CK96 signal shown in FIG. It changes from “level” to “L” level. Then, after the level of this ACK signal becomes “L” level, the level of the Ready signal changes from “L” level to “H” level at the first rising time t2 of the CK64 signal shown in FIG. To do.
[0028]
At this time t2, the level of the Ready signal becomes “H” level, whereby the CPU 12 starts to transfer the data WD to be written shown in FIG. The data WD is continuously transferred by a predetermined amount (D0 to D7) in synchronization with the CK64 signal, that is, burst transferred. Although not shown in the figure, the address signal corresponding to the data WD is transferred from the CPU 12 to the memory controller 16 along with the transfer of the data WD.
[0029]
Further, at the time t2, the counting operation by the counter 34 is started. As a result, as shown in FIG. 3F, a CNT signal that repeatedly and alternately represents the values “1” and “2” is generated in synchronization with the rising edge of the CK64 signal. This CNT signal is processed by the flip-flop 38, thereby generating a CNT ′ signal as shown in FIG. That is, the CNT ′ signal is a signal obtained by capturing the value of the CNT signal updated in synchronization with the CK64 signal in synchronization with the CK96 signal, which is a signal having a frequency 1.5 times that of the CK64 signal. The value represented by the CNT ′ signal becomes the same value as the previous cycle every two cycles of the CK96 signal. Therefore, the value represented by the CNT ′ signal is repeatedly updated in the order of “1” → “1” → “2” in synchronization with the rising edge of the CK96 signal.
[0030]
At the third rising time t3 of the CK96 signal, counting from the time t1 when the level of the ACK signal becomes “L” level, the level of the CMPE signal shown in FIG. 3 (h) changes from “H” level to “L” level. Thus, the comparison operation by the comparator 36 is started. As described above, the comparator 36 compares the CNT signal and the CNT ′ signal at the time of data writing, and the comparison result COMP signal is a signal as shown in FIG. In FIG. 3, the rise or fall timing of the COMP signal coincides with the rise or fall timing of the CK96 signal. However, in actuality, the rise or fall timing of the COMP signal is CK96. The signal is delayed by a time corresponding to the processing speed of the comparator 36 from the rising or falling timing of the signal.
[0031]
This COMP signal is input to the CKE signal generation circuit 42, thereby generating a CKE signal as shown in FIG. Here, paying attention to the relationship between the CKE signal and the CNT ′ signal when the level of the CMPE signal is the “L” level, the value represented by the CNT ′ signal in a certain cycle of the CK96 signal is the value of the certain cycle. When the value represented by the CNT ′ signal is the same as the value represented by the CNT ′ signal in the previous cycle, that is, when the value represented by the CNT ′ signal is the same for two cycles of the CK96 signal, the level of the CKE signal is set to the “L” level. Become. This CKE signal is input to the SDRAM 14 via the control bus 62. Although not understood from FIG. 3, the rising or falling timing of the CKE signal is slightly delayed from the rising or falling timing of the CK96 signal.
[0032]
As described above, the SDRAM 14 operates in synchronization with the CK96 signal. However, when the level of the CKE signal is “L” level, the operation of the SDRAM 14 is disabled. Specifically, in the SDRAM 14, as shown in FIGS. 3J and 3K, when the level of the CKE signal is “L” level at the rising edge of the CK96 signal, the next CK96 is set. The rising edge of the signal (pulse indicated by dotted line 80) is masked. That is, in the SDRAM 14, the rising edge of the CK96 signal is masked every two cycles. Data is not written to the SDRAM 14 during this masked period.
[0033]
On the other hand, the data WD to be written is processed by the flip-flop group 44, thereby generating data WD ′ whose phase is delayed by one cycle of the CK64 signal as compared with the data WD as shown in FIG. . The data WD ′ is processed by the flip-flop group 46, thereby generating data WD ″ as shown in FIG. 3 (n). That is, the data WD ″ is updated in synchronization with the CK64 signal. Since the contents of WD ′ (D0 to D7) are data captured in synchronization with the CK96 signal which is a signal having a frequency 1.5 times that of the CK64 signal, the contents of the data WD ″ are two cycles of the CK96 signal. Every other content is the same as the previous period (D1, D3, D5 and D7).
[0034]
Since this data WD ″ is further subjected to the phase delay processing for one cycle of the CK96 signal by the flip-flop group 48, the data SD as shown in FIG. 3 (o) is input to the SDRAM 14. Since the data SD is input to the SDRAM 14 via the interface circuit 24 and the data bus 64, the timing of the data SD is correspondingly higher than the rising timing of the CK96 signal, as shown exaggeratedly in FIG. Be late.
[0035]
Thus, the content of the data SD input to the SDRAM 14 becomes the same content (D1, D3, D5 and D7) as the previous cycle every two cycles of the CK96 signal, but the operation of the CK96 signal is synchronized with this timing. Since only one period is disabled, the same contents are not written to the SDRAM 14 redundantly. Therefore, the data SD (D0 to D7) is appropriately written at the originally scheduled address.
[0036]
Note that at the time t4 when a predetermined amount of data WD is output from the CPU 12, the level of the Ready signal returns from the "H" level to the "L" level. Then, after one cycle of the CK64 signal from this time t4, at the first rising time t5 of the CK96 signal, the level of the ACK signal returns from the “L” level to the “H” level. At the same time, the level of the CMPE signal also changes from the “L” level to the “H” level. Then, at time t6 when the CK64 signal first rises after time t5, the counting operation by the counter 34 is stopped, and a series of writing operations is completed.
[0037]
Next, with reference to FIG. 4, the operation timing of each main part at the time of data reading will be described. When a control signal including a read instruction is output from the CPU 12, the level of the ACK signal shown in FIG. 4B is “H” at a certain time t11 in synchronization with the rising edge of the CK96 signal shown in FIG. It changes from “level” to “L” level. Although not shown in the figure, the CPU 12 outputs an address signal for designating an address of data to be read out together with the output of the control signal.
[0038]
After the level of the ACK signal becomes “L” level, the counting operation by the counter 34 is started at the rising edge t12 at the beginning of the CK64 signal shown in FIG. 4C, and as shown in FIG. In synchronization with the rising edge of the CK64 signal, a CNT signal that alternately represents the values “1” and “2” is generated. This CNT signal is processed by the flip-flop 38, whereby a CNT ′ signal similar to that shown in FIG. 3G is generated as shown in FIG. Further, this CNT ′ signal is processed by the flip-flop 40, thereby generating a CNT ”signal whose phase is delayed by one cycle of the CK96 signal from the CNT ′ signal, as shown in FIG. 4 (f).
[0039]
At the fifth rising time t13 of the CK96 signal, counting from the time t11 when the level of the ACK signal becomes the “L” level, the level of the CMPE signal changes from the “H” level to the “L” level. The comparison operation by 36 is started. As described above, since the comparator 36 compares the CNT ′ signal and the CNT ″ signal at the time of data reading, the COMP signal as a comparison result is a signal as shown in FIG.
[0040]
This COMP signal is input to the CKE signal generation circuit 42, whereby a CKE signal as shown in FIG. 4 (i) is generated. Here, paying attention to the relationship between the CKE signal and the CNT ”signal when the level of the CMPE signal is“ L ”level, the value represented by the CNT” signal in a certain cycle of the CK96 signal is the value of the certain cycle. When the value represented by the CNT "signal is the same as the value represented by the CNT" signal in the previous cycle, that is, when the value represented by the CNT "signal is the same over two cycles of the CK96 signal, the level of the CKE signal is set to the" L "level. Become. This CKE signal is input to the SDRAM 14 via the control bus 62.
[0041]
In the SDRAM 14, as shown by a dotted line 82 in FIG. 4J, the rising edge of the CK96 signal is masked at the next timing when the level of the CKE signal becomes “L” level. That is, the rising edge of the CK96 signal is masked every two cycles. The data SD read from the SDRAM 14 in synchronism with the rising edge of the CK96 signal is data as shown in FIG. That is, after one data D0 is read in synchronization with the rising edge of the CK96 signal, the next data D1 is continuously read over two cycles of the CK96 signal, and the subsequent data D2 to D7 have the same timing. Is read out. In FIG. 4 (k), data D8 to DB other than the read target are also read from the SDRAM 14, but these data D8 to DB are invalidated (by the flip-flop group 52) in the middle as will be described later. It is said.
[0042]
The data SD read from the SDRAM 14 is processed by the flip-flop group 50, thereby generating data SD ′ whose phase is delayed by one cycle of the CK96 signal from the data SD as shown in FIG. Is done. The data SD ′ is processed by the flip-flop group 52 to become data RD whose contents are updated in synchronization with the rising edge of the CK64 signal as shown in FIG. 4 (n). The data RD is transferred to the CPU 12.
[0043]
Note that the level of the Ready signal changes from the “L” level to the “H” level in accordance with the transfer start time t14 of the data RD. Specifically, the level of the Ready signal is changed from the “L” level at the first rising time t14 of the CK64 signal after eight cycles of the CK96 signal from the time t11 when the level of the ACK signal becomes the “L” level. Changes to “H” level. Then, at the time t15 when the reading of the data RD (D0 to D7) to be read is completed, the level of the Ready signal returns from the “H” level to the “L” level.
[0044]
The Ready signal is also input to the flip-flop group 52 as described above, and the operation of the flip-flop group 52 is validated only when the level of the Ready signal is “H” level. Therefore, the data D8 to DB other than the read target are disabled and are not transferred to the CPU 12.
[0045]
Further, at time t15, the level of the COMP signal also returns from the “L” level to the “H” level. Then, after this time t15, at the first rising time t16 of the CK96 signal, the level of the ACK signal returns from the “L” level to the “H” level, and after this time t16, at the first rising time t17 of the CK64 signal. Then, the counting operation by the counter 34 is stopped, and a series of reading operations is completed.
[0046]
As can be seen from the above description, in the memory controller 16, the counter 34 performs a counting operation in synchronization with the CK64 signal, and the count value by the counter 34 is taken in synchronization with the CK96 signal. When the fetched value becomes the same value continuously over two cycles of the CK96 signal, the data write operation to the SDRAM 14 or the data read operation from the SDRAM 14 is stopped. Therefore, the same data is not continuously written to the SDRAM 14 or the same data is not continuously read from the SDRAM 14, and an appropriate access operation can be realized. In addition, since the burst transfer between the CPU 12 and the SDRAM 14 is possible without the buffer 5 as in the prior art described above, an access operation faster than the conventional one can be realized.
[0047]
In this embodiment, the case where the present invention is applied to a digital camera has been described. Needless to say, the present invention can also be applied to electronic devices other than a digital camera.
[0048]
Further, the operation clock frequencies fc and fs of the CPU 12 and the SDRAM 14 are not limited to the values described in this embodiment.
[0049]
Further, although the CPU 12, the memory controller 16, and the interface circuit 24 are integrally formed by the ASIC 22, they may be individually configured.
[0050]
At the time of writing data from the CPU 12 to the SDRAM 14, the CKE signal is generated based on the comparison result between the CNT signal and the CNT ′ signal by the comparator 36. However, the present invention is not limited to this. For example, the CKE signal may be generated based on the comparison result of the CNT ′ signal and the CNT ″ signal at the time of data writing as well as at the time of data reading. And the CNT ′ signal may be generated based on the comparison result, and the CKE signal may be generated by a circuit configuration other than that described in this embodiment.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing details of a CKE signal generation circuit in FIG. 1;
FIG. 3 is a timing chart showing the operation of each main part at the time of data writing in the embodiment of FIG. 1;
4 is a timing chart showing the operation of each main part at the time of data reading in the embodiment of FIG.
FIG. 5 is a block diagram showing a configuration of a conventional memory access circuit.
6 is a timing diagram for explaining problems in the prior art of FIG.
[Explanation of symbols]
10: Memory access circuit
12 ... CPU
14 ... SDRAM
16 ... Memory controller
18, 20 ... oscillation circuit
34 ... Counter
36 ... Comparator
42 ... CKE generation circuit

Claims (2)

In a memory access circuit for accessing a memory in response to a second clock faster than the first clock for writing / reading data burst transferred in response to a first clock,
Capturing means for capturing a numerical value updated in response to the first clock in response to the second clock;
Comparing means for comparing two numerical values successively captured by the capturing means, and disabling means for disabling the second clock supplied to the memory when the comparison result of the comparing means indicates a match A memory access circuit comprising: The memory is a clock synchronous type memory having a clock enable terminal,
2. The memory access circuit according to claim 1, wherein the disabling unit disables the second clock by supplying a predetermined signal to the clock enable terminal.

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