JP3746147B2 - Clock gate circuit and clock gating circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock gate circuit and a clock gating circuit, and more particularly to a clock gate circuit and a clock gating circuit that can stop and restart the supply of a clock signal at an arbitrary timing.
[0002]
[Prior art]
The power consumption when the clock signal operates is large in the power consumption of the entire chip. For this reason, a technique for reducing power consumption by halving the apparent frequency of the clock signal by using both rising and falling edges of the clock signal is used. Furthermore, when there is a temporarily unused circuit block, a technique for reducing the power consumption of the entire chip by stopping the supply of a clock signal to the circuit block for an arbitrary cycle is also used. A circuit for temporarily stopping the supply of the clock in this way is called a clock gate circuit.
[0003]
A conventional clock gating circuit having a clock gate circuit CG and a flip-flop circuit FF is shown in FIG. As can be seen from FIG. 28, the conventional clock gate circuit CG includes an AND circuit AN. The AND circuit AN is supplied with an input clock signal CLK1 and an enable signal E for controlling the supply of the input clock signal CLK1. The output clock signal CLK0 of the AND circuit AN is input to the flip-flop circuit FF. That is, the input data signal Dn is input and the output data signal Qn is input to the flip-flop circuit FF. Therefore, the output clock signal CLK0 is supplied to the flip-flop circuit FF of FIG. 28 while the flip-flop circuit FF is used, and the output clock signal CLK0 is not supplied when the flip-flop circuit FF is not used.
[0004]
Next, based on FIG. 29, a flip-flop circuit that is synchronized only with the rising edge of the clock signal (hereinafter referred to as a single edge flip-flop circuit), and a flip-flop circuit that is synchronized with both the rising and falling edges of the clock signal. The operation with (hereinafter referred to as a double edge flip-flop circuit) will be described in comparison. FIG. 29 is a timing chart of both types of flip-flop circuits.
[0005]
As can be seen from FIG. 29, in the case of a single edge flip-flop circuit, if the clock signal input to this flip-flop circuit is CP1 and the input data signal is D1, the output data signal is Q1. On the other hand, in the case of a double edge flip-flop circuit, if the clock signal input to the flip-flop circuit is CP2 and the input data signal is D1, the output data signal is Q2. As can be seen from these, the double edge flip-flop circuit operates in the same manner as the single edge flip-flop circuit even when the frequency of the clock signal CP2 is half the clock frequency CP1 of the single edge flip-flop circuit. In this way, by using both the rising and falling edges of the clock signal, the frequency of the clock signal can be apparently halved while performing the same operation, thereby reducing the power consumption of the chip. .
[0006]
Next, the operation of the flip-flop circuit FF when the clock gate circuit CG shown in FIG. 28 is used will be described with reference to FIG. FIG. 30 is a timing chart of the clock gate circuit CG and the flip-flop FF.
[0007]
As can be seen from FIG. 30, in the case of a single edge flip-flop circuit, the output clock signal of the clock gate circuit CG is CLK01 when the input clock signal is CLK11 and the enable signal is E1. This output clock signal CLK01 is input to the single edge flip-flop circuit. Further, when the input data signal input to the flip-flop circuit is D1, the output data signal is Q11.
[0008]
On the other hand, in the case of the double edge flip-flop circuit, the output clock signal of the clock gate circuit CG is CLK02 when the input clock signal is CLK12 and the enable signal is E1. This output clock signal CLK02 is input to the double edge flip-flop circuit. Further, when the input data signal input to the flip-flop circuit is D1, the output data signal is Q21. In the case of FIG. 30, the output data signal Q22 of the double edge flip-flop circuit has the same operation as the output data signal Q11 of the single edge flip-flop circuit.
[0009]
As described above, the clock gate circuit CG temporarily stops the supply of the clock signal and restarts the supply of the stopped clock signal, and the stop period can be set in an arbitrary cycle. There must be. That is, it must be possible to stop and restart the clock signal at an arbitrary timing.
[0010]
[Problems to be solved by the invention]
The problems that occur in the conventional clock gate circuit CG will be described with reference to the timing chart shown in FIG. As can be seen from FIG. 31, in the case of a single edge flip-flop circuit, the output clock signal of the clock gate circuit CG is CLK01 when the input clock signal is CLK11 and the enable signal is E2. This output clock signal CLK01 is input to the single edge flip-flop circuit. Further, if the input data signal is D1, the output data signal is Q12.
[0011]
On the other hand, in the case of the double edge flip-flop circuit, the output clock signal of the clock gate circuit CG is CLK02 when the input clock signal is CLK12 and the enable signal is E2. This output clock signal CLK02 is input to the double edge flip-flop circuit. Further, when the input data signal is D1, the output data signal is Q22.
[0012]
As can be seen by comparing these output data signals Q12 and Q22, the output data signal Q22 of the double edge flip-flop circuit operates differently from the output data signal Q12 of the single edge flip-flop circuit. This is because extra edges EG and EG synchronized with the enable signal E2 are generated in the output clock signal CLK02 of the clock gate circuit CG. In such a case, there is a problem in that a double edge flip-flop circuit using both rising and falling edges of the clock signal causes a malfunction.
[0013]
Next, based on FIG. 32, the process in which such an extra edge EG occurs will be examined in detail. FIG. 32A shows the input clock signal CLK12 input to the clock gate circuit CG. Assume that an enable signal E is input as shown in FIG. 32B in a state where the input clock signal CLK12 is input. That is, assume that when the input clock signal CLK12 is high, the enable signal E becomes low and the clock supply is stopped, and when the input clock signal CLK12 is high, the enable signal E becomes high and the clock supply is resumed. In this case, two extra edges EG and EG appear in the output clock signal CLK02. Therefore, if this output clock signal CLK02 is input to the double edge flip-flop circuit, it may cause a malfunction.
[0014]
When the input clock signal CLK12 is input to the clock gate circuit CG as shown in FIG. 32A, it is assumed that the enable signal E as shown in FIG. 32C is input. That is, assume that when the input clock signal CLK12 is high, the enable signal E goes low and the clock supply is stopped, and when the input clock signal CLK12 is low, the enable signal E goes high and the clock supply is resumed. In this case, one extra edge EG appears in the output clock signal CLK02. Therefore, if this output clock signal CLK02 is input to the double edge flip-flop circuit, it may cause a malfunction.
[0015]
When the input clock signal CLK12 is input to the clock gate circuit CG as illustrated in FIG. 32A, it is assumed that the enable signal E illustrated in FIG. 32D is input. That is, assume that when the input clock signal CLK12 is low, the enable signal E is low and the clock supply is stopped, and when the input clock signal CLK12 is low, the enable signal E is high and the clock supply is resumed. In this case, no extra edge EG appears in the output clock signal CLK02. Therefore, even if this output clock signal CLK02 is input to the double edge flip-flop circuit, no malfunction occurs.
[0016]
As shown in FIG. 32A, when the input clock signal CLK12 is input to the clock gate circuit CG, it is assumed that the enable signal E as shown in FIG. 32E is input. That is, it is assumed that when the input clock signal CLK12 is low, the enable signal E becomes low and the clock supply is stopped, and when the input clock signal CLK12 is high, the enable signal E becomes high and the clock supply is resumed. In this case, one extra edge EG appears in the output clock signal CLK02. Therefore, if this output clock signal CLK02 is input to the double edge flip-flop circuit, it may cause a malfunction.
[0017]
As can be seen from the above, in order to avoid such a malfunction, the timing of the enable signal E has to be limited to a fixed case as shown in FIG. That is, when the clock gate circuit CG including the AND circuit AN as shown in FIG. 28 is used, the enable signal E is switched only when the input clock signal CLK12 is low as shown in FIG. Had to make a limit. That is, there is a problem that the clock signal cannot be gated at an arbitrary timing.
[0018]
[Means for Solving the Problems]
In order to solve the above problems, a clock gate circuit according to the present invention includes:
The input clock signal is supplied to the outside as an output clock signal, the supply of the output clock signal is stopped at an arbitrary timing, and the supply of the stopped output clock signal is restarted at an arbitrary timing. It can be a clock gate circuit,
During the period when the supply of the output clock signal is stopped, a hold circuit that holds the state of the output clock signal when the supply of the output clock signal is stopped and outputs the hold circuit;
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped matches the state of the input clock signal when the supply of the output clock signal is resumed. A buffer circuit that outputs the output clock signal to the outside in the same phase as the input clock signal, and outputs the output clock signal to the outside in a phase opposite to the input clock signal if they do not match,
It is characterized by providing.
[0019]
Further, the clock gate circuit according to the present invention includes:
While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing, A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during a period in which the supply of the output clock signal is stopped;
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the outside as the output clock signal; and
A control signal generation circuit that outputs to the buffer a control signal for controlling whether the buffer circuit outputs the input clock signal in the same phase or outputs it in the opposite phase; and
With
The control signal generation circuit includes:
During the period when the supply of the output clock signal is stopped, the number of edges of the input clock signal is counted during the period when the supply of the output clock signal is stopped,
When resuming the supply of the output clock signal,
When the counted number of edges is an even number, if the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is the same phase, the output of the input clock signal in the same phase The control signal to be output as a clock signal is output, and when the relationship between the input clock signal and the output clock signal at the time of stopping supply of the output clock signal is in reverse phase, the input clock signal is in reverse phase Output the control signal to be output as an output clock signal,
When the counted number of edges is an odd number, the input clock signal is in reverse phase when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in phase. The control signal to be output as an output clock signal is output, and when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in reverse phase, the input clock signal is in phase Outputting the control signal to be output as an output clock signal;
It is characterized by that.
A clock gate circuit according to the present invention includes:
While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing, A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during a period in which the supply of the output clock signal is stopped;
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the outside as the output clock signal; and
A control signal generation circuit that outputs to the buffer a control signal for controlling whether the buffer circuit outputs the input clock signal in the same phase or outputs it in the opposite phase; and
With
The control signal generation circuit includes:
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped and the state of the input clock signal when the supply of the output clock signal is resumed are: If they match, the control signal that outputs the output clock signal in the same phase as the input clock signal is output to the outside, and if they do not match, the output clock signal is out of phase with the input clock signal to the outside Outputting the control signal to be output;
It is characterized by that.
A clock gate circuit according to the present invention includes:
A buffer circuit that receives an input clock signal and a control signal and outputs an output clock signal;
A control signal generation circuit that receives the input clock signal, the output clock signal, and an enable signal and outputs the control signal to the buffer circuit;
With
The buffer circuit includes a first exclusive OR circuit and a first latch circuit,
The control signal generation circuit includes a second exclusive OR circuit and a second latch circuit,
The first exclusive OR circuit receives the input clock signal and the control signal from the second latch circuit, and outputs a first intermediate signal obtained by calculating an exclusive OR of these two signals.
The first latch circuit receives the first intermediate signal and the enable signal, and based on the state of the enable signal, outputs the output clock signal as the output signal as it is or holds the first intermediate signal,
The second exclusive OR circuit receives the output clock signal and the input clock signal, and outputs a second intermediate signal obtained by calculating an exclusive OR of these two signals.
The second intermediate circuit and the enable signal are input to the second latch circuit, and based on the state of the enable signal, the second intermediate signal is left as it is or is held and output as the control signal.
A clock gate circuit characterized by the above.
A clock gate circuit according to the present invention includes:
The input clock signal is supplied to the outside as an output clock signal, and the supply of the output clock signal is stopped at an arbitrary timing by switching the enable signal, and the supply of the stopped output clock signal is arbitrarily performed. A clock gate circuit that can be restarted at the timing,
The input clock signal and the enable signal are input, and during the clock supply stop period, the number of edges of the input clock signal is counted, and a first intermediate signal that is high or low depending on whether the number of edges is even or odd. A count circuit that maintains a high or low state when the clock supply is resumed and outputs it as a first intermediate signal during the clock supply period;
A first exclusive OR circuit that receives the first intermediate signal and the input clock signal and outputs a second intermediate signal obtained by performing an exclusive OR operation between the two signals;
The second intermediate signal and the enable signal are input, the second intermediate signal is directly output as an output clock signal during the clock supply period, and an output clock signal when the clock supply is stopped during the clock supply stop period. A latch circuit that holds and outputs the state;
It is provided with.
A clock gating circuit according to the present invention includes:
The input clock signal is supplied to the outside as an output clock signal, the supply of the output clock signal is stopped at an arbitrary timing, and the supply of the stopped output clock signal is restarted at an arbitrary timing. A clock gate circuit that can
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:
The clock gate circuit includes:
During the period when the supply of the output clock signal is stopped, a hold circuit that holds the state of the output clock signal when the supply of the output clock signal is stopped and outputs the hold circuit;
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped matches the state of the input clock signal when the supply of the output clock signal is resumed. A buffer circuit that outputs the output clock signal to the outside in the same phase as the input clock signal, and outputs the output clock signal to the outside in a phase opposite to the input clock signal if they do not match,
It is characterized by providing.
A clock gating circuit according to the present invention includes:
While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing, A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during the period in which the supply of the output clock signal is stopped;
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:
The clock gate circuit includes:
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the double edge flip-flop circuit as the output clock signal; and
A control signal generation circuit that outputs to the buffer circuit a control signal for controlling whether the buffer circuit outputs the input clock signal in phase or in phase, and
With
The control signal generation circuit includes:
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped and the state of the input clock signal when the supply of the output clock signal is resumed are: If they match, the control signal is output to the double edge flip-flop circuit while keeping the output clock signal in phase with the input clock signal, and if not, the output clock signal is inverted from the input clock signal. Outputting the control signal to be output to the double edge flip-flop circuit in a phase;
It is characterized by that.
A clock gating circuit according to the present invention includes:
While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing, A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during the period in which the supply of the output clock signal is stopped;
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:
The clock gate circuit includes:
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the double edge flip-flop circuit as the output clock signal; and
A control signal generation circuit that outputs to the buffer circuit a control signal for controlling whether the buffer circuit outputs the input clock signal in phase or in phase, and
With
The control signal generation circuit includes:
During the period when the supply of the output clock signal is stopped, the number of edges of the input clock signal is counted during the period when the supply of the output clock signal is stopped,
When resuming the supply of the output clock signal,
When the counted number of edges is an even number, if the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is the same phase, the output of the input clock signal in the same phase The control signal to be output as a clock signal is output, and when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is the reverse phase, the input clock signal Output the control signal to be output as an output clock signal,
When the counted number of edges is an odd number, the input clock signal is in reverse phase when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in phase. The control signal to be output as an output clock signal is output, and when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in reverse phase, the input clock signal is in phase Outputting the control signal to be output as an output clock signal;
It is characterized by that.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
The clock gate circuit according to the first embodiment of the present invention prevents an extra edge from being generated in the output clock signal when the supply of the output clock signal is stopped or when the supply of the output clock signal is resumed. Thus, the supply of the output clock signal can be stopped or restarted at an arbitrary timing. More details will be described below.
[0021]
FIG. 1 is a diagram showing a clock gating circuit according to an embodiment of the present invention. As can be seen from FIG. 1, this clock gating circuit includes a clock gate circuit CG and a flip-flop circuit FF.
[0022]
An input clock signal CLK1 and an enable signal E are input to the clock gate circuit CG. The clock gate circuit CG outputs an output clock signal CLK0. However, the supply of the output clock signal CLK0 can be stopped and restarted at an arbitrary timing. These supply stop timing and supply restart timing are determined based on the enable signal E.
[0023]
The clock gate circuit CG having such a function includes a hold circuit HL and a buffer circuit BF. The hold circuit HL is a circuit that holds the value of the output clock signal CLK0 when the supply of the output clock signal CLK0 is stopped. That is, when the supply of the output clock signal CLK0 is stopped, if the output clock signal CLK0 is high, this high state is maintained. If the output clock signal CLK0 is low when supply of the output clock signal CLK0 is stopped, this low state is maintained. That is, the hold circuit HL functions as a kind of memory circuit.
[0024]
The buffer circuit BF outputs an output clock signal CLK0 according to the state of the enable signal E. That is, when the enable signal E is in the clock supply state, the input clock signal CLK1 is output in the same phase or in the opposite phase and output as the output clock signal CLK0. When the enable signal E is in the clock stop state, the value of the hold circuit HL is output.
[0025]
When the enable signal E is in the clock supply state, whether the input clock signal CLK1 is output as the output clock signal CLK0 while being in phase, or whether the input clock signal CLK1 is inverted and output as the output clock signal CLK0 is as follows. It is decided like this. That is, depending on whether the state of the output clock signal CLK0 when the supply of the output clock signal CLK0 is stopped and the state of the input clock signal CLK1 when the supply of the output clock signal CLK0 is the same or different, Switch modes. Specifically, when the two match, the data is output in the same phase, and when the two are different, the data is output in the opposite phase.
[0026]
FIG. 2 is a timing chart showing the relationship among the input clock signal CLK1, the enable signal E, and the output clock signal CLK0.
[0027]
FIG. 2A shows the input clock signal CLK1 input to the clock gate circuit CG. Assume that the enable signal E is input as shown in FIG. 2B in a state where the input clock signal CLK1 is input. That is, the enable signal E goes low when the input clock signal CLK1 is in the high state to stop the clock supply, and the enable signal E goes high when the input clock signal CLK1 is in the high state at time t4. Assume that clock supply is resumed. In this case, the output clock signal CLK0 is maintained in the high state from time t1 to time t4. Since the input clock signal CLK1 is also in the high state at time t4, the output clock signal CLK0 is output in phase with the input clock signal CLK1 even after time t4.
[0028]
Assume that the enable signal E is input as illustrated in FIG. 2C in a state where the input clock signal CLK1 as illustrated in FIG. 2A is input to the clock gate circuit CG. That is, the enable signal E goes low when the input clock signal CLK1 is in the high state to stop the clock supply, and the enable signal E goes high when the input clock signal CLK1 is in the low state at time t3. Assume that clock supply is resumed. In this case, the output clock signal CLK0 is maintained in the high state from time t1 to time t3. Since the input clock signal CLK1 is in the low state at time t3, the output clock signal CLK0 is output in phase opposite to that of the input clock signal CLK1 after time t3.
[0029]
Assume that the enable signal E is input as illustrated in FIG. 2D in a state where the input clock signal CLK1 as illustrated in FIG. 2A is input to the clock gate circuit CG. That is, the enable signal E goes low at time t2 when the input clock signal CLK1 is in the low state and the clock supply is stopped, and the enable signal E goes high at time t5 when the input clock signal CLK1 is in the low state. Assume that clock supply is resumed. In this case, the output clock signal CLK0 is maintained in the low state from time t2 to time t5. Since the input clock signal CLK1 is also in the low state at time t5, the output clock signal CLK0 is output in phase with the input clock signal CLK1 after time t5.
[0030]
Assume that the enable signal E is input as illustrated in FIG. 2E in a state where the input clock signal CLK1 as illustrated in FIG. 2A is input to the clock gate circuit CG. That is, the enable signal E goes low at time t2 when the input clock signal CLK1 is in the low state and the clock supply is stopped, and the enable signal E goes high at time t4 when the input clock signal CLK1 is in the high state. Assume that clock supply is resumed. In this case, the output clock signal CLK0 is maintained in the low state from time t2 to time t4. Since the input clock signal CLK1 is in the high state at time t4, the output clock signal CLK0 is output in reverse phase to the input clock signal CLK1 after time t4.
[0031]
The above operations are summarized in a table as shown in FIG. As can be seen from FIG. 3, when the state of the output clock signal CLK0 when the clock gate circuit CG stops supplying the clock and the state of the input clock signal CLK1 when restarting the clock supply match, An output clock signal CLK0 having the same phase as the input clock signal CLK1 is output. On the other hand, if the state of the output clock signal CLK0 when the clock gate circuit CG stops supplying the clock and the state of the input clock signal CLK1 when starting the clock supply are different, the input clock signal CLK1 An output clock signal CLK0 is output.
[0032]
As described above, according to the clock gate circuit CG according to the present embodiment, even if the supply of the clock signal is stopped or restarted at an arbitrary timing, no extra edge is generated in the output clock signal CLK0. It is possible to prevent malfunction of the double etching flip-flop circuit. That is, when the clock supply is stopped, the state of the output clock signal CLK0 at that time is held until the clock supply is started again. For this reason, it is possible to avoid the occurrence of an extra edge in the output clock signal CLK0 when the clock supply is stopped. Furthermore, when the clock supply is started, the output mode is changed depending on whether or not the state of the output clock signal CLK0 when the clock supply is stopped and the state of the input clock signal CLK1 when the clock supply is started match. did. That is, when the two match, the input clock signal CLK1 is output as the output clock signal CLK0 in the same phase, and when the two do not match, the input clock signal CLK1 is inverted and output as the output clock signal CLK0. For this reason, it is possible to avoid occurrence of an extra edge in the output clock signal CLK0 even when the clock supply is resumed.
[0033]
Even if the supply of the clock is stopped or restarted at an arbitrary timing as described above, no extra edge is generated in the output clock signal CLK0. Therefore, as shown in FIG. 1, when the clock is supplied to the double edge flip-flop circuit, This malfunction of the flip-flop circuit FF can be avoided. In addition, since the clock supply can be stopped or restarted at an arbitrary timing in this way, the degree of freedom of design when using this clock gating circuit is increased and the power consumption can be suppressed.
[0034]
(Second Embodiment)
The second embodiment is a modification of the first embodiment, and the input clock signal is inverted at the start of clock supply depending on whether the clock supply is stopped even number of times or odd number of times. Or to determine whether the input clock signal is to be the output clock signal in phase.
[0035]
FIG. 4 is a block diagram of the clock gate circuit CG according to the second embodiment. As can be seen from FIG. 4, the clock gate circuit CG includes a buffer circuit BF and a control signal generation circuit CL.
[0036]
An input clock signal CLK1 from the outside and a control signal CTR from the control signal generation circuit CL are input to the buffer circuit BF. Then, the output clock signal CLK0 is output to the outside. The buffer circuit BF is a circuit that receives the state of the control signal CTR when supplying a clock signal, and outputs the output clock signal CLK0 in phase or in phase with the input clock signal CLK1.
[0037]
An input clock signal CLK1, an output clock signal CLK0, and an enable signal E are input to the control signal generation circuit CL. Then, the control signal CTR is output to the buffer circuit BF. The control signal generation circuit CL holds the output clock signal CLK0 when the clock supply is stopped. Further, the control signal generation circuit CL determines the buffer circuit BF depending on the state of the output clock signal CLK0 when the clock supply is stopped and the number of edges of the input clock signal CLK1 while the clock supply is stopped. A control signal CTR for controlling the output mode is generated. That is, when the number of edges of the input clock signal CLK1 during the clock supply stop period is an even number, the control signal for outputting the output clock signal CLK0 in the same manner as before the clock supply stop after restarting the clock supply Generate CTR. That is, the control signal CTR is generated so as to output the output clock signal CLK0 in the same phase when the clock supply is stopped and in the opposite phase when the clock supply is stopped. On the other hand, when the number of edges of the input clock signal CLK1 during the clock supply stop period is an odd number, the output clock signal CLK0 is output in a manner opposite to that before the clock supply stop after restarting the clock supply. Control signal CTR is generated. That is, the control signal CTR is generated so as to output the output clock signal CLK0 in the reverse phase when the clock supply is stopped and in the opposite phase when the clock supply is stopped.
[0038]
FIG. 5 is a diagram showing an example of the circuit configuration of the clock gate circuit CG shown in FIG. As can be seen from FIG. 5A, the buffer circuit BF includes switches S <b> 1 and S <b> 2, a non-inverting output circuit 10, and an inverting output circuit 12. Among these, the switches S1 and S2 are connected in parallel to each other and controlled by the control signal CTR. More specifically, the switch S1 is a switch that is turned on when the clock is supplied and the control signal CTR is low. In other cases, the switch S1 is off. That is, when the clock is stopped or when the control signal CTR is high even in the clock supply state, the signal is off. The switch S2 is a switch that is turned on when the clock is supplied and the control signal CTR is high. In other cases, the switch S1 is off. That is, it is off when the clock is in a stopped state or when the control signal CTR is low even in the clock supply state.
[0039]
The non-inverting output circuit 10 is connected in series with the switch S1. The inverting output circuit 12 is connected in series with the switch S2. The non-inverting output circuit 10 is a circuit that outputs the input clock signal CLK1 as it is. The inverting output circuit 12 is a circuit that inverts and outputs the input clock signal CLK1 inputted.
[0040]
The control signal generation circuit CL includes latch circuits LAT1 and LAT2, switches S3 and S4, a non-inverting output circuit 14, and an inverting output circuit 16. While the clock supply is stopped, the latch circuit LAT1 stores and holds the state of the output clock signal CLK0 when the clock supply is stopped, and outputs it as the signal D1. On the other hand, while the clock is supplied, the output clock signal CLK0 is output as the signal D1.
[0041]
The switch S3 is a switch that is turned on when the signal D1 is low and turned off when the signal D1 is high. The switch S4 is a switch that is turned on when the signal D1 is high and turned off when the signal D1 is low.
[0042]
The non-inverting output circuit 14 is connected in series with the switch S3. The inverting output circuit 16 is connected in series with the switch S4. The non-inverting output circuit 14 is a circuit that outputs the input clock signal CLK1 as it is as the signal D2. The inverting output circuit 16 is a circuit that inverts the input clock signal CLK1 and outputs it as a signal D2. The signal D2 output from the non-inverting output circuit 14 and the inverting output circuit 16 is input to the latch circuit LAT2.
[0043]
When the latch circuit LAT2 is in the clock supply state, the latch circuit LAT2 holds the state of the signal D2 when the clock supply is resumed and outputs it as the control signal CTR. On the other hand, when the clock supply is stopped, the signal D2 is output as it is as the control signal CTR.
[0044]
The latch circuits LAT1 and LAT2 described above are configured as shown in FIG. 5B, for example. In the latch circuit shown in FIG. 5B, during the clock supply stop period, that is, during the period when the enable signal E is low, the clocked inverter in the latch circuit is turned on. , Is to be held during that period.
[0045]
Next, the operation of the clock gate circuit CG shown in FIG. 5 will be described in detail based on the timing charts shown in FIGS.
[0046]
FIG. 6 shows a timing chart when the control signal CTR is low when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is restarted when the input clock signal CLK1 is high. FIG. As can be seen from FIG. 6, the control signal CTR is low before the clock supply is stopped, that is, before the time t1. For this reason, the switch S1 is in an on state. Therefore, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0047]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at time t1 is high, the output clock signal CLK0 is held in a high state, and the output signal D1 of the latch circuit LAT1 is also held in a high state. Since the signal D1 is high, the switch S4 is turned on. Therefore, the signal D2 obtained by inverting the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR obtained by inverting the input clock signal CLK1 is output from the latch circuit LAT2.
[0048]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. Therefore, the control signal CTR is low. When the control signal CTR is low, the switch S1 is turned on. Therefore, the output clock signal CLK0 is output in phase with the input clock signal CLK1. Further, since the enable signal E is high after the time t2, the control signal CTR holds the low state at the time t2. Therefore, after time t2, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0049]
FIG. 7 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is resumed when the input clock signal CLK1 is high. FIG. As can be seen from FIG. 7, the control signal CTR is high before the clock supply is stopped, that is, before the time t1. For this reason, the switch S2 is in an on state. Therefore, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0050]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held in the low state, and the output signal D1 of the latch circuit LAT1 is also held in the low state. Since the signal D1 is low, the switch S3 is turned on. Therefore, the signal D2 that remains in phase with the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR having the same phase as that of the input clock signal CLK1 is output from the latch circuit LAT2.
[0051]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. Therefore, the control signal CTR is also high. When the control signal CTR is high, the switch S2 is turned on. Therefore, the output clock signal CLK0 is output as a reverse phase of the input clock signal CLK1. Further, since the enable signal E is high after time t2, the control signal CTR maintains the high state at time t2. Therefore, after time t2, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0052]
FIG. 8 shows a timing chart when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is restarted when the input clock signal CLK1 is low, and the initial state of the control signal CTR is low. FIG. As can be seen from FIG. 8, the control signal CTR is low before the clock supply is stopped, that is, before the time t1. For this reason, the switch S1 is in an on state. Therefore, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0053]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at time t1 is high, the output clock signal CLK0 is held in a high state, and the output signal D1 of the latch circuit LAT1 is also held in a high state. Since the signal D1 is high, the switch S4 is turned on. Therefore, the signal D2 obtained by inverting the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR obtained by inverting the input clock signal CLK1 is output from the latch circuit LAT2.
[0054]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. Therefore, the control signal CTR is high. When the control signal CTR is high, the switch S2 is turned on. Therefore, the output clock signal CLK0 is output by inverting the input clock signal CLK1. Further, since the enable signal E is high after time t2, the control signal CTR maintains the high state at time t2. Therefore, after time t2, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0055]
FIG. 9 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is resumed when the input clock signal CLK1 is low. FIG. As can be seen from FIG. 9, the control signal CTR is high before the clock supply is stopped, that is, before the time t1. For this reason, the switch S2 is in an on state. Therefore, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0056]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held in the low state, and the output signal D1 of the latch circuit LAT1 is also held in the low state. Since the signal D1 is low, the switch S3 is turned on. Therefore, the signal D2 that remains in phase with the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR having the same phase as that of the input clock signal CLK1 is output from the latch circuit LAT2.
[0057]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. Therefore, the control signal CTR is also low. When the control signal CTR is low, the switch S1 is turned on. For this reason, the output clock signal CLK0 is output in phase with the input clock signal CLK1. Further, since the enable signal E is high after the time t2, the control signal CTR holds the low state at the time t2. Therefore, after time t2, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0058]
FIG. 10 shows a timing chart when the initial state of the control signal CTR is low when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is low. FIG. As can be seen from FIG. 10, the control signal CTR is low before the clock supply is stopped, that is, before the time t1. For this reason, the switch S1 is in an on state. Therefore, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0059]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held in the low state, and the output signal D1 of the latch circuit LAT1 is also held in the low state. Since the signal D1 is low, the switch S3 is turned on. Therefore, the signal D2 having the same phase as the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR having the same phase as that of the input clock signal CLK1 is output from the latch circuit LAT2.
[0060]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. Therefore, the control signal CTR is low. When the control signal CTR is low, the switch S1 is turned on. Therefore, the output clock signal CLK0 is output in phase with the input clock signal CLK1. Further, since the enable signal E is high after the time t2, the control signal CTR holds the low state at the time t2. Therefore, after time t2, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0061]
FIG. 11 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is low. FIG. As can be seen from FIG. 11, the control signal CTR is high before the clock supply is stopped, that is, before the time t1. For this reason, the switch S2 is in an on state. Therefore, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0062]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at time t1 is high, the output clock signal CLK0 is held in a high state, and the output signal D1 of the latch circuit LAT1 is also held in a high state. Since the signal D1 is high, the switch S4 is turned on. Therefore, a signal D2 having a phase opposite to that of the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR having a phase opposite to that of the input clock signal CLK1 is output from the latch circuit LAT2.
[0063]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. Therefore, the control signal CTR is high. When the control signal CTR is high, the switch S2 is turned on. Therefore, the output clock signal CLK0 is output as a reverse phase of the input clock signal CLK1. Further, since the enable signal E is high after time t2, the control signal CTR maintains the high state at time t2. Therefore, after time t2, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0064]
FIG. 12 is a timing chart when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is high, and the initial state of the control signal CTR is low. FIG. As can be seen from FIG. 12, the control signal CTR is low before the clock supply is stopped, that is, before the time t1. For this reason, the switch S1 is in an on state. Therefore, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0065]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held in the low state, and the output signal D1 of the latch circuit LAT1 is also held in the low state. Since the signal D1 is low, the switch S3 is turned on. Therefore, the signal D2 having the same phase as the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR having the same phase as that of the input clock signal CLK1 is output from the latch circuit LAT2.
[0066]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. Therefore, the control signal CTR is also high. When the control signal CTR is high, the switch S2 is turned on. Therefore, the output clock signal CLK0 is output in a phase opposite to that of the input clock signal CLK1. Further, since the enable signal E is high after time t2, the control signal CTR maintains the high state at time t2. Therefore, after time t2, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0067]
FIG. 13 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is high. FIG. As can be seen from FIG. 13, the control signal CTR is high before the clock supply is stopped, that is, before time t1. For this reason, the switch S2 is in an on state. Therefore, the output clock signal CLK0 is output in the opposite phase to the input clock signal CLK1.
[0068]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at time t1 is high, the output clock signal CLK0 is held in a high state, and the output signal D1 of the latch circuit LAT1 is also held in a high state. Since the signal D1 is high, the switch S4 is turned on. Therefore, a signal D2 having a phase opposite to that of the input clock signal CLK1 is supplied to the latch circuit LAT2. After time t1, a control signal CTR having a phase opposite to that of the input clock signal CLK1 is output from the latch circuit LAT2.
[0069]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. Therefore, the control signal CTR is low. When the control signal CTR is low, the switch S1 is turned on. For this reason, the output clock signal CLK0 is output in phase with the input clock signal CLK1. Further, since the enable signal E is high after the time t2, the control signal CTR holds the low state at the time t2. Therefore, after time t2, the output clock signal CLK0 is output in phase with the input clock signal CLK1.
[0070]
As can be seen from FIGS. 6 to 13, when the enable signal E falls, the clock gate circuit CG holds the state of the output clock signal CLK0 when the enable signal E falls. Then, the relationship between the in-phase / anti-phase when the enable signal E falls and the relationship between the in-phase / anti-phase when the enable signal E rises are summarized as shown in FIG.
[0071]
As can be seen from FIG. 14, when the input clock signal CLK1 and the output clock signal CLK0 are in phase when the enable signal E falls, the edge of the input clock signal CLK1 while the enable signal E is low. When the number is even, the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E rises is also in phase (see FIGS. 6 and 10). That is, when the input clock signal CLK1 is switched between low and high during the clock supply stop period, the output clock signal CLK1 is output in the same phase. This applies similarly when the initial state is in reverse phase. That is, when the input clock signal CLK1 and the output clock signal CLK0 are in reverse phase when the enable signal E falls, and the number of edges of the input clock signal CLK1 is an even number while the enable signal E is low. When the enable signal E rises, the input clock signal CLK1 and the output clock signal CLK0 are in opposite phases (see FIGS. 7 and 11). That is, when the number of edges of the input clock signal CLK1 during the clock supply stop period is an even number, the relationship between the input clock signal CLK1 and the output clock signal CLK0 is as follows before the clock supply stop and after the clock supply restart. It turns out that it is immutable.
[0072]
Further, as can be seen from FIG. 14, when the input clock signal CLK1 when the enable signal E falls and the output clock signal CLK0 are in phase, the input clock signal CLK1 while the enable signal E is low. When the number of edges is an odd number, the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E rises is reversed (see FIGS. 8 and 12). That is, when the input clock signal CLK1 is switched between low and high during the clock supply stop period an odd number of times, the output clock signal CLK1 is output with the in-phase changed to the opposite phase. On the other hand, when the initial state is the reverse phase, the phase is switched to the same phase. That is, when the input clock signal CLK1 and the output clock signal CLK0 are in reverse phase when the enable signal E falls, and the edge of the input clock signal CLK1 is odd while the enable signal E is low, When the enable signal E rises, the input clock signal CLK1 and the output clock signal CLK0 are in phase (see FIGS. 9 and 13). That is, when the number of edges of the input clock signal CLK1 during the clock supply stop period is an odd number, the relationship between the input clock signal CLK1 and the output clock signal CLK0 is as follows before the clock supply stop and after the clock supply restart. I can see that they are different.
[0073]
As described above, even if the clock gate circuit CG according to the second embodiment also stops or restarts the supply of the clock signal at an arbitrary timing as in the first embodiment, an extra edge is added to the output clock signal CLK0. Therefore, it is possible to prevent the double edge flip-flop circuit from malfunctioning.
[0074]
(Third embodiment)
As in the second embodiment, the third embodiment specifically shows a modification of the clock gate circuit according to the present invention.
[0075]
FIG. 15 is a diagram showing a clock gate circuit CG according to the third embodiment. As can be seen from FIG. 15, the clock gate circuit CG includes a buffer circuit BF and a control signal generation circuit CL.
[0076]
The buffer circuit BF includes an exclusive OR circuit EXO1 and a latch circuit LAT3. An input clock signal CLK1 from the outside and a control signal CTR from the control signal generation circuit CL are input to the exclusive OR circuit EXO1. Then, a signal D3 obtained by calculating an exclusive OR of the input clock signal CLK1 and the control signal CTR is output. That is, the exclusive OR circuit EXO1 is a circuit that outputs the input clock signal CLK1 as the signal D3 in phase or in phase with the control signal CTR. This signal D3 and the enable signal E are input to the latch circuit LAT3. Then, the output clock signal CLK0 is output. That is, the latch circuit LAT3 is a circuit that outputs the signal D3 as it is or holds and outputs the output clock signal CLK0 depending on the state of the enable signal E.
[0077]
The control signal generation circuit CL includes an exclusive OR circuit EXO2 and a latch circuit LAT4. An output clock signal CLK0 and an input clock signal CLK1 are input to the exclusive OR circuit EXO2. Then, a signal D4 obtained by calculating an exclusive OR between the output clock signal CLK0 and the input clock signal CLK1 is output. That is, the exclusive OR circuit EXO2 is a circuit that outputs a different signal D4 depending on whether or not the state of the input clock signal CLK1 and the state of the output clock signal CLK0 match. The latch circuit LAT4 receives the signal D4 and the enable signal E. Then, as described above, the control signal CTR is output to the exclusive OR circuit EXO1 of the buffer circuit BF. That is, the latch circuit 4 is a circuit that outputs the signal D4 as it is as the control signal CTR depending on the state of the enable signal E, or outputs the control signal CTR while maintaining the state of the signal D4.
[0078]
Next, the operation of the clock gate circuit CG shown in FIG. 15 will be described in detail based on the timing charts shown in FIGS.
[0079]
FIG. 16 shows a timing chart when the control signal CTR is low when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is restarted when the input clock signal CLK1 is high. FIG. As can be seen from FIG. 16, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in phase. For this reason, the signal D4 is low, and the control signal CTR is also low.
[0080]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is high, the output clock signal CLK0 is held in the high state by the latch circuit LAT3. The output clock signal CLK0 in the high state is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal having a phase opposite to that of the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1. That is, when the enable signal E rises, when the control signal CTR is low, the output is in-phase, and when the control signal CTR is high, the output is opposite phase.
[0081]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. The control signal CTR is low because it is opposite in phase to the input clock signal CLK1. The fact that the control signal CTR is low means that the output of the exclusive OR circuit EXO1 is in phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having the same phase as the input clock signal CLK1. Further, the low state of the control signal CTR of the latch circuit LAT4 at the time t2 is maintained after the time t2. That is, the state of the control signal CTR when the enable signal E rises is held. Therefore, the signal D3 having the same phase as the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, the latch circuit LAT3 outputs the output clock signal CLK0 having the same phase as the input clock signal CLK1.
[0082]
FIG. 17 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is resumed when the input clock signal CLK1 is high. FIG. As can be seen from FIG. 17, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in opposite phases. Therefore, the signal D4 is high and the control signal CTR is also high.
[0083]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held low by the latch circuit LAT3. This low state output clock signal CLK0 is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal in phase with the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0084]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. Since the control signal CTR is in phase with the input clock signal CLK1, it is high. When the control signal CTR is high, the output of the exclusive OR circuit EXO1 is in reverse phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having a phase opposite to that of the input clock signal CLK1. Further, the high state of the control signal CTR of the latch circuit LAT4 at time t2 is maintained after time t2. That is, the state of the control signal CTR when the enable signal E rises is held. For this reason, the signal D3 having a phase opposite to that of the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, an output clock signal CLK0 having a phase opposite to that of the input clock signal CLK1 is output from the latch circuit LAT3.
[0085]
FIG. 18 shows a timing chart when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is restarted when the input clock signal CLK1 is low, and the initial state of the control signal CTR is low. FIG. As can be seen from FIG. 18, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in phase. For this reason, the signal D4 is low, and the control signal CTR is also low.
[0086]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is high, the output clock signal CLK0 is held in the high state by the latch circuit LAT3. The output clock signal CLK0 in the high state is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal having a phase opposite to that of the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0087]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. The control signal CTR is high because it is opposite in phase to the input clock signal CLK1. When the control signal CTR is high, the output of the exclusive OR circuit EXO1 is in reverse phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having a phase opposite to that of the input clock signal CLK1. Further, the high state of the control signal CTR of the latch circuit LAT4 at time t2 is maintained after time t2. That is, the state of the control signal CTR when the enable signal E rises is held. For this reason, the signal D3 having a phase opposite to that of the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, an output clock signal CLK0 having a phase opposite to that of the input clock signal CLK1 is output from the latch circuit LAT3.
[0088]
FIG. 19 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is high and the clock supply is restarted when the input clock signal CLK1 is low. FIG. As can be seen from FIG. 19, before the clock supply is stopped, that is, before the time t1, the input clock signal CLK1 and the output clock signal CLK0 are in opposite phases. Therefore, the signal D4 is high and the control signal CTR is also high.
[0089]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held low by the latch circuit LAT3. This low state output clock signal CLK0 is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal in phase with the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0090]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. Since the control signal CTR is in phase with the input clock signal CLK1, it is low. The fact that the control signal CTR is low means that the output of the exclusive OR circuit EXO1 is in phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having the same phase as the input clock signal CLK1. Further, the low state of the control signal CTR of the latch circuit LAT4 at the time t2 is maintained after the time t2. That is, the state of the control signal CTR when the enable signal E rises is held. Therefore, the signal D3 having the same phase as the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, the latch circuit LAT3 outputs the output clock signal CLK0 having the same phase as the input clock signal CLK1.
[0091]
FIG. 20 is a timing chart when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is low, and the initial state of the control signal CTR is low. FIG. As can be seen from FIG. 20, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in phase. For this reason, the signal D4 is low, and the control signal CTR is also low.
[0092]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held low by the latch circuit LAT3. This low state output clock signal CLK0 is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal in phase with the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0093]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. Since the control signal CTR is in phase with the input clock signal CLK1, it is low. The fact that the control signal CTR is low means that the output of the exclusive OR circuit EXO1 is in phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having the same phase as the input clock signal CLK1. Further, the low state of the control signal CTR of the latch circuit LAT4 at the time t2 is maintained after the time t2. That is, the state of the control signal CTR when the enable signal E rises is held. Therefore, the signal D3 having the same phase as the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, the latch circuit LAT3 outputs an output clock signal CLK0 that is in phase with the input clock signal CLK1.
[0094]
FIG. 21 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is low. FIG. As can be seen from FIG. 21, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in opposite phases. Therefore, the signal D4 is high and the control signal CTR is also high.
[0095]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is high, the output clock signal CLK0 is held in the high state by the latch circuit LAT3. The output clock signal CLK0 in the high state is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal having a phase opposite to that of the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0096]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is low. The control signal CTR is high because it is opposite in phase to the input clock signal CLK1. When the control signal CTR is high, the output of the exclusive OR circuit EXO1 is in reverse phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having a phase opposite to that of the input clock signal CLK1. Further, the high state of the control signal CTR of the latch circuit LAT4 at time t2 is maintained after time t2. That is, the state of the control signal CTR when the enable signal E rises is held. For this reason, the signal D3 having a phase opposite to that of the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, an output clock signal CLK0 having a phase opposite to that of the input clock signal CLK1 is output from the latch circuit LAT3.
[0097]
FIG. 22 shows a timing chart when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is high, and the initial state of the control signal CTR is low. FIG. As can be seen from FIG. 22, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in phase. For this reason, the signal D4 is low, and the control signal CTR is also low.
[0098]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is low, the output clock signal CLK0 is held low by the latch circuit LAT3. This low state output clock signal CLK0 is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal in phase with the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0099]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. Since the control signal CTR is in phase with the input clock signal CLK1, it is high. When the control signal CTR is high, the output of the exclusive OR circuit EXO1 is in reverse phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having a phase opposite to that of the input clock signal CLK1. Further, the high state of the control signal CTR of the latch circuit LAT4 at time t2 is maintained after time t2. That is, the state of the control signal CTR when the enable signal E rises is held. For this reason, the signal D3 having a phase opposite to that of the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, an output clock signal CLK0 having a phase opposite to that of the input clock signal CLK1 is output from the latch circuit LAT3.
[0100]
FIG. 23 shows a timing chart when the initial state of the control signal CTR is high when the clock supply is stopped when the input clock signal CLK1 is low and the clock supply is restarted when the input clock signal CLK1 is high. FIG. As can be seen from FIG. 23, before the clock supply is stopped, that is, before time t1, the input clock signal CLK1 and the output clock signal CLK0 are in opposite phases. Therefore, the signal D4 is high and the control signal CTR is also high.
[0101]
The enable signal E switches to low at time t1. Since the output clock signal CLK0 at this time t1 is high, the output clock signal CLK0 is held in the high state by the latch circuit LAT3. The output clock signal CLK0 in the high state is also input to the exclusive OR circuit EXO2. Therefore, the signal D4 is output from the exclusive OR circuit EXO2 as a signal having a phase opposite to that of the input clock signal CLK1. This signal D4 is input to the latch circuit LAT4, but since the enable signal E is low, it is output as it is as the control signal CTR. This control signal CTR is input to the exclusive OR circuit EXO1.
[0102]
The enable signal E switches to high at time t2. The input clock signal CLK1 at time t2 is high. The control signal CTR is low because it is opposite in phase to the input clock signal CLK1. The fact that the control signal CTR is low means that the output of the exclusive OR circuit EXO1 is in phase. That is, the exclusive OR circuit EXO1 outputs a signal D3 having the same phase as the input clock signal CLK1. Further, the low state of the control signal CTR of the latch circuit LAT4 at the time t2 is maintained after the time t2. That is, the state of the control signal CTR when the enable signal E rises is held. Therefore, the signal D3 having the same phase as the input clock signal CLK1 is output from the exclusive OR circuit EXO1 after the time t2. Therefore, the latch circuit LAT3 outputs the output clock signal CLK0 having the same phase as the input clock signal CLK1.
[0103]
As can be seen from FIGS. 16 to 23, when the enable signal E falls, the clock gate circuit CG holds the state of the output clock signal CLK0 when the enable signal E falls. Then, the relationship between the in-phase / anti-phase when the enable signal E falls and the relationship between the in-phase / anti-phase when the enable signal E rises are summarized as shown in FIG.
[0104]
As can be seen from FIG. 24, when the input clock signal CLK1 and the output clock signal CLK0 are in phase when the enable signal E falls, the edge of the input clock signal CLK1 while the enable signal E is low. When the number is an even number, the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E rises is in phase (see FIGS. 16 and 20). That is, when the input clock signal CLK1 is switched between low and high during the clock supply stop period, the output clock signal CLK1 is output in the same phase. This also applies when the initial state is in reverse phase. That is, when the input clock signal CLK1 and the output clock signal CLK0 are in reverse phase when the enable signal E falls, the number of edges of the input clock signal CLK1 is an even number while the enable signal E is low. When the enable signal E rises, the input clock signal CLK1 and the output clock signal CLK0 are in opposite phases (see FIGS. 17 and 21).
[0105]
Further, as can be seen from FIG. 24, when the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E falls is in phase, the input clock while the enable signal E is low. When the number of edges of the signal CLK1 is an odd number, the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E rises is reversed (see FIGS. 18 and 22). That is, when the input clock signal CLK1 is switched between low and high during the clock supply stop period an odd number of times, the output clock signal CLK1 is output with the in-phase changed to the opposite phase. On the other hand, when the initial state is the reverse phase, the phase is switched to the same phase. That is, when the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E falls is opposite in phase, the number of edges of the input clock signal CLK1 while the enable signal E is low. In the case of an odd number, the relationship between the input clock signal CLK1 and the output clock signal CLK0 when the enable signal E rises is in phase (see FIGS. 19 and 23).
[0106]
As described above, the clock gate circuit CG according to the third embodiment can output the clock signal even if the supply of the clock signal is stopped or restarted at an arbitrary timing, as in the first and second embodiments described above. An extra edge can be prevented from occurring in CLK0, and a malfunction of the double edge flip-flop circuit can be prevented.
[0107]
(Fourth embodiment)
The fourth embodiment shows an example of a more specific gate element configuration for realizing the clock gate circuit according to the third embodiment.
[0108]
FIG. 25 is a diagram showing a clock gate circuit CG according to the fourth embodiment using gate elements. As can be seen from FIG. 25, the exclusive OR circuits EXO1 and EXO2 can be configured by connecting AND elements and NOR elements as shown. The latch circuits LAT3 and LAT4 can be configured by connecting inverter elements and clocked inverter elements as shown.
[0109]
FIG. 26 is a modification of the clock gate circuit CG shown in FIG. 25 to reduce the number of elements. That is, as can be seen from FIG. 26, by configuring the exclusive OR circuits EXO1 and EXO2 as clocked exclusive OR circuits, two transistors are reduced in the buffer circuit BF, and the control signal generation circuit CL 2 transistors were also reduced.
[0110]
(Fifth embodiment)
In the fifth embodiment, a clock gate circuit is realized by a specific configuration different from the above embodiment.
[0111]
FIG. 27 is a diagram showing a clock gate circuit CG according to the fifth embodiment. As can be seen from FIG. 27, the clock gate circuit CG according to the fifth embodiment includes a count circuit CNT1, an exclusive OR circuit EX03, and a latch circuit LAT5.
[0112]
The count circuit CNT1 is a circuit that counts the number of edges of the input clock signal CLK1 during the clock supply stop period. During the clock supply period, the circuit holds a high or low output when the clock supply is resumed. More specifically, an input clock signal CLK1 and an enable signal E are input to the count circuit CNT1. Then, the number of edges of the input clock signal CLK1 from when the enable signal E falls to when it rises is counted. If the counted number of edges is an even number, the signal N1 in the same state as when the enable signal E falls is output. That is, when N1 is low when the enable signal E falls, low is also output when the enable signal E rises. On the other hand, if N1 is high when the enable signal E falls, high is also output when the enable signal E rises. On the other hand, if the counted number of edges is an odd number, the signal N1 in a state different from that when the enable signal E falls is output. That is, if N1 is low when the enable signal E falls, a high is output when the enable signal E rises. On the other hand, if N1 is high when the enable signal E falls, low is output when the enable signal E rises.
[0113]
This signal N1 and the input clock signal CLK1 are input to the exclusive OR circuit EX03. The exclusive OR circuit EX03 is a circuit that outputs the input clock signal CLK1 in phase or in phase according to the state of the signal N1. That is, when the signal N1 is low, the signal D5 having the same phase as the input clock signal CLK1 is output. When the signal N1 is high, a signal D5 having a phase opposite to that of the input clock signal CLK1 is output.
[0114]
The latch circuit LAT5 outputs the signal D5 as it is as the output clock signal CLK0 when it is in the clock supply state, and when it is in the clock supply stop state, the state of the output clock signal CLK0 when the clock supply is stopped. Is a circuit that holds and outputs.
[0115]
As described above, the clock gate circuit according to the fifth embodiment counts the number of edges of the input clock signal CLK1 during the clock supply stop period by the count circuit CNT1, so that when the clock supply is resumed, It is decided whether to output the output clock signal CLK0 in the same phase or to output the output clock signal CLK0 in the opposite phase to the input clock signal CLK1. For this reason, even if the supply of the output clock signal CLK0 is stopped or restarted at an arbitrary timing, the clock gate circuit CG according to the fifth embodiment also generates the output clock signal CLK0 as in the other embodiments described above. Extra edges can be prevented from occurring, and malfunction of the double edge flip-flop circuit can be prevented.
[0116]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. In addition, each circuit and each element constituting each embodiment can be realized by using other circuits having equivalent functions. The clock gate circuit CG supplies the clock signal is not limited to the flip-flop circuit, and may be another device such as a memory.
[0117]
【The invention's effect】
According to the present invention, during the supply stop period of the output clock signal, the state of the output clock signal at the time when the supply of the output clock signal is stopped is held and output, and when the supply of the output clock signal is resumed, the output clock signal is output. Since the state of the output clock signal when the supply of the signal is stopped matches the state of the input clock signal when the supply of the output clock signal is restarted, the output is performed when the supply of the output clock signal is stopped and restarted. It is possible to prevent an extra edge from occurring in the clock signal.
[Brief description of the drawings]
FIG. 1 is a diagram showing a clock gating circuit including a clock gate circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the clock gate circuit shown in FIG. 1;
FIG. 3 is a diagram collectively showing a state of an output clock signal when a clock supply is stopped, a state of an input clock signal when a clock supply is resumed, and a relationship between the input clock signal and the output clock signal after the clock supply is resumed.
FIG. 4 is a diagram showing a clock gate circuit according to a second embodiment of the present invention.
5 is a diagram showing an example of a specific configuration of a clock gate circuit shown in FIG. 4;
FIG. 6 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is high when the supply of the output clock signal is stopped, and the input clock signal is also high when the supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being.
FIG. 7 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is high when the supply of the output clock signal is stopped, and the input clock signal is also supplied when the supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being high.
FIG. 8 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is high when supply of the output clock signal is stopped, and the input clock signal is low when supply of the output clock signal is resumed. The figure which shows a timing chart in a case.
FIG. 9 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is high when the output clock signal supply is stopped, and the input clock signal is low when the output clock signal supply is resumed. The figure which shows a timing chart in case of.
FIG. 10 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is low when the supply of the output clock signal is stopped, and the input clock signal is also low when the supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being.
FIG. 11 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is low when the output clock signal supply is stopped, and the input clock signal is also supplied when the output clock signal supply is resumed. The figure which shows a timing chart in the case of being low.
FIG. 12 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is low when supply of the output clock signal is stopped, and the input clock signal is high when supply of the output clock signal is resumed. The figure which shows a timing chart in a case.
FIG. 13 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is low when supply of the output clock signal is stopped, and the input clock signal is high when supply of the output clock signal is resumed. The figure which shows a timing chart in case of.
FIG. 14 is a timing chart illustrating the operation of the timing charts in FIGS. 6 to 13; the relationship between the input clock signal and the output clock signal when the clock supply is stopped; the number of edges of the input clock signal during the clock supply stop period; The figure which shows the relationship between the input clock signal of this and an output clock signal collectively in a table | surface.
FIG. 15 is a view showing a clock gate circuit according to a third embodiment.
FIG. 16 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is high when the supply of the output clock signal is stopped, and the input clock signal is also high when the supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being.
FIG. 17 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is high when the supply of the output clock signal is stopped, and the input clock signal is also supplied when the supply of the output clock signal is restarted. The figure which shows a timing chart in the case of being high.
FIG. 18 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is high when supply of the output clock signal is stopped, and the input clock signal is low when supply of the output clock signal is resumed. The figure which shows a timing chart in a case.
FIG. 19 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is high when the supply of the output clock signal is stopped, and the input clock signal is low when the supply of the output clock signal is restarted. The figure which shows a timing chart in the case of being.
FIG. 20 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is low when supply of the output clock signal is stopped, and the input clock signal is low when supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being.
FIG. 21 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is low when the supply of the output clock signal is stopped, and the input clock signal is also supplied when the supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being low.
FIG. 22 shows that when the output clock signal is supplied in the same phase before the clock supply is stopped, the input clock signal is low when the supply of the output clock signal is stopped, and the input clock signal is high when the supply of the output clock signal is restarted. The figure which shows a timing chart in a case.
FIG. 23 shows that when the output clock signal is supplied in reverse phase before the clock supply is stopped, the input clock signal is low when supply of the output clock signal is stopped, and the input clock signal is high when supply of the output clock signal is resumed. The figure which shows a timing chart in the case of being.
FIG. 24 shows the operation of the timing charts in FIGS. 16 to 23 with respect to the relationship between the input clock signal and the output clock signal when the clock supply is stopped, the number of edges of the input clock signal during the clock supply stop period, and after the clock supply is restarted. The figure which shows the relationship between the input clock signal of this and an output clock signal collectively in a table | surface.
FIG. 25 is a diagram showing a clock gate circuit according to a fourth embodiment of the present invention.
FIG. 26 is a diagram showing a clock gate circuit according to another fourth embodiment of the present invention.
FIG. 27 is a diagram showing a clock gate circuit according to a fifth embodiment of the present invention;
FIG. 28 is a diagram showing a clock gating circuit including a conventional clock gate circuit.
FIG. 29 is a timing chart of operations of a single edge flip-flop circuit and a double edge flip-flop circuit.
FIG. 30 is a timing chart when a single edge flip-flop circuit and a double edge flip-flop circuit are operated using a conventional clock gate circuit (with a single-edge flip-flop circuit and a double-edge flip-flop circuit; If the behavior matches).
FIG. 31 is a timing chart when a single edge flip-flop circuit and a double edge flip-flop circuit are operated using a conventional clock gate circuit (a circuit between a single edge flip-flop circuit and a double edge flip-flop circuit; If the behavior does not match).
FIG. 32 is a diagram showing a detailed timing chart of a conventional clock gate circuit.
[Explanation of symbols]
CLK1 input clock signal
CLK0 output clock signal
E Enable signal
Dn Input data signal
Qn output data signal
CG clock gate circuit
FF flip-flop circuit

Claims (9)

The input clock signal is supplied to the outside as an output clock signal, the supply of the output clock signal is stopped at an arbitrary timing, and the supply of the stopped output clock signal is restarted at an arbitrary timing. It can be a clock gate circuit,
During the period when the supply of the output clock signal is stopped, a hold circuit that holds the state of the output clock signal when the supply of the output clock signal is stopped and outputs the hold circuit;
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped matches the state of the input clock signal when the supply of the output clock signal is resumed. A buffer circuit that outputs the output clock signal to the outside in the same phase as the input clock signal, and outputs the output clock signal to the outside in the opposite phase to the input clock signal if not matched ,
A clock gate circuit comprising: While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing , A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during a period in which the supply of the output clock signal is stopped ;
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the outside as the output clock signal; and
A control signal generation circuit that outputs to the buffer a control signal for controlling whether the buffer circuit outputs the input clock signal in the same phase or outputs it in the opposite phase; and
With
The control signal generation circuit includes:
During the period when the supply of the output clock signal is stopped, the number of edges of the input clock signal is counted during the period when the supply of the output clock signal is stopped,
When resuming the supply of the output clock signal,
When the counted number of edges is an even number, if the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is the same phase, the output of the input clock signal in the same phase The control signal to be output as a clock signal is output, and when the relationship between the input clock signal and the output clock signal at the time of stopping supply of the output clock signal is in reverse phase, the input clock signal is in reverse phase Output the control signal to be output as an output clock signal,
When the counted number of edges is an odd number, the input clock signal is in reverse phase when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in phase. The control signal to be output as an output clock signal is output, and when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in reverse phase, the input clock signal is in phase Outputting the control signal to be output as an output clock signal;
A clock gate circuit characterized by the above. While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing , A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during a period in which the supply of the output clock signal is stopped ;
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the outside as the output clock signal; and
A control signal generation circuit that outputs to the buffer a control signal for controlling whether the buffer circuit outputs the input clock signal in the same phase or outputs it in the opposite phase; and
With
The control signal generation circuit includes:
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped and the state of the input clock signal when the supply of the output clock signal is resumed are: If they match, the control signal that outputs the output clock signal in the same phase as the input clock signal is output to the outside, and if they do not match, the output clock signal is out of phase with the input clock signal to the outside Outputting the control signal to be output;
A clock gate circuit characterized by the above. A buffer circuit that receives an input clock signal and a control signal and outputs an output clock signal;
A control signal generation circuit that receives the input clock signal, the output clock signal, and an enable signal and outputs the control signal to the buffer circuit;
With
The buffer circuit includes a first exclusive OR circuit and a first latch circuit,
The control signal generation circuit includes a second exclusive OR circuit and a second latch circuit,
The first exclusive OR circuit receives the input clock signal and the control signal from the second latch circuit, and outputs a first intermediate signal obtained by calculating an exclusive OR of these two signals.
The first latch circuit receives the first intermediate signal and the enable signal, and based on the state of the enable signal, outputs the output clock signal as the output signal as it is or holds the first intermediate signal,
The second exclusive OR circuit receives the output clock signal and the input clock signal, and outputs a second intermediate signal obtained by calculating an exclusive OR of these two signals.
The second intermediate circuit and the enable signal are input to the second latch circuit, and based on the state of the enable signal, the second intermediate signal is left as it is or is held and output as the control signal.
A clock gate circuit characterized by the above. The input clock signal is supplied to the outside as an output clock signal, and the supply of the output clock signal is stopped at an arbitrary timing by switching the enable signal, and the supply of the stopped output clock signal is arbitrarily performed. A clock gate circuit that can be restarted at the timing,
The input clock signal and the enable signal are input, and during the clock supply stop period, the number of edges of the input clock signal is counted, and a first intermediate signal that is high or low depending on whether the number of edges is even or odd. A count circuit that maintains a high or low state when the clock supply is resumed and outputs it as a first intermediate signal during the clock supply period;
A first exclusive OR circuit that receives the first intermediate signal and the input clock signal and outputs a second intermediate signal obtained by performing an exclusive OR operation between the two signals;
The second intermediate signal and the enable signal are input, the second intermediate signal is directly output as an output clock signal during the clock supply period, and an output clock signal when the clock supply is stopped during the clock supply stop period. A latch circuit that holds and outputs the state;
A clock gate circuit comprising: The input clock signal is supplied to the outside as an output clock signal, the supply of the output clock signal is stopped at an arbitrary timing, and the supply of the stopped output clock signal is restarted at an arbitrary timing. A clock gate circuit that can
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:
The clock gate circuit includes:
During the period when the supply of the output clock signal is stopped, a hold circuit that holds the state of the output clock signal when the supply of the output clock signal is stopped and outputs the hold circuit;
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped matches the state of the input clock signal when the supply of the output clock signal is resumed. A buffer circuit that outputs the output clock signal to the outside in the same phase as the input clock signal, and outputs the output clock signal to the outside in the opposite phase to the input clock signal if not matched ,
A clock gating circuit comprising: While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing , A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during the period in which the supply of the output clock signal is stopped ;
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:
The clock gate circuit includes:
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the double edge flip-flop circuit as the output clock signal; and
A control signal generation circuit that outputs to the buffer circuit a control signal for controlling whether the buffer circuit outputs the input clock signal in phase or in phase, and
With
The control signal generation circuit includes:
When resuming the supply of the output clock signal, the state of the output clock signal when the supply of the output clock signal is stopped and the state of the input clock signal when the supply of the output clock signal is resumed are: If they match, the control signal is output to the double edge flip-flop circuit while keeping the output clock signal in phase with the input clock signal, and if not, the output clock signal is inverted from the input clock signal. Outputting the control signal to be output to the double edge flip-flop circuit in a phase;
A clock gating circuit characterized by that. While supplying the input clock signal input to the outside as an output clock signal, the supply of the output clock signal can be stopped at an arbitrary timing, and the supply of the stopped output clock signal can be restarted at an arbitrary timing , A clock gate circuit that maintains the state of the output clock signal when the supply of the output clock signal is stopped and outputs it to the outside during the period in which the supply of the output clock signal is stopped ;
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:
The clock gate circuit includes:
When resuming the supply of the output clock signal, the input clock signal remains in phase or is out of phase and output to the double edge flip-flop circuit as the output clock signal; and
A control signal generation circuit that outputs to the buffer circuit a control signal for controlling whether the buffer circuit outputs the input clock signal in phase or in phase, and
With
The control signal generation circuit includes:
During the period when the supply of the output clock signal is stopped, the number of edges of the input clock signal is counted during the period when the supply of the output clock signal is stopped,
When resuming the supply of the output clock signal,
When the counted number of edges is an even number, if the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is the same phase, the output of the input clock signal in the same phase The control signal to be output as a clock signal is output, and when the relationship between the input clock signal and the output clock signal at the time of stopping supply of the output clock signal is in reverse phase, the input clock signal is in reverse phase Output the control signal to be output as an output clock signal,
When the counted number of edges is an odd number, the input clock signal is in reverse phase when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in phase. The control signal to be output as an output clock signal is output, and when the relationship between the input clock signal and the output clock signal when the supply of the output clock signal is stopped is in reverse phase, the input clock signal is in phase Outputting the control signal to be output as an output clock signal;
A clock gating circuit characterized by that. A clock gate circuit according to claim 4 or 5,
A double edge flip-flop circuit that receives the output clock signal from the clock gate circuit and is synchronized with both falling and rising edges of the output clock signal;
A clock gating circuit comprising:

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