JP3746815B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory element, and more particularly to a nonvolatile memory that can directly control a source-drain current by using a ferroelectric in a gate portion of a transistor.
[0002]
[Prior art]
Semiconductor memory elements include a volatile memory that can store information only while the power is turned on and a non-volatile memory that can store information even when the power is turned off. Volatile memory includes DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Non-volatile memory includes mask ROM (Mask Read Only Memory, PROM). Programmable Read Only Memory (EEPROM), EEPROM (Electrically Erasable Programmable Read Only Memory), and the like.
[0003]
Among these non-volatile memories, EPROM and EEPROM are ROMs whose contents can be rewritten like RAM, and have a MOS-FET (MOS type field effect transistor) structure having a floating gate between a control gate and a channel. Things are common. EPROM utilizes the fact that hot electrons generated when high voltage is applied between the control gate and the drain remain in the floating gate by erasing the carrier in the floating gate by irradiating ultraviolet rays. Then, the write operation is performed. In the EEPROM, an erasing operation can be performed without irradiating ultraviolet rays.
[0004]
[Problems to be solved by the invention]
However, the above-described floating gate type MOS-FET requires a time on the order of milliseconds (msec.) And a high electric field on the order of 10 ⁷ V / cm for writing and erasing operations. For this reason, the EEPROM cannot realize write and erase operations in the same cycle as a normal DRAM, and also requires a high-voltage power supply.
[0005]
Many of the FRAMs (Ferroelectric Random Access Memories) that have been developed recently have a structure in which a DRAM capacitor is replaced with a ferroelectric capacitor (Japanese Patent Laid-Open No. 2-11396), and write, erase, and read operations are performed. Since both are accompanied by polarization inversion of the ferroelectric material, the fatigue of the ferroelectric material becomes a problem, and since each operation involves charging and discharging of the capacitor, the operation time takes about 100 nanoseconds (nsec.). Further, it is necessary to provide a transistor and a capacitor separately, which is disadvantageous for area reduction.
[0006]
In order to solve such a problem, a semiconductor memory element having a structure in which an epitaxial oxide film and a ferroelectric thin film are stacked in a gate portion of a transistor has been proposed (Japanese Patent Laid-Open No. 4-243232). In addition, while providing a non-volatile memory suitable for area reduction with less fatigue of ferroelectrics, the gate characteristics of transistors have problems in terms of reproducibility and stability, and it is difficult to increase production yield. It was. As the cause, it may be difficult to control the interface between the Si substrate and the ferroelectric thin film, and carriers may be injected from the Si substrate into the ferroelectric to cancel the polarization of the ferroelectric.
[0007]
The present invention has been made to solve such an unsolved problem of the conventional technology, and is suitable for area reduction, at high speed, with less fatigue of the ferroelectric material, particularly in gate characteristics. An object of the present invention is to provide a semiconductor memory device that is excellent in stability, does not inject carriers into a ferroelectric material, and is excellent in production yield improvement.
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor memory element having a transistor formed on a Si single crystal substrate, wherein the gate portion of the transistor has a thickness of 20 to 20 on the Si single crystal substrate. It has a laminated structure of a carrier injection blocking layer made of a Si oxide film of 100 angstroms (except when the film thickness is 50 angstroms or more) , an oriented CeO ₂ thin film, an oriented PbTiO ₃ thin film, and a conductor thin film. Features.
[0010]
A semiconductor memory element according to a second aspect of the present invention is the semiconductor memory element according to the first aspect, wherein the Si single crystal substrate is a Si (100) single crystal substrate.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the CeO ₂ thin film oriented, a specific crystal axis of the paraelectric crystals is that of CeO ₂ thin film vertically aligned strongly to the substrate surface. The oriented PbTiO3 thin films, the specific crystal axis of a ferroelectric crystal is that of PbTiO ₃ film vertically aligned strongly to the substrate surface, the crystal axis is perpendicular strongly to the substrate in particular allow polarization strongest It is preferable. The arrangement of these crystals can be confirmed by high-speed electron diffraction, X-ray diffraction, or the like.
[0012]
As the conductor thin film, for example, a metal thin film, a conductive oxide thin film, or the like in which impurities are diffused into polycrystalline Si to increase conductivity can be used.
[0013]
The laminated structure of the present invention is a laminated structure comprising a Si substrate and an Si oxide film, an oriented CeO ₂ thin film, an oriented PbTiO ₃ thin film, and a conductor thin film in order from the side closest to the Si substrate. There is no need to go.
[0014]
The substrate used in the present invention is a Si single crystal substrate. This is necessary for orienting the CeO ₂ thin film and the PbTiO ₃ thin film, and in order to generate the polarization of the PbTiO ₃ thin film more stably, the one oriented to the (100) or (111) plane is preferably used. .
[0015]
These paraelectric oxide thin films can be formed by, for example, vacuum deposition, laser ablation, or the like.
[0016]
The oriented CeO ₂ thin film provided between the Si single crystal substrate and the PbTiO ₃ thin film is necessary to prevent the ferroelectric from deteriorating due to mutual diffusion between the Si single crystal substrate and the oriented PbTiO ₃ thin film.
[0017]
The Si oxide film as a carrier injection blocking layer is important not only in terms of preventing carriers from being injected from the Si substrate and canceling the polarization of the ferroelectric thin film, but also stably turning on the source-drain current. -It is indispensable for turning off and improving manufacturing yield, yield, and stable operation of the device. Further, it is particularly preferable that the thickness of the carrier injection blocking layer made of this Si oxide film has a value between 20 and 100 angstroms. This demonstrates good electrical characteristics at the interface, prevents carriers from moving between the Si single crystal substrate and the oriented ferroelectric thin film, and lowers the polarization of the ferroelectric, and also reduces the device operating voltage. This is a preferable condition for maintaining low. This Si oxide film is formed by forming an oriented paraelectric oxide thin film and then heat-treating it in an oxidizing atmosphere, or by exposing it to an oxidizing atmosphere for a long time when forming an oriented ferroelectric thin film. Can do.
[0018]
By using the gate electrode according to the present invention and reversing the spontaneous polarization of the ferroelectric, the source-drain current can be turned on and off. In order to reverse the spontaneous polarization of the ferroelectric, it is necessary to apply a voltage between the substrate and the gate, between the drain and the gate, or between the source and the gate. The reversal speed of the spontaneous polarization of the ferroelectric is extremely fast, and a rewriting and erasing operation speed higher than that of the DRAM can be obtained. In addition, it is not necessary to provide a capacitor in addition to the transistor, which is advantageous for area reduction.
[0019]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0020]
FIG. 1 is a schematic cross-sectional view showing a semiconductor memory element of the present invention. In FIG. 1, 1 is a Si single crystal substrate, 2 is a source of a transistor formed on the Si single crystal substrate 1, 3 is a drain of the transistor, and 4 is a carrier injection blocking layer formed on the Si single crystal substrate 1. Si oxide film 5, 5 is a CeO ₂ thin film as a paraelectric oxide thin film formed on the Si oxide film 4, 6 is a PbTiO ₃ thin film as a ferroelectric thin film formed on the CeO ₂ thin film 5, Reference numeral 7 denotes an aluminum electrode connected to the PbTiO ₃ thin film 6. Reference numeral 8 denotes an insulating film.
[0021]
First, an n-type Si (100) single crystal substrate having a resistivity of 2 Ωcm is used as the substrate 1. The substrate 1 is heated to about 900 ° C. in a vacuum of 1 × 10 ⁻⁶ Torr, and then a CeO ₂ tablet is used. The CeO ₂ thin film 5 having a film thickness of about 150 Å was formed on the Si substrate 1 by vacuum deposition by electron beam heating. When the surface of this CeO ₂ thin film was observed by RHEED (reflection high-energy electron diffraction), several dot patterns could be observed, and it was confirmed that an (110) -oriented epitaxial film had grown.
[0022]
Next, heating was performed at 900 ° C. for 5 minutes in a 1 atm dry oxygen atmosphere to form a Si oxide film 4 as a SiO ₂ carrier injection blocking layer of about 40 Å at the interface between the Si substrate 1 and the CeO ₂ thin film 5. An aluminum (Al) electrode 7 as a conductor thin film was formed on the surface of the CeO ₂ thin film by a vacuum deposition method, and capacitance-voltage (CV) characteristics were measured using this electrode. As a result, as shown in FIG. 2, the electrostatic capacitance (capacitance) increases linearly with respect to the applied voltage as shown by the solid line until the applied voltage is about 1 V, and is saturated at about 2.2 V. As the applied voltage decreases, as shown by the dotted line, the voltage decreases by following substantially the same path in reverse, and the capacitance does not change substantially when a negative voltage is applied. Thus, very good CV characteristics were obtained, and it was proved that the CeO ₂ thin film can be used as a gate oxide film. As shown in FIG. 3, when the above oxidation operation is performed, the interface state is 10 ¹³ / cm ² · eV to 10 ¹¹ / cm ² when compared with the case where the above oxidation operation is not performed.・ Improved to eV. The interface state is a technique for electrically evaluating the disorder of crystallinity at the gate lower interface, and can be estimated from the slope of the CV characteristic. A value of 10 ¹¹ / cm ² · eV or less can be interpreted as a good interface.
[0023]
Further, a PbTiO ₃ thin film 6 was formed on CeO ₂ / SiO ₂ / Si (100) by MOCVD. That is, Pb (C ₂ H ₅ ) ₄ and Ti (i-OC ₃ H ₇ ) ₄ are used as materials, maintained at temperatures of 0 ° C. and 30 ° C., respectively, and carriers N _{2 of} 7 cc / min and 4.5 cc / min, respectively. The material was carried by gas and sprayed onto a structure composed of a CeO ₂ / SiO ₂ / Si (100) substrate having a substrate temperature of 540 ° C. together with 30 cc / min of O ₂ to form a PbTiO ₃ thin film 6. The atmospheric pressure was about 1 Torr. The film thickness was about 1000 angstroms. When this thin film was analyzed using an X-ray diffractometer, it was confirmed that the thin film was strongly oriented in the PbTiO ₃ (100) and (001) planes (FIG. 4).
[0024]
When a cross section of this sample was observed using a transmission electron microscope (TEM), a PbTiO ₃ / CeO ₂ / SiO ₂ / Si (100) laminated structure was formed as schematically shown in FIG. It was confirmed. Specifically, this laminated structure includes a Si (100) substrate 1, a Si oxide thin film (SiO ₂ thin film) 4, a CeO _x film 5a, a CeO ₂ thin film 5, and a PbTiO ₃ thin film 6 laminated in this order. It was confirmed that an SiO ₂ thin film was formed between the CeO ₂ thin film and the CeO ₂ thin film.
[0025]
Furthermore, an aluminum electrode 7 was formed on the sample surface by vacuum deposition, and capacitance-voltage (CV) characteristics were measured. As a result, the hysteresis characteristic according to the sweep direction as shown in FIG. 6 was shown (memory-window width 2.3 V), and the storage operation was confirmed. Here, after once sweeping the bias voltage from −3 V to +3 V, the capacitance at the center of the memory window was measured, and the change with time was observed. By this operation, the memory retention time of this sample can be measured. As a result, in the case where the carrier injection blocking layer was not particularly formed, the capacitance decreased by 20% or more in about 27 hours, whereas in the case where the carrier injection blocking layer was formed as described above, one month passed. However, no decrease in capacitance was observed.
[0026]
Further, the PbTiO ₃ / CeO ₂ / SiO ₂ is formed between the source and drain, an Al electrode is provided, and an attempt is made to control the on / off of the source-drain current using the self-polarization of PbTiO ₃ , The phenomenon was confirmed.
[0027]
【The invention's effect】
As described above, according to the present invention, an CeO ₂ (paraelectric) thin film that is oriented and grown on a Si substrate is formed, and then heated in an oxidizing atmosphere to heat the interface between the Si substrate and the CeO ₂ thin film. A carrier injection layer made of a Si oxide film is formed on this, and a highly oriented PbTiO ₃ (ferroelectric) thin film is formed through this layer to prevent carriers from being injected into the ferroelectric from the Si substrate. In addition, the current between the source and the drain can be directly turned on and off by the ferroelectric self-polarization. Compared to the FRAM currently being studied, the read operation does not involve reversal of spontaneous polarization, so the film fatigue of the ferroelectric is extremely small, and there is no need to provide a capacitor in a region other than the transistor. A nonvolatile memory suitable for area reduction can be provided. Furthermore, control of the interface, which has been considered difficult in the past, is achieved by forming a carrier injection blocking layer consisting of a Si oxide film on the interface by heating after the formation of CeO ₂ to block carrier injection from the substrate to the ferroelectric. In addition, the gate characteristics can be further improved. As described above, there is an effect that a nonvolatile memory having many advantages can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a basic structure of a semiconductor memory element according to an embodiment of the present invention.
FIG. 2 shows the result of measuring capacitance-voltage (CV) characteristics by depositing an Al electrode on a Si (100) substrate that was vacuum-deposited with CeO ₂ and heat-treated in an oxidizing atmosphere. FIG.
FIG. 3 is a characteristic diagram showing a result of measuring capacitance-voltage (CV) characteristics by depositing an Al electrode on a vacuum-deposited CeO ₂ on a Si (100) substrate.
FIG. 4 is a characteristic diagram showing the results obtained by further depositing PbTiO ₃ on a Si (100) substrate by vacuum deposition of CeO ₂ by the CVD method and analyzing the sample using an X-ray diffractometer; is there.
FIG. 5 is a cross-sectional view schematically showing a result of observation of a cross-sectional structure of a PbTiO ₃ / CeO ₂ / SiO ₂ / Si (100) sample with a transmission electron microscope.
6 is a characteristic diagram showing a result of measuring capacitance-voltage (CV) characteristics after forming an Al electrode on the surface of the sample shown in FIG. 5 by vacuum vapor deposition. FIG.
[Explanation of symbols]
1 Si single crystal substrate 2 source 3 drain 4 Si oxide film 5 paraelectric PbTiO ₃ film 7 of aluminum as CeO ₂ film 6 ferroelectric thin film as an oxide film (Al) electrode 8 insulating film

Claims (2)

In a semiconductor memory device having a transistor formed on a Si single crystal substrate, the gate portion of the transistor has a film thickness of 20 to 100 angstroms (provided that the film thickness is 50 angstroms or more) on the Si single crystal substrate. A semiconductor memory element having a laminated structure of a carrier injection blocking layer made of a Si oxide film, an oriented CeO ₂ thin film, an oriented PbTiO ₃ thin film, and a conductor thin film.   The semiconductor memory element according to claim 1, wherein the Si single crystal substrate is a Si (100) single crystal substrate.

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