JP3748857B2 - Semiconductor integrated circuit and data carrier equipped with the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, a non-contact information medium on which the semiconductor integrated circuit is mounted, and a non-contact information system including the non-contact information medium.
[0002]
[Prior art]
In recent years, a data carrier such as a non-contact IC card which uses a mutual induction phenomenon of coils to supply power and transmit / receive data using radio waves of a predetermined wavelength has entered a practical stage. This contactless IC card is roughly classified into a contact type, a proximity type, and a proximity type according to the distance at which communication can be performed between the reader / writer that transmits and receives radio waves to and from the contactless IC card. Etc., and the standards for each are being prepared.
[0003]
In particular, if the proximity type non-contact IC card that can be used at a distance of about 10 cm from the reader / writer is used for applications such as a commuter pass, for example, it can be used from a regular entry at a ticket gate of a station. Thus, the gate opening / closing control of the ticket gate can be performed based on the exchange of information in a non-contact state with the reader / writer without taking out the card.
[0004]
Hereinafter, techniques related to a conventional non-contact type IC card mounted with a semiconductor integrated circuit will be described with reference to FIGS.
FIG. 14 shows an outline of a non-contact IC card system.
[0005]
Communication between the non-contact type IC card 1 and the reader / writer 2 is performed when the non-contact type IC card 1 approaches the reader / writer 2 and performs non-contact power transmission and signal exchange using electromagnetic waves. The reader / writer 2 transmits / receives information on the card 1 to / from the host device 3.
[0006]
The non-contact type IC card 1 is configured as shown in FIG.
The non-contact type IC card 1 includes a non-contact IC card LSI 11, an antenna coil 12, and a tuning capacitor 13. The non-contact type IC card LSI 11 includes an analog circuit unit 20, a logic circuit unit 21, a memory circuit unit 22, a random number generation circuit 23, and the like.
[0007]
The antenna coil 12 for transmitting and receiving the electromagnetic wave 5 output from the antenna coil 4 of the reader / writer 2 is connected to the pads 36 and 37 of the LSI 11 for non-contact IC card. A tuning capacitor 13 is connected to the antenna coil 12. The antenna coil 12 receives the electromagnetic wave 5 from the reader / writer 2, and an AC voltage is generated at both ends (between the pad 36 and the pad 37) of the antenna coil 12.
[0008]
The AC voltage generated at both ends of the antenna coil 12 is input to the analog circuit unit 20. The analog circuit unit 20 includes a rectifier circuit 30, a power supply circuit 31, a clock generation circuit 32, a demodulation circuit 33, a modulation circuit 34, a reset generation circuit 35, and the like. A power supply voltage for operating the logic circuit unit 21, the memory circuit unit 22, and the random number generation circuit 23 is generated by the rectifier circuit 30 and the power supply circuit 31.
[0009]
The reset generation circuit 35 monitors the generated voltage of the power supply circuit 31, and when the non-contact type IC card LSI 11 reaches a power supply voltage level that does not cause a malfunction, the reset signal is canceled and the non-contact type IC card LSI 11 operates. To do.
[0010]
The clock generation circuit 32 generates a clock for operating the logic circuit unit 21 and the memory circuit unit 22 from the AC signal generated at both ends of the antenna coil 12.
[0011]
Data transmitted and received between the non-contact type IC card 1 and the reader / writer 2 is superimposed on the AC electromagnetic wave 5 and demodulated by the demodulation circuit 33 (when the non-contact type IC card 1 receives data from the reader / writer 2). Alternatively, modulation is performed by the modulation circuit 34 (when the non-contact type IC card 1 transmits data to the reader / writer 2). Data transmitted and received between the non-contact type IC card 1 and the reader / writer 2 is processed by the logic circuit unit 21 and stored in the memory circuit unit 22 by designating addresses and data, and read and written by designating addresses. .
[0012]
In order to prevent unauthorized writing or falsification of data written in the non-contact type IC card 1, the IC card 1 and the reader / writer 2 perform a process of authenticating each other when exchanging data. That is, the reader / writer 2 executes mutual authentication processing with the non-contact type IC card 1 that has returned a predetermined response signal in response to a polling signal transmitted by itself. As a method of mutual authentication processing, a method using an encryption key is known.
[0013]
Here, a mutual authentication process using encryption performed between the non-contact type IC card 1 and the reader / writer 2 will be briefly described.
First, the reader / writer 2 transmits an internally generated random number a to the non-contact type IC card 1. The non-contact type IC card 1 converts the received random number a into a random number A using its own encryption key, and returns the random number A to the reader / writer. The reader / writer 2 processes the generated random number a using a common encryption key used with a specific non-contact type IC card 1 to obtain the random number A ′, and the obtained random number A ′ and the non-contact type The random number A returned from the type IC card 1 is compared. The reader / writer 2 authenticates the non-contact type IC card 1 as a regular one when the random number A matches the random number A ′.
[0014]
Next, the non-contact type IC card 1 transmits the internally generated random number b to the reader / writer 2. In this case, the reader / writer 2 converts the received random number b into a random number B using its own encryption key, and returns the random number B to the contactless IC card 1. The non-contact type IC card 1 processes the generated random number b using a common encryption key used with a specific reader / writer 2, and generates a random number B ′ and a random number B returned from the reader / writer 2. And compare. The non-contact type IC card 1 authenticates that the reader / writer 2 is authentic when the random number B and the random number B ′ match.
[0015]
The non-contact type IC card 1 and the reader / writer 2 incorporate a random number generation circuit 23 that generates a random number used in the mutual authentication process.
Usually, in order to generate a random number that is difficult to predict, a thermal noise signal source based on the thermal fluctuation of the resistor is used. However, since the thermal noise signal generates only a very small voltage fluctuation (about 50 μV), a highly sensitive amplifier is required. Further, since the power supply voltage of the non-contact type IC card 1 is generated by rectifying electromagnetic waves, the carrier wave component and the transmission data signal component of the electromagnetic waves are largely superimposed as noise on the power supply voltage, and therefore based on the thermal fluctuation of the resistor. Amplifying a thermal noise signal source is very difficult. Therefore, normally, a logic circuit is used for the random number generation circuit 23 for the non-contact type IC card 1.
[0016]
FIG. 16 shows an example of a conventional random number generation circuit 23.
The random number generation circuit 23 is a circuit called a so-called 48-bit M-sequence random number generation circuit, and includes a 1-bit shift register 41, a 2-bit shift register 42, a 25-bit shift register 43, and a 20-bit shift register connected in cascade (multi-stage serial). 44, and adders 51, 51, 51 constituting an adder circuit for inputting the sum of the shift register outputs of each bit to the input terminal of the first-stage 20-bit shift register 44.
[0017]
The M-sequence random number generation circuit is described in (Patent Document 1) and the like. A system using random numbers in the non-contact IC card system is described in (Patent Document 2) and the like.
[0018]
The 1-bit shift register 41 includes a flip-flop 55 and a transfer gate 56 that operate in synchronization with the clock signal CLK output from the CLK circuit 32. When the address signal line in which the address 15F2H is selected by the CPU included in the logic circuit unit 21 is switched from "L" to "H", the output of the flip-flop 55 is output as random number data D10.
[0019]
The circuits of the 2-bit shift register 42, the 25-bit shift register 43, and the 20-bit shift register 44 are the same circuits as the 1-bit shift register 41 connected in series by the number of bits to be shifted. The 2-bit shift register 42 outputs random number data D11 and D12 when the address 15F2H is selected. The 25-bit shift register 43 outputs random number data D13 to D17, D18 to D115, D20 to D27, and D28 to D211 when the addresses 15F2H, 15F3H, 15F4H, and 15F5H are selected. The 20-bit shift register 44 outputs random numbers as data D212 to D215, D30 to D37, and D38 to D315 when the addresses 15F5H, 15F6H, and 15F7H are selected.
[0020]
[Patent Document 1]
JP-A-6-244684
[0021]
[Patent Document 2]
Japanese Patent Publication No. 7-27460
[0022]
[Problems to be solved by the invention]
The random number generated by the random number generation circuit 23 configured as described above has a predetermined generation pattern that repeats at a constant time.
[0023]
For this reason, communication data exchanged between the reader / writer 2 and the non-contact type IC card 1 may be eavesdropped and a random number generation pattern may be specified. When the random number pattern is specified in this way, the contactless IC card 1 can be forged by using a table in which the random number a and the random number A are associated with each other without knowing the encryption key and the content of the encryption process. Can do. Similarly, the reader / writer 2 can be counterfeited by using a table in which the random number b and the random number B are associated with each other.
[0024]
In order to effectively prevent forgery of the contactless IC card 1 and the reader / writer 2 due to the wiretapping of the communication data, a sophisticated random number generation circuit is required so that the generated pattern cannot be deciphered even if the communication data is wiretapped. The However, if the random number generation circuit is complicated, illegal decoding of the random number generation pattern can be effectively prevented, but the circuit size increases. Particularly in the case of the non-contact type IC card 1, it is desirable that the size of the built-in random number generation circuit is small.
[0025]
Further, the non-contact type IC card 1 changes the response time of the response signal to the polling process from the reader / writer 2 at the timing based on the internally generated random number, for example, before executing the communication process for performing the mutual authentication process. For example, it is necessary to execute a process for avoiding a collision with a response signal output from another non-contact type IC card. In order to improve the communication speed between the non-contact type IC card 1 and the reader / writer 2, a random number generation circuit that operates at high speed is desired.
[0026]
The present invention makes it possible to reduce the size of a non-contact IC card (non-contact information medium) incorporating the circuit with a simple configuration, and to generate random data that is fast, regular, and difficult to predict. An object of the present invention is to provide a semiconductor integrated circuit that can be generated.
[0027]
[Means for Solving the Problems]
In order to solve the above problems, the semiconductor integrated circuit for a data carrier according to the present invention is equipped with a counter configured by a logic circuit for random number generation, so that a non-contact type IC card is placed in the communication area of the reader / writer 2. Each time the non-contact type IC card 1 enters the communication area of the reader / writer 2 by measuring the time from when it enters to actually receiving the command of the reader / writer and using that value (measurement time) as a random number value It is possible to generate completely uniform and non-periodic random numbers. Therefore, it is possible to easily realize a safe non-contact type IC card that is very difficult to counterfeit against an attack by a malicious third party.
[0028]
  The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit used for the data carrier in a non-contact type information system in which a signal sent from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal. A rectifier circuit that receives and rectifies a carrier wave transmitted from a reader / writer, a demodulator circuit that demodulates an input received signal and reproduces data, and an output voltage of the rectifier circuit exceeds a specified value. From timingDetects the synchronization pattern included in the signal sent from the reader / writerAnd a random number generation circuit for counting the time interval and generating a random number.
[0029]
In addition, a reset generation circuit is provided for detecting the timing when the input voltage exceeds a specified value by using the output signal of the rectification circuit that receives and rectifies the carrier wave transmitted from the reader / writer, and the random number generation circuit is the reset generation circuit. The counting is started by the output signal of
[0030]
Further, the demodulating signal of the demodulating circuit for demodulating the inputted received signal and reproducing the data or the synchronization signal included in the received signal is recognized, and the random number generating circuit ends the counting.
[0031]
Further, the clock signal is a synchronous clock obtained by dividing a carrier wave transmitted from a reader / writer by a clock generation circuit.
In addition, a logic circuit unit that returns a random number generated by the random number generation circuit to the reader / writer is further provided.
[0032]
  The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit used for the data carrier in a non-contact type information system in which a signal sent from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal. A rectifier circuit that receives and rectifies a carrier wave transmitted from a reader / writer, a demodulator circuit that demodulates an input received signal and reproduces data, and an output voltage of the rectifier circuit is a first specified value. A first random number generation circuit for generating a random number by counting a time interval from when the reader / writer is recognized to when the reader / writer is recognized, and from the timing when the output voltage of the rectifier circuit exceeds a second specified value A second random number generation circuit that counts a time interval until recognition of a random number and generates a random numberThe output of the first random number generation circuit and the output of the second random number generation circuit are combined to generate a random number.It is characterized by that. The firstAnd the output of the second random number generator circuit and the output of the second random number generator circuitIt further comprises a logic circuit section for returning random numbers to the reader / writer.
[0033]
  The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit used for the data carrier in a non-contact type information system in which a signal sent from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal. A rectifier circuit that receives and rectifies a carrier wave transmitted from a reader / writer, a demodulator circuit that demodulates an input received signal and reproduces data, and an output voltage of the rectifier circuit exceeds a specified value. A first random number generation circuit that counts a first clock signal and counts a time interval to generate a random number from timing to recognition of the reader / writer, and an output obtained by receiving and rectifying a carrier wave transmitted from the reader / writer A second clock signal different from the first clock signal from when the voltage exceeds a specified value until the reader / writer is recognized. A second random number generating circuit for generating a counted random number counted by the time intervalThe output of the first random number generation circuit and the output of the second random number generation circuit are combined to generate a random number.It is characterized by that.
[0034]
The first clock signal is a synchronous clock obtained by frequency-dividing a carrier wave transmitted from a reader / writer by a clock generation circuit, and the second clock signal is generated by an asynchronous clock generation circuit. It is characterized by being.
[0035]
  The firstAnd the output of the second random number generator circuit and the output of the second random number generator circuitIt further comprises a logic circuit unit for returning random numbers to the reader / writer..
[0037]
A data carrier according to the present invention is equipped with any of the semiconductor integrated circuits described above.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, each embodiment of the present invention will be described with reference to FIGS.
In addition, the same code | symbol is attached | subjected and demonstrated to what has the effect | action similar to FIG. 15 which shows a prior art example.
[0039]
(Embodiment 1)
1 to 6 show (Embodiment 1) of the present invention.
FIG. 1 shows a random number generation circuit incorporated in place of the random number generation circuit 23 in the non-contact type IC card 1 shown in FIG.
[0040]
The random number generation circuit 100 includes an N-bit binary counter 101 and N transfer gates 56.₀~ 56_N-1It is comprised by. The reset signal 102 and the clock signal 103 are input to the N-bit binary counter 101, and N outputs Q₀~ Q_N-1N transfer gates 56 according to the reception start signal 104₀~ 56_N-1An N-bit random number is output via.
[0041]
The clock signal 103 is a synchronous clock obtained by frequency-dividing the carrier wave transmitted from the reader / writer 2 by the clock generation circuit 32.
FIG. 2 shows a communication time chart between the non-contact type IC card 1 and the reader / writer 2. FIG. 3 shows the distance dependency of the power supply voltage and reset signal generated inside the non-contact IC card LSI 11 between the non-contact IC card 1 and the reader / writer 2. FIG. 4 shows various signal waveforms obtained by enlarging the time range A in FIG.
[0042]
The reader / writer 2 transmits a carrier wave (13.56 MHz in the international standard ISO / IEC14443), and has a period T as shown in FIG._DLThen, the downlink signal is superimposed and the non-contact type IC card 1 is called.
[0043]
When the non-contact type IC card 1 approaches the reader / writer 2, the power supply voltage generated by the internal rectifier circuit 30 rises as shown in FIG. In the example, at a timing T1 that is 4.5 volts or more), the reset signal is canceled as shown in FIG. 3B, and the non-contact type IC card 1 starts operating. Then, the non-contact type IC card 1 transmits the transmission data (uplink signal) to the reader / writer 2 as shown in FIG.
[0044]
When the non-contact type IC card 1 starts receiving, a reception start signal 104 is generated by detecting a synchronization pattern formed by a downlink signal transmitted from the reader / writer 2 or a specific pattern of the received signal. If it can be normally received, the non-contact type IC card 1 transmits an uplink signal to the reader / writer 2 and one transaction is completed.
[0045]
FIG. 5 shows a reception signal waiting time T from when the reset signal 102 is released until the reception start signal 104 is output.₀The probability distribution of
The downlink signal transmitted by the reader / writer 2 has a fixed period T._DLHowever, the contactless IC card 1 approaches the reader / writer 2 manually. Therefore, the period when the non-contact type IC card 1 approaches the reader / writer 2 is the period T_DLAnd the time interval has no correlation.
[0046]
Therefore, the reception signal waiting time T₀, As shown in FIG._DLBelow time, it is uniform and completely random. This received signal waiting time T₀Can be used as random numbers that are completely uniform and have no periodicity.
[0047]
Receive signal waiting time T₀FIG. 6 shows a configuration example and timing chart of the N-bit binary counter 101 for measuring.
The N-bit binary counter has N flip-flops 55₀~ 55_N-1Consists of. Flip-flop 55 of the first stage for the clock signal₀And the output NQ of the flip-flop 55 is returned to the input D, whereby the output Q₀Divides the input clock signal by two and outputs it. Similarly flip-flop 55₁~ 55_N-1Are connected in series, Q₁~ Q_NThe number of clocks from when the reset signal is released until the reception start signal is input is counted, and the reception signal waiting time T₀Can be measured.
[0048]
Here, the number of bits necessary for the binary counter is considered.
Since the reader / writer 2 does not know whether the non-contact type IC card 1 falls within the communication range, the reader / writer 2 periodically superimposes (polling signal) on the downlink signal. The period T of this downlink signal_DLIs determined by the system specifications, but here it is about 5 msec when referring to the case of ISO / IEC14443. The clock signal is 13.56 MHz because a normal carrier wave is used.
[0049]
Hence, the downlink signal period T_DLThe number of generated clock signals is 67567 ≈ approximately 2¹⁶It becomes a piece. That is, under the above conditions, a 16-bit random number can be generated by a 16-bit binary counter.
[0050]
The logic circuit unit 21 returns a random number generated using the count output of the random number generation circuit 100 or a random number obtained by converting the count output using its own encryption key to the reader / writer 2.
[0051]
In this embodiment, an asynchronous binary count-up counter is used as the counter. However, a synchronous counter and a down counter are equally effective.
Here, Q₀~ Q_N-1Output directly in parallel, but it is also effective to rearrange each bit. Specifically, Q_N-1~ Q₀The randomness can be further increased by performing as described above.
[0052]
(Embodiment 2)
7 to 9 show (Embodiment 2) of the present invention.
The random number generation circuit 100 of (Embodiment 1) has a received signal waiting time T.₀Is a complete random number, but there is a problem that the number of random number bits is as small as about 16 bits. If the number of bits is small, when a non-contact IC card 1 and reader / writer 2 perform mutual authentication, a malicious third party 2¹⁶Adding one trial succeeds once. Therefore, in order to make the contactless IC card 1 more secure, it is necessary to increase the number of bits of the random number.
[0053]
FIG. 7 shows a random number generation circuit 110 incorporated in place of the random number generation circuit 23 in the non-contact type IC card 1 shown in FIG.
FIG. 8 shows the distance dependency of the first reset signal 112 and the second reset signal 113 between the non-contact type IC card 1 and the reader / writer 2. FIG. 9 shows the reception signal waiting time T.₀₁And T₀₂The relationship is shown.
[0054]
The random number generation circuit 110 includes two 16-bit binary counters 111a and 111b as first and second random number generation circuits, and 32 transfer gates 56.₀~ 56₁₅, 56₁₆~ 56₃₁It is comprised by.
[0055]
The 16-bit binary counter 111a performs counting of the clock signal 103 by the first reset signal 112, and the 16-bit binary counter 111b performs counting of the clock signal 103 by the second reset signal 113.
[0056]
As shown in FIGS. 8A and 8B, the first reset signal 112 is set at an operation lower limit voltage (4.5 volts) of a normal non-contact type IC card LSI 11 and a release distance of about 10 cm. The data is set so that the data in the memory circuit 22 in the non-contact type IC card LSI 11 can be normally written.
[0057]
As shown in FIGS. 8A and 8C, the second reset signal 113 is 4.3 volts, and is set lower by 0.2 volts than the first reset signal 112.
Here, at a voltage of about 4.3 volts, the logic circuit inside the non-contact type IC card LSI 11 operates normally and does not cause a problem. The second reset signal 113 can be released at a distance of about 12 cm between the non-contact type IC card 1 and the reader / writer 2 when set at a reset voltage of 4.3 volts. The difference in release distance between the first reset signal 112 and the second reset signal 113 is about 2 cm.
[0058]
When a non-contact IC card system is used at a ticket gate at a station or the like, the movement speed of a person is about 6 km / h, and the difference of 2 cm between the reset signal 1 and the second reset signal 113 is moved in about 12 msec. General downlink signal period T_DLIs 5 msec. Therefore, when the difference between the release distances of the reset signal 1 and the second reset signal 113 is 2 cm, the period T of the downlink signal_DLThere are 2.4 cycles.
[0059]
As shown in FIG.₀~ Q₁₅Received signal waiting time T determined by₀₁And Q₁₆~ Q₃₁Received signal waiting time T determined by₀₂Have a correlation. However, in actual use, since the movement speed of the person changes, the reception signal waiting time T₀₁And T₀₂Since the multiple changes every time the non-contact type IC card 1 enters the communication area of the reader / writer 2 from the inclination of 2.4 times, the correlation becomes very weak. Therefore, Q₀~ Q₁₅And Q₁₆~ Q₃₁Can be used for random numbers.
[0060]
The logic circuit unit 21 returns a random number generated using the count output of the random number generation circuit 110 or a random number obtained by converting the count output using its own encryption key to the reader / writer 2.
[0061]
Where Q₁~ Q₃₁Output directly in parallel, but it is also effective to rearrange each bit.
In order to obtain a random number of 32 bits or more, it can be easily realized by preparing a plurality of reset signals and 16-bit binary counters.
[0062]
(Embodiment 3)
10 and 11 show (Embodiment 3) of the present invention.
The random number generation circuit of (Embodiment 1) is a reception signal waiting time T.₀Is a complete random number, but there is a problem that the number of random number bits is as small as about 16 bits. If the number of bits is small, when a non-contact IC card 1 and reader / writer 2 perform mutual authentication, a malicious third party 2¹⁶Adding one trial succeeds once. Therefore, it is necessary to increase the number of bits of the random number.
[0063]
FIG. 10 shows a random number generation circuit incorporated in place of the random number generation circuit 23 in the non-contact type IC card 1 shown in FIG.
The random number generation circuit 120 includes two 16-bit binary counters 111a and 111b as first and second random number generation circuits, and 32 transfer gates 56.₀~ 56₃₁It is comprised by.
[0064]
A first clock signal 103a and a second clock signal 103b having different frequencies are input to the 16-bit binary counters 111a and 111b, respectively.
[0065]
The clock generation circuit 124 that generates the second clock signal 103b is a ring oscillator in which 2N + 1 stage (odd number) inverters are connected in series as shown in FIG. The first clock signal 103a is a synchronous clock obtained by dividing the carrier wave transmitted from the reader / writer 2 by the clock generation circuit 32, and operates at the carrier wave period (in this case, 13.56 MHz). The second clock signal 103b operates at a frequency determined by the number of stages of the ring oscillator and the capacity of the inverter 125.
[0066]
When the constant of the clock generation circuit 124 is set to about twice that of 13.56 MHz, the number of random bits can be easily increased as in the second embodiment.
The logic circuit unit 21 returns a random number generated using the count output of the random number generation circuit 120 or a random number obtained by converting the count output using its own encryption key to the reader / writer 2.
[0067]
Where Q₁~ Q₃₁Output directly in parallel, but it is also effective to rearrange each bit.
In order to obtain a random number of 32 bits or more, it can be easily realized by preparing a plurality of pairs of clock signals and 16-bit binary counters.
[0068]
(Embodiment 4)
FIG. 12 shows (Embodiment 4) of the present invention.
The random number generation circuit of (Embodiment 1) is a reception signal waiting time T.₀Is a complete random number, but there is a problem that the number of random number bits is as small as about 16 bits. If the number of bits is small, a malicious third party will not be able to use 2 when performing mutual authentication between the contactless IC card and the reader / writer 2.¹⁶Adding one trial succeeds once. Therefore, it is necessary to increase the number of bits of the random number.
[0069]
(Embodiment 2) When the random number generation circuit of (Embodiment 3) is used, there is a correlation between each 16 bits although it is very weak. Therefore, it is necessary to generate a more uniform random number.
[0070]
FIG. 12 shows a random number generation circuit according to (Embodiment 4) of the present invention incorporated in place of the random number generation circuit 23 in the non-contact type IC card 1 shown in FIG.
The random number generation circuit 130 includes 16-bit binary counters 111a and 111b and 32 transfer gates 56.₀~ 56₃₁, A 16-bit parallel / serial conversion circuit 131, an M-sequence random number generation circuit 132, and an M-bit serial / parallel conversion circuit 133.
[0071]
Since the M-sequence random number generation circuit 132 operates logically, it is necessary to set an initial value when the reset signal is released. That is, if the initial value is not set after the reset signal is released, when all the output signals of the shift registers in the M-sequence random number generation circuit 132 are in the “L” state, only “L” is output forever Because.
[0072]
Normally, when only a M-sequence random number generation circuit 132 is used and a random number generation circuit is used, initial value setting is important. Therefore, generally, random numbers are generated by using the identification number set in the memory circuit unit 22 of each contactless IC card 1 as an initial value. By adopting such a configuration, it is possible to generate a different pseudorandom number for each contactless IC card 1.
[0073]
However, when random number generation is performed by such a method, since the initial value is constant, the random number after power-on is repeated. In addition, the initial value from which the random number is generated is built in the memory circuit unit 22, and if a malicious third party grasps the memory content by analysis, the generation pattern of the random number can be easily known. It cannot be said that it is safe for security.
[0074]
Therefore, by using the random number obtained by the random number generation circuit of (Embodiment 1) as the initial value for the M-sequence random number generation circuit 132, it is safer and has a large value corresponding to the number of bits of the M-sequence random number generation circuit 132. A random number can be generated with the number of bits.
[0075]
In this (Embodiment 4), a 16-bit parallel-serial conversion circuit 131 and an M-sequence random number generation circuit 132 are used for expansion of random numbers obtained by the random number generation circuit of (Embodiment 1) and diffusion between bits. However, the random number generated in (Embodiment 2) or (Embodiment 3) can be similarly implemented using the 16-bit parallel-serial conversion circuit 131 and the M-sequence random number generation circuit 132.
[0076]
(Embodiment 5)
FIG. 13 shows (Embodiment 5) of the present invention.
The random number generation circuit of the above (Embodiment 1) to (Embodiment 4) has a reception signal waiting time T in a normal use situation.₀Is a complete random number. However, if a malicious third party brings the non-contact type IC card 1 close to the reader / writer 2 in the same way, it will not be a random number but will output the same value every time. Therefore, it is necessary to increase randomness.
[0077]
FIG. 13 shows a random number generation circuit incorporated in place of the random number generation circuit 23 in the non-contact type IC card 1 shown in FIG.
The random number generation circuit 140 includes a 16-bit binary counter 111 and 16 transfer gates 56.₀~ 56₁₅, Selectors 141a and 141b.
[0078]
One of the first and second clock signals 103a and 103b having different frequencies is selected and input to the clock of the 16-bit binary counter 111 by the selector 141a.
[0079]
Here, the 2N + 1 stage (odd number stage) of the clock generation circuit for generating the first clock signal 103a is a ring oscillator or the like in which inverters are connected in series, and has a clock frequency whose frequency changes depending on the power supply voltage, temperature, and the like.
[0080]
The second clock signal 103b operates at the period of the carrier wave output from the reader / writer 2 (in this case, 13.56 MHz).
In addition, the selector 141b selects the first reset signal 112 and the second reset signal 113 that start the operation at different voltages as the reference signal for resetting the 16-bit binary counter 111, that is, the operation of the 16-bit binary counter 111. Then enter.
[0081]
In this way, the selectors 141a and 141b are used to switch the first and second clock signals 103a and 103b, and the first and second reset signals 112 and 113 are switched to periodically operate from the outside. In this case, the output of the 16-bit binary counter 111 changes every time. Even if a malicious third party brings the non-contact type IC card 1 close to the reader / writer 2 every time, a different random number is output every time. It will be. Therefore, a safer random number can be generated and used.
[0082]
【The invention's effect】
As described above, the semiconductor integrated circuit of the present invention is used for the data carrier in a non-contact type information system in which a signal transmitted from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal. A semiconductor integrated circuit that receives a carrier wave transmitted from a reader / writer and counts a time interval by counting a clock signal from when the rectified output voltage exceeds a specified value until the reader / writer is recognized. Since there is provided a random number generation circuit and a logic circuit unit that returns a random number obtained by converting the count output of the random number generation circuit at the timing when the reader / writer is recognized using its own encryption key to the reader / writer, the data carrier Measure the time from when the reader / writer enters the communication area to when the reader / writer command is actually received. And, by using the value (measurement time) as a random number value, each time the data carrier enters the reader writer communication area, it can produce a perfectly uniform and periodic no random numbers. Therefore, a safe data carrier that is very difficult to counterfeit against attacks by malicious third parties can be easily realized.
[0083]
In addition, the present invention provides a first random number generation circuit for counting a time interval from when the output voltage obtained by receiving and rectifying a carrier wave transmitted from a reader / writer exceeds a first specified value until the reader / writer is recognized. And a second random number generation circuit for counting a time interval from when the output voltage obtained by receiving and rectifying the carrier wave transmitted from the reader / writer exceeds the first specified value until the reader / writer is recognized from the received signal. And a logic circuit unit that returns a random number obtained by converting the count output of the first and second random number generation circuits at the timing when the reader / writer is recognized using its own encryption key to the reader / writer, or The reader / writer is recognized when the output voltage rectified by receiving the carrier wave transmitted from the reader / writer exceeds the specified value. A first random number generating circuit that counts the first clock signal and counts the time interval; and the reader / writer is detected from the timing when the output voltage rectified by receiving the carrier wave transmitted from the reader / writer exceeds a specified value. A second random number generation circuit that counts a second clock signal different from the first clock signal to recognize a time interval before recognition, and the first and second timings at which the reader / writer is recognized Similarly, a safe data carrier can be easily realized by providing a logic circuit unit that returns a random number obtained by converting the count output of the random number generation circuit using its own encryption key to the reader / writer. it can.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a random number generation circuit which is a main part of (Embodiment 1) of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a communication time chart of the contactless IC card and the reader / writer according to the embodiment;
FIG. 3 is an explanatory diagram of the distance dependency between the contactless IC card and the reader / writer of the power supply voltage and the reset signal according to the embodiment;
4 is a waveform diagram of each signal in the time range A shown in FIG. 2 according to the embodiment.
FIG. 5 is an explanatory diagram of a probability distribution of a received signal waiting time according to the embodiment;
FIG. 6 is a configuration diagram and timing chart of an N-bit binary counter according to the embodiment;
FIG. 7 is a configuration diagram of a random number generation circuit in (Embodiment 2) of a semiconductor integrated circuit according to the present invention;
FIG. 8 is an explanatory diagram of distance dependency of the first and second reset signals according to the embodiment;
FIG. 9 shows a reception signal waiting time T according to the embodiment;₀₁And T₀₂Relationship diagram
FIG. 10 is a configuration diagram of a random number generation circuit in (Embodiment 3) of a semiconductor integrated circuit according to the present invention;
FIG. 11 is a configuration diagram of a clock generation circuit according to the embodiment;
FIG. 12 is a configuration diagram of a random number generation circuit in (Embodiment 4) of a semiconductor integrated circuit according to the present invention;
FIG. 13 is a configuration diagram of a random number generation circuit in the semiconductor integrated circuit according to the fifth embodiment of the present invention.
FIG. 14 is a schematic view of a non-contact type IC card system.
FIG. 15 is a block diagram of a conventional non-contact type IC card.
FIG. 16 is a configuration diagram of a conventional random number generation circuit (M-sequence random number generation circuit).
[Explanation of symbols]
1 Non-contact IC card (data carrier)
2 leader writer
3 Host machine
5 Electromagnetic waves
11 LSI for non-contact type IC card
21 Logic circuit
22 Memory circuit
30 Rectifier circuit
31 Power supply circuit
32 Clock generation circuit
33 Demodulator circuit
35 Reset generation circuit
34 Modulation circuit
103a, 103b first and second clock signals
100 Random number generator
T₀, T₀₁, T₀₂    Time interval
111a, 111b first and second random number generation circuits
124 Clock generation circuit
131 Parallel to serial converter
132 M-sequence random number generator
141a, 141b first and second selector circuits

Claims (11)

A semiconductor integrated circuit used for the data carrier in a non-contact information system in which a signal sent from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal,
A rectifier circuit that receives and rectifies the carrier wave transmitted from the reader / writer, and
A demodulator that demodulates the received signal and reproduces the data;
Random number generation that generates a random number by counting the time interval by counting the clock signal from the timing when the output voltage of the rectifier circuit exceeds a specified value until the synchronization pattern included in the signal sent from the reader / writer is detected And a semiconductor integrated circuit. A reset generation circuit is provided for detecting a timing when the input voltage exceeds a specified value by receiving an output signal of the rectification circuit that receives and rectifies a carrier wave transmitted from a reader / writer, and a random number generation circuit is provided for the reset generation circuit. 2. The semiconductor integrated circuit according to claim 1, wherein counting is started by an output signal. 2. The semiconductor integrated circuit according to claim 1, wherein the random number generating circuit terminates the counting upon recognizing a demodulated signal of the demodulating circuit for demodulating an inputted received signal and reproducing data or a synchronization signal included in the received signal. 2. The semiconductor integrated circuit according to claim 1, wherein the clock signal is a synchronous clock obtained by dividing a carrier wave transmitted from a reader / writer by a clock generation circuit. 2. The semiconductor integrated circuit according to claim 1, further comprising a logic circuit unit that returns a random number generated by the random number generation circuit to the reader / writer. A semiconductor integrated circuit used for the data carrier in a non-contact information system in which a signal sent from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal,
A rectifier circuit that receives and rectifies the carrier wave transmitted from the reader / writer, and
A demodulator that demodulates the received signal and reproduces the data;
A first random number generation circuit for generating a random number by counting a time interval from when the output voltage of the rectifier circuit exceeds a first specified value until the reader / writer is recognized;
A second random number generating circuit for generating a random number by counting a time interval from when the output voltage of the rectifier circuit exceeds a second specified value to when the reader / writer is recognized, and generating the first random number A semiconductor integrated circuit configured to generate a random number by combining the output of the circuit and the output of the second random number generation circuit. 7. The semiconductor integrated circuit according to claim 6, further comprising a logic circuit unit that returns a random number generated by combining the output of the first random number generation circuit and the output of the second random number generation circuit to the reader / writer. A semiconductor integrated circuit used for the data carrier in a non-contact information system in which a signal sent from a reader / writer is recognized on the data carrier side and the data carrier responds and returns a signal,
A rectifier circuit that receives and rectifies the carrier wave transmitted from the reader / writer, and
A demodulator that demodulates the received signal and reproduces the data;
A first random number generation circuit that counts a first clock signal and counts a time interval to generate a random number from the timing when the output voltage of the rectifier circuit exceeds a specified value until the reader / writer is recognized;
The second clock signal that is different from the first clock signal is counted until the reader / writer is recognized from the timing when the output voltage rectified by receiving the carrier wave transmitted from the reader / writer exceeds a specified value. A second random number generation circuit that counts the interval and generates a random number, and is configured to generate a random number by combining the output of the first random number generation circuit and the output of the second random number generation circuit Semiconductor integrated circuit. The first clock signal is a synchronous clock obtained by frequency-dividing a carrier wave transmitted from a reader / writer by a clock generation circuit, and the second clock signal is an asynchronous clock generated by an asynchronous clock generation circuit. The semiconductor integrated circuit according to claim 8. 9. The semiconductor integrated circuit according to claim 8, further comprising a logic circuit unit that returns a random number generated by combining the output of the first random number generation circuit and the output of the second random number generation circuit to the reader / writer. A data carrier on which the semiconductor integrated circuit according to claim 1 is mounted.

Images