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JP3750466B2 - Semiconductor wafer finish polishing method - Google Patents
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JP3750466B2 - Semiconductor wafer finish polishing method - Google Patents

Semiconductor wafer finish polishing method Download PDF

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Publication number
JP3750466B2
JP3750466B2 JP2000049395A JP2000049395A JP3750466B2 JP 3750466 B2 JP3750466 B2 JP 3750466B2 JP 2000049395 A JP2000049395 A JP 2000049395A JP 2000049395 A JP2000049395 A JP 2000049395A JP 3750466 B2 JP3750466 B2 JP 3750466B2
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Japan
Prior art keywords
polishing
wafer
slurry
semiconductor wafer
alkaline
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JP2000049395A
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JP2001239452A (en
Inventor
健夫 加藤
秀樹 坂本
英之 近藤
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Sumco Corp
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Sumco Corp
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  • Mechanical Treatment Of Semiconductor (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、シリコンウェーハに代表される半導体ウェーハの仕上げ研磨方法に関するものである。
【0002】
【従来の技術】
一般に半導体ウェーハの製造工程は、単結晶インゴットをスライスして薄円板状のウェーハを得るスライス工程と、スライス工程によって得られたウェーハの割れ、欠けを防止するためにその外周部を面取りする面取り工程と、このウェーハを平面化するラッピング工程と、面取り及びラッピングされたウェーハに残留する加工歪みを除去するエッチング工程と、このウェーハの表面を鏡面にする研磨工程と、研磨されたウェーハを洗浄してこれに付着した研磨剤や異物を除去する洗浄工程からなる。この鏡面研磨工程では、研磨布とウェーハ間に研磨スラリーを用い、いわゆる、メカノケミカル研磨法(機械化学複合研磨法)でウェーハを研磨している。これは機械研磨が持つ力学的作用とエッチングによる化学的作用とを複合させ、その相乗効果で高能率、高精度の面質を得る方法で、その研磨特性は研磨時の機械的要素と化学的要素の配分により左右される。またこの鏡面研磨工程には、エッチングによる表面の凹凸を除去するための粗研磨工程と、この粗研磨の後のウェーハ表面の最終的な面質を決定する仕上げ研磨工程がある。
従来、この仕上げ研磨工程では、研磨布には圧縮率5%以上の比較的柔らかい布が、研磨スラリーにはSiO2系微粒子その他の砥粒を弱アルカリ液中に懸濁させた液が使用される。仕上げ研磨スラリーには、通常更に添加有機物が10ppm以上含有されており、この添加有機物は化学反応を抑制・制御し、また液粘性を高め、ヘイズ・スクラッチを防止する効果を有する。
【0003】
【発明が解決しようとする課題】
しかし、前述した研磨布と研磨スラリーを用いた仕上げ研磨では、粗研磨後に残存するエッチングに起因した5μm〜1mmの範囲の波長成分の凹凸の除去効率が悪く、この範囲のマイクロラフネスを低減するためには長時間の研磨が必要であった。
また、仕上げ研磨に使用される研磨スラリーは研磨面に成長した自然酸化膜や研磨時に付着した有機物の影響を受ける。そのため、研磨反応を開始する時間が遅れ、短時間の研磨では面質が不安定になる問題があった。
本発明の目的は、ウェーハ表面のマイクロラフネスを短時間で低減しかつ最終的な面質を安定にする半導体ウェーハの仕上げ研磨方法を提供することにある。
【0004】
【課題を解決するための手段】
請求項1に係る発明は、半導体ウェーハと研磨布との間に研磨スラリーを介在させてウェーハを研磨してウェーハの表面の最終的な面質を決定する半導体ウェーハの仕上げ研磨方法において、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であってポリビニルアルコール又はヒドロキシエチルセルロースのいずれか一方またはその双方からなる添加有機物の含有率が10ppm未満の研磨スラリーを用いてウェーハを研磨した後に、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であってポリビニルアルコール又はヒドロキシエチルセルロースのいずれか一方またはその双方からなる添加有機物の含有率が10ppm以上の研磨スラリーを用いてウェーハを更に研磨することを特徴とする半導体ウェーハの仕上げ研磨方法である。
請求項1に係る発明では、研磨布の圧縮率及び研磨スラリーの含有有機物に注目し、従来の仕上げ研磨で使用していた組合せとは異なる、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であって添加有機物の含有率が10ppm未満の研磨スラリーにより研磨した後、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であって添加有機物の含有率が10ppm以上の研磨スラリーを用いてウェーハを更に研磨する仕上げ研磨を行う。前段の研磨の組合せでは、化学反応の抑制をする添加有機物の含有量が10ppm未満の研磨スラリーを用いることで研磨反応開始が速まり、また比較的柔らかい研磨布を用いることで、粗研磨後に残存するエッチングに起因した5μm〜1mmの範囲の波長成分の凹凸の除去効率を高めることができ、短時間の研磨でウェーハの最終的な面質が安定する。
【0005】
後段の研磨の組合せでは、従来の仕上げ研磨に相当する研磨を行うことで、よりマイクロラフネスを低減できる。
【0006】
また研磨スラリーが上記有機物を含むことにより、より効果的に研磨反応を抑制し、制御することができる。
【0007】
【発明の実施の形態】
次に本発明の実施の形態について説明する。
本発明の研磨布はスウェードが挙げられる。スウェードの基布はポリウレタン類が通常用いられる。研磨布の圧縮率は、JIS L−1096に準拠した方法で求められる。具体的には公知の自動圧縮率測定器を使用し、初荷重L0(300g/cm2)を付加してその1分後の厚さT1を計測し、この計測と同時に荷重をL1(1800g/cm2)に増加させて、その1分後に厚さT2を計測し、前記T1とT2に基づいて下記式(1)により圧縮率が求められる。
【0008】
圧縮率(%)={(T1−T2)/T1}×100 ……(1)
本発明の仕上げ研磨方法には、通常片面研磨方法が用いられる。図1に基づいて片面研磨方法について述べる。この研磨装置10は回転定盤11とウェーハ保持具12を備える。回転定盤11は大きな円板であり、その底面中心に接続されたシャフト13によって回転する。回転定盤11の上面には研磨布14が貼付けられる。ウェーハ保持具12は加圧ヘッド12aとこれに接続して加圧ヘッド12aを回転させるシャフト12bからなる。加圧ヘッド12aの下面には研磨プレート16が取付けられる。研磨プレート16の下面には複数枚の半導体ウェーハ17が貼付けられる。回転定盤11の上部には研磨スラリー18を供給するための配管19が設けられる。この研磨装置10により半導体ウェーハ17を研磨する場合には、加圧ヘッド12aを下降して半導体ウェーハ17に所定の圧力を加えてウェーハ17を押さえる。配管19から研磨スラリー18を研磨布14に供給しながら、加圧ヘッド12aと回転定盤11とを同一方向に回転させて、ウェーハ17の表面を平坦に研磨する。
【0009】
次にこのような装置による仕上げ研磨について説明する
【0010】
先ず研磨布に圧縮率5%以上の表層がスウェードからなる研磨布を、研磨スラリーにアルカリ性であって添加有機物の含有率が10ppm未満の研磨スラリーを用いてウェーハを研磨する。圧縮率10〜20%の表層がスウェードからなる研磨布とアルカリ性であって添加有機物の含有率が10ppm未満の研磨スラリーを用いてウェーハを研磨することが好ましい。添加有機物含有率が10ppmを越えると化学反応の抑制効果が強くなり過ぎるため、研磨レートが低下し、ラフネス除去効率が低下する不具合を生じる。この組合せで研磨することによりウェーハ表面の凹凸の5μm〜1mmの波長成分の除去効率を高めることができ、また研磨面に成長した自然酸化膜や付着有機物の影響を速やかに除去できる。
【0011】
次に、上記研磨に続いて、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であって添加有機物の含有率が10ppm以上の研磨スラリーを用いてウェーハを研磨する。圧縮率10〜20%の表層がスウェードからなる研磨布とアルカリ性であって添加有機物の含有率が100ppm〜1%の研磨スラリーを用いてウェーハを研磨することが好ましい。この磨を行うことで更にウェーハ表面のマイクロラフネスを低減できる。
【0012】
【実施例】
次に本発明の実施例を説明する。
実施例
先ず、半導体ウェーハとして粗研磨工程を終えたシリコンウェーハを用意し、表層がスウェードからなる圧縮率が5%以上の研磨布と有機物が添加されているSiO 2 の研磨粒子が分散した市販されているアルカリ性の研磨用スラリー原液を純水で希釈して添加有機物の含有率が100ppm以上になるように調製したアルカリ性研磨スラリーを用いて図1に示す研磨装置により研磨圧力1.96×104Pa、研磨布とウェーハの相対速度1.0m/sで仕上げ研磨を3分間行った。続いてこのシリコンウェーハを表層がスウェードからなる圧縮率が5%以上の研磨布と有機物が添加されていないSiO 2 の研磨粒子が分散した市販されているアルカリ性の研磨用スラリー原液を純水で希釈して調製した有機物が添加されていないアルカリ性研磨スラリーを用いて上記と同様の研磨条件で更に3分間仕上げ研磨を行った。
【0013】
<比較例1>
実施例1と同様に粗研磨されたシリコンウェーハを用意し、表層がスウェードからなる圧縮率が5%以上の研磨布と有機物が添加されていないSiO 2 の研磨粒子が分散した市販されているアルカリ性の研磨用スラリー原液を純水で希釈して調製した有機物が添加されていないアルカリ性研磨スラリーを用いて図1に示す研磨装置により研磨圧力1.96×104Pa、研磨布とウェーハの相対速度1.0m/sで仕上げ研磨を6分間行った。
<比較評価>
仕上げ研磨を終えたシリコンウェーハの表面を光学的非接触式プロファイラを用いて表面粗さパワースペクトル(Power Spectral Density、以下、PSDという。)を測定し、得られたPSDより波長100μm以下の平方根平均ラフネス(root-mean-square roughness、以下、Rmsという。)を求めた。実施例1及び比較例1で得られたPSDを図2に、Rmsを表1に示す。なお、図2には実施例1及び比較例1のPSD曲線の他に粗研磨工程を終えた仕上げ研磨前のウェーハ表面より得られたPSDを基準値をして示す。
なお、PSDとは、表面粗さプロファイルをフーリエ変換によって空間周波数ごとの成分に分解したものである。また、Rmsはある空間周波数の範囲でPSDを積分したものの平方根である。
【0014】
【表1】

Figure 0003750466
【0015】
表1より明らかなように比較例1に対して実施例1ではRms値が減少しており、短時間の研磨でウェーハ表面のラフネスが低減していることが判る
また、図2より比較例1に対して実施例1では空間周波数1×10-2〜1×10-1(μm-1)の範囲でのPSD強度が小さくなっており、マイクロラフネスが低減されていることがわかる。
【0016】
【発明の効果】
以上述べたように、本発明によれば、半導体ウェーハの仕上げ研磨を圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であってポリビニルアルコール又はヒドロキシエチルセルロースのいずれか一方またはその双方からなる添加有機物の含有率が10ppm未満の研磨スラリーの組合せで研磨した後に、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であってポリビニルアルコール又はヒドロキシエチルセルロースのいずれか一方またはその双方からなる添加有機物の含有率が10ppm以上の研磨スラリーを用いてウェーハを更に研磨するようにしたので、ウェーハ表面のマイクロラフネスを短時間で低減し、かつ最終的な面質を安定にすることができる。
【図面の簡単な説明】
【図1】 半導体基板の片面研磨装置の構成図。
【図2】 実施例1及び比較例1の空間周波数における表面粗さパワースペクトルを示す図。
【符号の説明】
10 片面研磨装置
11 回転定盤
12 ウェーハ保持具
12a 加圧ヘッド
12b シャフト
13 シャフト
14 研磨布
16 研磨プレート
17 半導体ウェーハ
18 研磨スラリー
19 配管[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for finishing polishing a semiconductor wafer represented by a silicon wafer.
[0002]
[Prior art]
In general, the manufacturing process of a semiconductor wafer includes a slicing process for slicing a single crystal ingot to obtain a thin disk-shaped wafer, and a chamfering process for chamfering the outer periphery to prevent cracking and chipping of the wafer obtained by the slicing process. A polishing process for planarizing the wafer, an etching process for removing chamfering and processing distortion remaining on the lapped wafer, a polishing process for mirroring the surface of the wafer, and cleaning the polished wafer. And a cleaning process for removing abrasives and foreign matters adhering to the surface. In this mirror polishing process, a polishing slurry is used between the polishing cloth and the wafer, and the wafer is polished by a so-called mechanochemical polishing method (mechanical chemical composite polishing method). This is a method that combines the mechanical action of mechanical polishing and the chemical action of etching, and synergistically obtains high-efficiency, high-precision surface quality. It depends on the distribution of elements. In addition, the mirror polishing process includes a rough polishing process for removing surface irregularities due to etching and a final polishing process for determining the final surface quality of the wafer surface after the rough polishing.
Conventionally, in this final polishing process, a relatively soft cloth with a compression ratio of 5% or more is used as the polishing cloth, and a liquid in which SiO 2 fine particles and other abrasive grains are suspended in a weak alkaline liquid is used as the polishing slurry. The The finish polishing slurry usually further contains 10 ppm or more of added organic matter, and this added organic matter has the effect of suppressing and controlling the chemical reaction, increasing the liquid viscosity, and preventing haze and scratches.
[0003]
[Problems to be solved by the invention]
However, in the above-described finish polishing using the polishing cloth and the polishing slurry, the removal efficiency of the unevenness of the wavelength component in the range of 5 μm to 1 mm due to the etching remaining after the rough polishing is poor, and the microroughness in this range is reduced. It took a long time to polish.
Further, the polishing slurry used for finish polishing is affected by a natural oxide film grown on the polishing surface and organic substances attached during polishing. For this reason, there is a problem that the time for starting the polishing reaction is delayed, and the surface quality becomes unstable in a short time polishing.
An object of the present invention is to provide a semiconductor wafer finish polishing method that reduces the microroughness of the wafer surface in a short time and stabilizes the final surface quality.
[0004]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method for final polishing a semiconductor wafer in which a polishing slurry is interposed between a semiconductor wafer and a polishing cloth to polish the wafer to determine a final surface quality of the wafer surface. After polishing the wafer with a polishing slurry in which the surface layer of 5% or more is made of suede and alkaline, and the content of the added organic substance consisting of one or both of polyvinyl alcohol and hydroxyethyl cellulose is less than 10 ppm, The wafer is further polished using a polishing slurry having a surface layer with a compressibility of 5% or more and a polishing cloth made of suede and alkaline, and containing at least 10 ppm of an added organic substance made of polyvinyl alcohol or hydroxyethyl cellulose. Of semiconductor wafers characterized by It is a raised polishing method.
In the invention according to claim 1, paying attention to the compressibility of the polishing cloth and the organic matter contained in the polishing slurry, the polishing cloth comprising a suede surface layer having a compressibility of 5% or more, which is different from the combination used in the conventional finish polishing. And a polishing slurry having a surface layer with a compressibility of 5% or more and a polishing cloth made of suede and having a content of additive organics of 10 ppm or more. A final polishing is performed to further polish the wafer using. In the combination of the previous stage polishing, the polishing reaction start is accelerated by using a polishing slurry having an additive organic substance content of less than 10 ppm that suppresses chemical reaction, and the remaining after rough polishing by using a relatively soft polishing cloth. The removal efficiency of the unevenness of the wavelength component in the range of 5 μm to 1 mm due to the etching to be performed can be increased, and the final surface quality of the wafer is stabilized by the short-time polishing.
[0005]
In the combination of the subsequent polishing , the microroughness can be further reduced by performing polishing corresponding to conventional finish polishing.
[0006]
Further, when the polishing slurry contains the organic substance, the polishing reaction can be more effectively suppressed and controlled.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described.
Polishing cloth of the present invention include scan Wade. Base fabric of the scan Wade is polyurethanes is usually used. The compressibility of the polishing cloth is determined by a method based on JIS L-1096. Specifically using known automatic compression rate measuring unit, the thickness T 1 of Part 1 minute after measured by adding the initial load L 0 (300g / cm 2) , simultaneously load and the measured L 1 (1800 g / cm 2 ), and after 1 minute, the thickness T 2 is measured, and the compression rate is obtained by the following formula (1) based on the T 1 and T 2 .
[0008]
Compression rate (%) = {(T 1 −T 2 ) / T 1 } × 100 (1)
A single-side polishing method is usually used for the finish polishing method of the present invention. A single-side polishing method will be described with reference to FIG. The polishing apparatus 10 includes a rotating surface plate 11 and a wafer holder 12. The rotating surface plate 11 is a large disk and is rotated by a shaft 13 connected to the center of the bottom surface. A polishing cloth 14 is affixed to the upper surface of the rotating surface plate 11. The wafer holder 12 includes a pressure head 12a and a shaft 12b connected to the pressure head 12a and rotating the pressure head 12a. A polishing plate 16 is attached to the lower surface of the pressure head 12a. A plurality of semiconductor wafers 17 are attached to the lower surface of the polishing plate 16. A pipe 19 for supplying the polishing slurry 18 is provided on the upper part of the rotating surface plate 11. When the semiconductor wafer 17 is polished by the polishing apparatus 10, the pressure head 12 a is lowered and a predetermined pressure is applied to the semiconductor wafer 17 to hold the wafer 17. While supplying the polishing slurry 18 from the pipe 19 to the polishing pad 14, the pressure head 12 a and the rotating surface plate 11 are rotated in the same direction to polish the surface of the wafer 17 flatly.
[0009]
Next, finish polishing by such an apparatus will be described .
[0010]
The first polishing cloth Ken compression ratio of 5% or more of the surface layer is Ru suede Tona to Migakununo, the content of the added organic matter be alkaline in the polishing slurry to polish the wafer using a Migaku Ken slurry of less than 10 ppm. It is preferred that The compression ratio 10-20% of the surface layer is polished wafers with the content of the added organic matter a Migaku Ken cloth and alkaline Ru suede Tona is a Migaku Ken slurry of less than 10 ppm. If the additive organic content exceeds 10 ppm, the chemical reaction suppressing effect becomes too strong, resulting in a problem that the polishing rate is lowered and the roughness removal efficiency is lowered. By polishing with this combination , the removal efficiency of the wavelength component of 5 μm to 1 mm of the irregularities on the wafer surface can be enhanced, and the influence of the natural oxide film and the attached organic matter grown on the polished surface can be quickly removed.
[0011]
Then, following the polishing, the content of the compression ratio of 5% or more of the surface layer is added organics a Migaku Ken cloth and alkaline Ru suede Tona to polish the wafer using the above Migaku Ken slurry 10 ppm. It is preferable to polish the wafer using a polishing slurry having a surface layer with a compression rate of 10 to 20% and a polishing cloth made of suede and alkaline, and an additive organic content of 100 ppm to 1%. In performing this Migaku Ken can be further reduced microroughness of the wafer surface.
[0012]
【Example】
Next, examples of the present invention will be described.
< Example 1 >
First, a silicon wafer that has been subjected to a rough polishing step is prepared as a semiconductor wafer, and a polishing cloth whose surface layer is made of suede and a polishing cloth having a compressibility of 5% or more and SiO 2 abrasive particles to which an organic substance is added are commercially available. A polishing pressure of 1.96 × 10 4 Pa using a polishing apparatus shown in FIG. 1 using an alkaline polishing slurry prepared by diluting an alkaline polishing slurry stock solution with pure water so that the content of the added organic material is 100 ppm or more , the finish polishing was Tsu 3 minutes row at a relative speed 1.0m / s of the polishing pad and the wafer. Diluting a polishing slurry stock solution of alkaline to continue stomach abrasive particles of the SiO 2 to the silicon wafer surface layer is not compressibility consisting suede was added 5% or more of the polishing cloth and organic matter is commercially available was dispersed in pure water Then, final polishing was further performed for 3 minutes under the same polishing conditions as above using the alkaline polishing slurry to which no organic matter was added .
[0013]
<Comparative Example 1>
A commercially available alkaline solution in which a coarsely polished silicon wafer was prepared in the same manner as in Example 1, and a polishing cloth having a surface layer made of suede and having a compressibility of 5% or more and SiO 2 abrasive particles to which no organic matter was added was dispersed. 1 using a polishing slurry shown in FIG. 1 using an alkaline polishing slurry prepared by diluting a stock slurry for polishing with pure water to which organic substances are not added , a polishing pressure of 1.96 × 10 4 Pa, and a relative speed of a polishing cloth and a wafer Final polishing was performed at 1.0 m / s for 6 minutes.
<Comparison evaluation>
The surface roughness power spectrum (Power Spectral Density, hereinafter referred to as PSD) is measured on the surface of the finished silicon wafer using an optical non-contact profiler, and the square root average of wavelength of 100 μm or less is obtained from the obtained PSD. The roughness (root-mean-square roughness, hereinafter referred to as Rms) was obtained. The PSD obtained in Example 1及 beauty Comparative Example 1 in FIG. 2, showing the Rms in Table 1. Incidentally, in FIG. 2 shows the PSD obtained from another in the final polishing prior to the wafer surface having been subjected to the rough polishing step of the PSD curve of Example 1及 beauty Comparative Example 1 and the reference value.
Note that PSD is obtained by decomposing a surface roughness profile into components for each spatial frequency by Fourier transform. Rms is the square root of the PSD integrated in a certain spatial frequency range.
[0014]
[Table 1]
Figure 0003750466
[0015]
Table 1 has decreased Rms value in the embodiment 1 than against obvious Comparative Example 1 As it can be seen that the roughness of the wafer surface in a short time of polishing is reduced.
Further, in the embodiment 1 with respect to Comparative Example 1 from 2 has become small PSD strength in the range of spatial frequencies 1 × 10 -2 ~1 × 10 -1 (μm -1), microroughness is reduced You can see that
[0016]
【The invention's effect】
As described above, according to the present invention, final polishing of a semiconductor wafer is performed with a polishing cloth having a surface layer made of suede having a compression rate of 5% or more and alkaline, and is made of one or both of polyvinyl alcohol and hydroxyethyl cellulose. After polishing with a combination of polishing slurries with an additive organic content of less than 10 ppm, the surface layer with a compressibility of 5% or more is a polishing cloth made of suede and alkaline, and consists of one or both of polyvinyl alcohol and hydroxyethyl cellulose. Since the wafer is further polished using a polishing slurry having an additive organic content of 10 ppm or more, the microroughness of the wafer surface can be reduced in a short time and the final surface quality can be stabilized.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a single-side polishing apparatus for a semiconductor substrate.
FIG. 2 shows the surface roughness power spectrum in a spatial frequency of Example 1及 beauty Comparative Example 1.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Single-side polish apparatus 11 Rotating surface plate 12 Wafer holder 12a Pressure head 12b Shaft 13 Shaft 14 Polishing cloth 16 Polishing plate 17 Semiconductor wafer 18 Polishing slurry 19 Piping

Claims (1)

半導体ウェーハと研磨布との間に研磨スラリーを介在させて前記ウェーハを研磨して前記ウェーハの表面の最終的な面質を決定する半導体ウェーハの仕上げ研磨方法において、
圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であってポリビニルアルコール又はヒドロキシエチルセルロースのいずれか一方またはその双方からなる添加有機物の含有率が10ppm未満の研磨スラリーを用いて前記ウェーハを研磨した後に、圧縮率5%以上の表層がスウェードからなる研磨布とアルカリ性であってポリビニルアルコール又はヒドロキシエチルセルロースのいずれか一方またはその双方からなる添加有機物の含有率が10ppm以上の研磨スラリーを用いて前記ウェーハを更に研磨することを特徴とする半導体ウェーハの仕上げ研磨方法
In a final polishing method for a semiconductor wafer, in which a polishing slurry is interposed between a semiconductor wafer and a polishing cloth to polish the wafer and determine a final surface quality of the surface of the wafer,
Polishing the wafer using a polishing slurry having a surface layer with a compressibility of 5% or more and a polishing cloth made of suede and alkaline and containing less than 10 ppm of an added organic substance made of either polyvinyl alcohol or hydroxyethyl cellulose Then, the surface layer having a compressibility of 5% or more is a polishing cloth made of suede, and the polishing slurry is alkaline, and the content of the added organic substance consisting of either one or both of polyvinyl alcohol and hydroxyethyl cellulose is 10 ppm or more. A method for final polishing a semiconductor wafer, further comprising polishing the wafer .
JP2000049395A 2000-02-25 2000-02-25 Semiconductor wafer finish polishing method Expired - Fee Related JP3750466B2 (en)

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